mirror of
https://github.com/corundum/corundum.git
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452 lines
14 KiB
Verilog
452 lines
14 KiB
Verilog
/*
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Copyright (c) 2021 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Statistics for PCIe interface
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*/
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module stats_pcie_if #
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(
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// TLP segment header width
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parameter TLP_HDR_WIDTH = 128,
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// TLP segment count
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parameter TLP_SEG_COUNT = 1,
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// Statistics counter increment width (bits)
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parameter STAT_INC_WIDTH = 24,
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// Statistics counter ID width (bits)
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parameter STAT_ID_WIDTH = 5,
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// Statistics counter update period (cycles)
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parameter UPDATE_PERIOD = 1024
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)
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(
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input wire clk,
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input wire rst,
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/*
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* monitor input (request to BAR)
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*/
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input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_req_tlp_hdr,
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input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_valid,
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input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_sop,
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input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_eop,
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/*
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* monitor input (completion to DMA)
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*/
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input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_cpl_tlp_hdr,
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input wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_valid,
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input wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_sop,
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input wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_eop,
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/*
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* monitor input (read request from DMA)
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*/
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input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_rd_req_tlp_hdr,
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input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_valid,
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input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_sop,
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input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_eop,
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/*
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* monitor input (write request from DMA)
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*/
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input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_wr_req_tlp_hdr,
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input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_valid,
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input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_sop,
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input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_eop,
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/*
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* monitor input (completion from BAR)
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*/
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input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_cpl_tlp_hdr,
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input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_valid,
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input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_sop,
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input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_eop,
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/*
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* Statistics output
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*/
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output wire [STAT_INC_WIDTH-1:0] m_axis_stat_tdata,
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output wire [STAT_ID_WIDTH-1:0] m_axis_stat_tid,
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output wire m_axis_stat_tvalid,
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input wire m_axis_stat_tready,
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/*
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* Control inputs
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*/
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input wire update
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);
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wire stat_rx_req_tlp_mem_rd;
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wire stat_rx_req_tlp_mem_wr;
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wire stat_rx_req_tlp_io;
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wire stat_rx_req_tlp_cfg;
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wire stat_rx_req_tlp_msg;
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wire stat_rx_req_tlp_cpl;
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wire stat_rx_req_tlp_cpl_ur;
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wire stat_rx_req_tlp_cpl_ca;
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wire stat_rx_req_tlp_atomic;
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wire stat_rx_req_tlp_ep;
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wire [2:0] stat_rx_req_tlp_hdr_dw;
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wire [10:0] stat_rx_req_tlp_req_dw;
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wire [10:0] stat_rx_req_tlp_payload_dw;
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wire [10:0] stat_rx_req_tlp_cpl_dw;
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stats_pcie_tlp #(
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.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
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.TLP_SEG_COUNT(TLP_SEG_COUNT)
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)
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stats_pcie_rx_req_tlp_inst (
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.clk(clk),
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.rst(rst),
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/*
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* TLP monitor input
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*/
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.tlp_hdr(rx_req_tlp_hdr),
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.tlp_valid(rx_req_tlp_valid),
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.tlp_sop(rx_req_tlp_sop),
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.tlp_eop(rx_req_tlp_eop),
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/*
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* Statistics outputs
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*/
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.stat_tlp_mem_rd(stat_rx_req_tlp_mem_rd),
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.stat_tlp_mem_wr(stat_rx_req_tlp_mem_wr),
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.stat_tlp_io(stat_rx_req_tlp_io),
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.stat_tlp_cfg(stat_rx_req_tlp_cfg),
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.stat_tlp_msg(stat_rx_req_tlp_msg),
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.stat_tlp_cpl(stat_rx_req_tlp_cpl),
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.stat_tlp_cpl_ur(stat_rx_req_tlp_cpl_ur),
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.stat_tlp_cpl_ca(stat_rx_req_tlp_cpl_ca),
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.stat_tlp_atomic(stat_rx_req_tlp_atomic),
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.stat_tlp_ep(stat_rx_req_tlp_ep),
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.stat_tlp_hdr_dw(stat_rx_req_tlp_hdr_dw),
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.stat_tlp_req_dw(stat_rx_req_tlp_req_dw),
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.stat_tlp_payload_dw(stat_rx_req_tlp_payload_dw),
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.stat_tlp_cpl_dw(stat_rx_req_tlp_cpl_dw)
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);
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wire stat_rx_cpl_tlp_mem_rd;
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wire stat_rx_cpl_tlp_mem_wr;
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wire stat_rx_cpl_tlp_io;
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wire stat_rx_cpl_tlp_cfg;
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wire stat_rx_cpl_tlp_msg;
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wire stat_rx_cpl_tlp_cpl;
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wire stat_rx_cpl_tlp_cpl_ur;
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wire stat_rx_cpl_tlp_cpl_ca;
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wire stat_rx_cpl_tlp_atomic;
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wire stat_rx_cpl_tlp_ep;
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wire [2:0] stat_rx_cpl_tlp_hdr_dw;
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wire [10:0] stat_rx_cpl_tlp_req_dw;
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wire [10:0] stat_rx_cpl_tlp_payload_dw;
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wire [10:0] stat_rx_cpl_tlp_cpl_dw;
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stats_pcie_tlp #(
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.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
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.TLP_SEG_COUNT(TLP_SEG_COUNT)
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)
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stats_pcie_rx_cpl_tlp_inst (
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.clk(clk),
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.rst(rst),
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/*
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* TLP monitor input
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*/
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.tlp_hdr(rx_cpl_tlp_hdr),
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.tlp_valid(rx_cpl_tlp_valid),
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.tlp_sop(rx_cpl_tlp_sop),
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.tlp_eop(rx_cpl_tlp_eop),
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/*
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* Statistics outputs
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*/
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.stat_tlp_mem_rd(stat_rx_cpl_tlp_mem_rd),
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.stat_tlp_mem_wr(stat_rx_cpl_tlp_mem_wr),
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.stat_tlp_io(stat_rx_cpl_tlp_io),
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.stat_tlp_cfg(stat_rx_cpl_tlp_cfg),
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.stat_tlp_msg(stat_rx_cpl_tlp_msg),
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.stat_tlp_cpl(stat_rx_cpl_tlp_cpl),
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.stat_tlp_cpl_ur(stat_rx_cpl_tlp_cpl_ur),
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.stat_tlp_cpl_ca(stat_rx_cpl_tlp_cpl_ca),
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.stat_tlp_atomic(stat_rx_cpl_tlp_atomic),
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.stat_tlp_ep(stat_rx_cpl_tlp_ep),
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.stat_tlp_hdr_dw(stat_rx_cpl_tlp_hdr_dw),
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.stat_tlp_req_dw(stat_rx_cpl_tlp_req_dw),
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.stat_tlp_payload_dw(stat_rx_cpl_tlp_payload_dw),
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.stat_tlp_cpl_dw(stat_rx_cpl_tlp_cpl_dw)
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);
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wire [10:0] stat_rx_tlp_mem_rd = stat_rx_req_tlp_mem_rd;
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wire [10:0] stat_rx_tlp_mem_wr = stat_rx_req_tlp_mem_wr;
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wire [10:0] stat_rx_tlp_io = stat_rx_req_tlp_io;
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wire [10:0] stat_rx_tlp_cfg = stat_rx_req_tlp_cfg;
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wire [10:0] stat_rx_tlp_msg = stat_rx_req_tlp_msg;
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wire [10:0] stat_rx_tlp_cpl = stat_rx_cpl_tlp_cpl;
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wire [10:0] stat_rx_tlp_cpl_ur = stat_rx_cpl_tlp_cpl_ur;
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wire [10:0] stat_rx_tlp_cpl_ca = stat_rx_cpl_tlp_cpl_ca;
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wire [10:0] stat_rx_tlp_atomic = stat_rx_req_tlp_atomic;
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wire [10:0] stat_rx_tlp_ep = stat_rx_req_tlp_ep + stat_rx_cpl_tlp_ep;
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wire [10:0] stat_rx_tlp_hdr_dw = stat_rx_req_tlp_hdr_dw + stat_rx_cpl_tlp_hdr_dw;
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wire [10:0] stat_rx_tlp_req_dw = stat_rx_req_tlp_req_dw;
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wire [10:0] stat_rx_tlp_payload_dw = stat_rx_req_tlp_payload_dw;
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wire [10:0] stat_rx_tlp_cpl_dw = stat_rx_cpl_tlp_cpl_dw;
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wire stat_tx_rd_req_tlp_mem_rd;
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wire stat_tx_rd_req_tlp_mem_wr;
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wire stat_tx_rd_req_tlp_io;
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wire stat_tx_rd_req_tlp_cfg;
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wire stat_tx_rd_req_tlp_msg;
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wire stat_tx_rd_req_tlp_cpl;
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wire stat_tx_rd_req_tlp_cpl_ur;
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wire stat_tx_rd_req_tlp_cpl_ca;
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wire stat_tx_rd_req_tlp_atomic;
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wire stat_tx_rd_req_tlp_ep;
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wire [2:0] stat_tx_rd_req_tlp_hdr_dw;
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wire [10:0] stat_tx_rd_req_tlp_req_dw;
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wire [10:0] stat_tx_rd_req_tlp_payload_dw;
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wire [10:0] stat_tx_rd_req_tlp_cpl_dw;
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stats_pcie_tlp #(
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.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
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.TLP_SEG_COUNT(TLP_SEG_COUNT)
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)
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stats_pcie_tx_rd_req_tlp_inst (
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.clk(clk),
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.rst(rst),
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/*
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* TLP monitor input
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*/
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.tlp_hdr(tx_rd_req_tlp_hdr),
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.tlp_valid(tx_rd_req_tlp_valid),
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.tlp_sop(tx_rd_req_tlp_sop),
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.tlp_eop(tx_rd_req_tlp_eop),
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/*
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* Statistics outputs
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*/
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.stat_tlp_mem_rd(stat_tx_rd_req_tlp_mem_rd),
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.stat_tlp_mem_wr(stat_tx_rd_req_tlp_mem_wr),
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.stat_tlp_io(stat_tx_rd_req_tlp_io),
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.stat_tlp_cfg(stat_tx_rd_req_tlp_cfg),
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.stat_tlp_msg(stat_tx_rd_req_tlp_msg),
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.stat_tlp_cpl(stat_tx_rd_req_tlp_cpl),
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.stat_tlp_cpl_ur(stat_tx_rd_req_tlp_cpl_ur),
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.stat_tlp_cpl_ca(stat_tx_rd_req_tlp_cpl_ca),
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.stat_tlp_atomic(stat_tx_rd_req_tlp_atomic),
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.stat_tlp_ep(stat_tx_rd_req_tlp_ep),
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.stat_tlp_hdr_dw(stat_tx_rd_req_tlp_hdr_dw),
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.stat_tlp_req_dw(stat_tx_rd_req_tlp_req_dw),
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.stat_tlp_payload_dw(stat_tx_rd_req_tlp_payload_dw),
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.stat_tlp_cpl_dw(stat_tx_rd_req_tlp_cpl_dw)
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);
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wire stat_tx_wr_req_tlp_mem_rd;
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wire stat_tx_wr_req_tlp_mem_wr;
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wire stat_tx_wr_req_tlp_io;
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wire stat_tx_wr_req_tlp_cfg;
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wire stat_tx_wr_req_tlp_msg;
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wire stat_tx_wr_req_tlp_cpl;
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wire stat_tx_wr_req_tlp_cpl_ur;
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wire stat_tx_wr_req_tlp_cpl_ca;
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wire stat_tx_wr_req_tlp_atomic;
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wire stat_tx_wr_req_tlp_ep;
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wire [2:0] stat_tx_wr_req_tlp_hdr_dw;
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wire [10:0] stat_tx_wr_req_tlp_req_dw;
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wire [10:0] stat_tx_wr_req_tlp_payload_dw;
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wire [10:0] stat_tx_wr_req_tlp_cpl_dw;
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stats_pcie_tlp #(
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.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
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.TLP_SEG_COUNT(TLP_SEG_COUNT)
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)
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stats_pcie_tx_wr_req_tlp_inst (
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.clk(clk),
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.rst(rst),
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/*
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* TLP monitor input
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*/
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.tlp_hdr(tx_wr_req_tlp_hdr),
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.tlp_valid(tx_wr_req_tlp_valid),
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.tlp_sop(tx_wr_req_tlp_sop),
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.tlp_eop(tx_wr_req_tlp_eop),
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/*
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* Statistics outputs
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*/
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.stat_tlp_mem_rd(stat_tx_wr_req_tlp_mem_rd),
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.stat_tlp_mem_wr(stat_tx_wr_req_tlp_mem_wr),
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.stat_tlp_io(stat_tx_wr_req_tlp_io),
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.stat_tlp_cfg(stat_tx_wr_req_tlp_cfg),
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.stat_tlp_msg(stat_tx_wr_req_tlp_msg),
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.stat_tlp_cpl(stat_tx_wr_req_tlp_cpl),
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.stat_tlp_cpl_ur(stat_tx_wr_req_tlp_cpl_ur),
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.stat_tlp_cpl_ca(stat_tx_wr_req_tlp_cpl_ca),
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.stat_tlp_atomic(stat_tx_wr_req_tlp_atomic),
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.stat_tlp_ep(stat_tx_wr_req_tlp_ep),
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.stat_tlp_hdr_dw(stat_tx_wr_req_tlp_hdr_dw),
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.stat_tlp_req_dw(stat_tx_wr_req_tlp_req_dw),
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.stat_tlp_payload_dw(stat_tx_wr_req_tlp_payload_dw),
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.stat_tlp_cpl_dw(stat_tx_wr_req_tlp_cpl_dw)
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);
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wire stat_tx_cpl_tlp_mem_rd;
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wire stat_tx_cpl_tlp_mem_wr;
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wire stat_tx_cpl_tlp_io;
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wire stat_tx_cpl_tlp_cfg;
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wire stat_tx_cpl_tlp_msg;
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wire stat_tx_cpl_tlp_cpl;
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wire stat_tx_cpl_tlp_cpl_ur;
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wire stat_tx_cpl_tlp_cpl_ca;
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wire stat_tx_cpl_tlp_atomic;
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wire stat_tx_cpl_tlp_ep;
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wire [2:0] stat_tx_cpl_tlp_hdr_dw;
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wire [10:0] stat_tx_cpl_tlp_req_dw;
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wire [10:0] stat_tx_cpl_tlp_payload_dw;
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wire [10:0] stat_tx_cpl_tlp_cpl_dw;
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stats_pcie_tlp #(
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.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
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.TLP_SEG_COUNT(TLP_SEG_COUNT)
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)
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stats_pcie_tx_cpl_tlp_inst (
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.clk(clk),
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.rst(rst),
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/*
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* TLP monitor input
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*/
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.tlp_hdr(tx_cpl_tlp_hdr),
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.tlp_valid(tx_cpl_tlp_valid),
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.tlp_sop(tx_cpl_tlp_sop),
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.tlp_eop(tx_cpl_tlp_eop),
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/*
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* Statistics outputs
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*/
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.stat_tlp_mem_rd(stat_tx_cpl_tlp_mem_rd),
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.stat_tlp_mem_wr(stat_tx_cpl_tlp_mem_wr),
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.stat_tlp_io(stat_tx_cpl_tlp_io),
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.stat_tlp_cfg(stat_tx_cpl_tlp_cfg),
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.stat_tlp_msg(stat_tx_cpl_tlp_msg),
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.stat_tlp_cpl(stat_tx_cpl_tlp_cpl),
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.stat_tlp_cpl_ur(stat_tx_cpl_tlp_cpl_ur),
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.stat_tlp_cpl_ca(stat_tx_cpl_tlp_cpl_ca),
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.stat_tlp_atomic(stat_tx_cpl_tlp_atomic),
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.stat_tlp_ep(stat_tx_cpl_tlp_ep),
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.stat_tlp_hdr_dw(stat_tx_cpl_tlp_hdr_dw),
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.stat_tlp_req_dw(stat_tx_cpl_tlp_req_dw),
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.stat_tlp_payload_dw(stat_tx_cpl_tlp_payload_dw),
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.stat_tlp_cpl_dw(stat_tx_cpl_tlp_cpl_dw)
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);
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wire [10:0] stat_tx_tlp_mem_rd = stat_tx_rd_req_tlp_mem_rd;
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wire [10:0] stat_tx_tlp_mem_wr = stat_tx_wr_req_tlp_mem_wr;
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wire [10:0] stat_tx_tlp_io = 0;
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wire [10:0] stat_tx_tlp_cfg = 0;
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wire [10:0] stat_tx_tlp_msg = 0;
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wire [10:0] stat_tx_tlp_cpl = stat_tx_cpl_tlp_cpl;
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wire [10:0] stat_tx_tlp_cpl_ur = stat_tx_cpl_tlp_cpl_ur;
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wire [10:0] stat_tx_tlp_cpl_ca = stat_tx_cpl_tlp_cpl_ca;
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wire [10:0] stat_tx_tlp_atomic = 0;
|
|
wire [10:0] stat_tx_tlp_ep = 0;
|
|
wire [10:0] stat_tx_tlp_hdr_dw = stat_tx_rd_req_tlp_hdr_dw + stat_tx_wr_req_tlp_hdr_dw + stat_tx_cpl_tlp_hdr_dw;
|
|
wire [10:0] stat_tx_tlp_req_dw = stat_tx_rd_req_tlp_req_dw;
|
|
wire [10:0] stat_tx_tlp_payload_dw = stat_tx_wr_req_tlp_payload_dw;
|
|
wire [10:0] stat_tx_tlp_cpl_dw = stat_tx_cpl_tlp_cpl_dw;
|
|
|
|
stats_collect #(
|
|
.COUNT(32),
|
|
.INC_WIDTH(11),
|
|
.STAT_INC_WIDTH(STAT_INC_WIDTH),
|
|
.STAT_ID_WIDTH(5),
|
|
.UPDATE_PERIOD(UPDATE_PERIOD)
|
|
)
|
|
stats_collect_inst (
|
|
.clk(clk),
|
|
.rst(rst),
|
|
|
|
/*
|
|
* Increment inputs
|
|
*/
|
|
.stat_inc({
|
|
11'd0, // index 31
|
|
11'd0, // index 30
|
|
stat_tx_tlp_cpl_dw, // index 29
|
|
stat_tx_tlp_payload_dw, // index 28
|
|
stat_tx_tlp_req_dw, // index 27
|
|
stat_tx_tlp_hdr_dw, // index 26
|
|
stat_tx_tlp_ep, // index 25
|
|
stat_tx_tlp_atomic, // index 24
|
|
stat_tx_tlp_cpl_ca, // index 23
|
|
stat_tx_tlp_cpl_ur, // index 22
|
|
stat_tx_tlp_cpl, // index 21
|
|
stat_tx_tlp_msg, // index 20
|
|
stat_tx_tlp_cfg, // index 19
|
|
stat_tx_tlp_io, // index 18
|
|
stat_tx_tlp_mem_wr, // index 17
|
|
stat_tx_tlp_mem_rd, // index 16
|
|
11'd0, // index 15
|
|
11'd0, // index 14
|
|
stat_rx_tlp_cpl_dw, // index 13
|
|
stat_rx_tlp_payload_dw, // index 12
|
|
stat_rx_tlp_req_dw, // index 11
|
|
stat_rx_tlp_hdr_dw, // index 10
|
|
stat_rx_tlp_ep, // index 9
|
|
stat_rx_tlp_atomic, // index 8
|
|
stat_rx_tlp_cpl_ca, // index 7
|
|
stat_rx_tlp_cpl_ur, // index 6
|
|
stat_rx_tlp_cpl, // index 5
|
|
stat_rx_tlp_msg, // index 4
|
|
stat_rx_tlp_cfg, // index 3
|
|
stat_rx_tlp_io, // index 2
|
|
stat_rx_tlp_mem_wr, // index 1
|
|
stat_rx_tlp_mem_rd // index 0
|
|
}),
|
|
.stat_valid({32{1'b1}}),
|
|
|
|
/*
|
|
* Statistics increment output
|
|
*/
|
|
.m_axis_stat_tdata(m_axis_stat_tdata),
|
|
.m_axis_stat_tid(m_axis_stat_tid),
|
|
.m_axis_stat_tvalid(m_axis_stat_tvalid),
|
|
.m_axis_stat_tready(m_axis_stat_tready),
|
|
|
|
/*
|
|
* Control inputs
|
|
*/
|
|
.update(update)
|
|
);
|
|
|
|
endmodule
|
|
|
|
`resetall
|