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319 lines
14 KiB
Verilog
319 lines
14 KiB
Verilog
/*
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Copyright (c) 2021 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* PCIe TLP multiplexer
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*/
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module pcie_tlp_mux #
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(
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// Input count
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parameter PORTS = 2,
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// TLP segment count
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parameter TLP_SEG_COUNT = 1,
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// TLP segment data width
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parameter TLP_SEG_DATA_WIDTH = 256,
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// TLP segment strobe width
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parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32,
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// TLP segment header width
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parameter TLP_SEG_HDR_WIDTH = 128,
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// select round robin arbitration
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parameter ARB_TYPE_ROUND_ROBIN = 0,
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// LSB priority selection
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parameter ARB_LSB_HIGH_PRIORITY = 1
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)
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(
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input wire clk,
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input wire rst,
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/*
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* TLP input
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*/
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input wire [PORTS*TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] in_tlp_data,
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input wire [PORTS*TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] in_tlp_strb,
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input wire [PORTS*TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] in_tlp_hdr,
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input wire [PORTS*TLP_SEG_COUNT*3-1:0] in_tlp_bar_id,
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input wire [PORTS*TLP_SEG_COUNT*8-1:0] in_tlp_func_num,
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input wire [PORTS*TLP_SEG_COUNT*4-1:0] in_tlp_error,
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input wire [PORTS*TLP_SEG_COUNT-1:0] in_tlp_valid,
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input wire [PORTS*TLP_SEG_COUNT-1:0] in_tlp_sop,
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input wire [PORTS*TLP_SEG_COUNT-1:0] in_tlp_eop,
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output wire [PORTS-1:0] in_tlp_ready,
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/*
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* TLP output
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*/
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output wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] out_tlp_data,
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output wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] out_tlp_strb,
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output wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] out_tlp_hdr,
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output wire [TLP_SEG_COUNT*3-1:0] out_tlp_bar_id,
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output wire [TLP_SEG_COUNT*8-1:0] out_tlp_func_num,
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output wire [TLP_SEG_COUNT*4-1:0] out_tlp_error,
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output wire [TLP_SEG_COUNT-1:0] out_tlp_valid,
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output wire [TLP_SEG_COUNT-1:0] out_tlp_sop,
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output wire [TLP_SEG_COUNT-1:0] out_tlp_eop,
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input wire out_tlp_ready
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);
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parameter CL_PORTS = $clog2(PORTS);
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// check configuration
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initial begin
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if (TLP_SEG_COUNT != 1) begin
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$error("Error: TLP segment count must be 1 (instance %m)");
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$finish;
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end
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if (TLP_SEG_HDR_WIDTH != 128) begin
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$error("Error: TLP segment header width must be 128 (instance %m)");
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$finish;
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end
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if (TLP_SEG_STRB_WIDTH*32 != TLP_SEG_DATA_WIDTH) begin
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$error("Error: PCIe interface requires dword (32-bit) granularity (instance %m)");
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$finish;
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end
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end
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wire [PORTS-1:0] request;
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wire [PORTS-1:0] acknowledge;
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wire [PORTS-1:0] grant;
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wire grant_valid;
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wire [CL_PORTS-1:0] grant_encoded;
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// input registers to pipeline arbitration delay
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reg [PORTS*TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] in_tlp_data_reg = 0;
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reg [PORTS*TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] in_tlp_strb_reg = 0;
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reg [PORTS*TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] in_tlp_hdr_reg = 0;
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reg [PORTS*TLP_SEG_COUNT*3-1:0] in_tlp_bar_id_reg = 0;
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reg [PORTS*TLP_SEG_COUNT*8-1:0] in_tlp_func_num_reg = 0;
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reg [PORTS*TLP_SEG_COUNT*4-1:0] in_tlp_error_reg = 0;
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reg [PORTS*TLP_SEG_COUNT-1:0] in_tlp_valid_reg = 0;
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reg [PORTS*TLP_SEG_COUNT-1:0] in_tlp_sop_reg = 0;
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reg [PORTS*TLP_SEG_COUNT-1:0] in_tlp_eop_reg = 0;
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// internal datapath
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reg [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] out_tlp_data_int;
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reg [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] out_tlp_strb_int;
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reg [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] out_tlp_hdr_int;
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reg [TLP_SEG_COUNT*3-1:0] out_tlp_bar_id_int;
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reg [TLP_SEG_COUNT*8-1:0] out_tlp_func_num_int;
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reg [TLP_SEG_COUNT*4-1:0] out_tlp_error_int;
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reg [TLP_SEG_COUNT-1:0] out_tlp_valid_int;
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reg [TLP_SEG_COUNT-1:0] out_tlp_sop_int;
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reg [TLP_SEG_COUNT-1:0] out_tlp_eop_int;
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reg out_tlp_ready_int_reg = 1'b0;
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wire out_tlp_ready_int_early;
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assign in_tlp_ready = ~in_tlp_valid_reg | ({PORTS{out_tlp_ready_int_reg}} & grant);
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// mux for incoming packet
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wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] current_in_tlp_data = in_tlp_data_reg[grant_encoded*TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH +: TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH];
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wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] current_in_tlp_strb = in_tlp_strb_reg[grant_encoded*TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH +: TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH];
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wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] current_in_tlp_hdr = in_tlp_hdr_reg[grant_encoded*TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH +: TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH];
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wire [TLP_SEG_COUNT*3-1:0] current_in_tlp_bar_id = in_tlp_bar_id_reg[grant_encoded*TLP_SEG_COUNT*3 +: TLP_SEG_COUNT*3];
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wire [TLP_SEG_COUNT*8-1:0] current_in_tlp_func_num = in_tlp_func_num_reg[grant_encoded*TLP_SEG_COUNT*8 +: TLP_SEG_COUNT*8];
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wire [TLP_SEG_COUNT*4-1:0] current_in_tlp_error = in_tlp_error_reg[grant_encoded*TLP_SEG_COUNT*4 +: TLP_SEG_COUNT*4];
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wire [TLP_SEG_COUNT-1:0] current_in_tlp_valid = in_tlp_valid_reg[grant_encoded*TLP_SEG_COUNT +: TLP_SEG_COUNT];
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wire [TLP_SEG_COUNT-1:0] current_in_tlp_sop = in_tlp_sop_reg[grant_encoded*TLP_SEG_COUNT +: TLP_SEG_COUNT];
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wire [TLP_SEG_COUNT-1:0] current_in_tlp_eop = in_tlp_eop_reg[grant_encoded*TLP_SEG_COUNT +: TLP_SEG_COUNT];
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wire current_in_tlp_ready = in_tlp_ready[grant_encoded];
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// arbiter instance
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arbiter #(
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.PORTS(PORTS),
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.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
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.ARB_BLOCK(1),
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.ARB_BLOCK_ACK(1),
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.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
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)
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arb_inst (
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.clk(clk),
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.rst(rst),
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.request(request),
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.acknowledge(acknowledge),
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.grant(grant),
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.grant_valid(grant_valid),
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.grant_encoded(grant_encoded)
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);
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assign request = (in_tlp_valid_reg & ~grant) | (in_tlp_valid & grant);
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assign acknowledge = grant & in_tlp_valid_reg & {PORTS{out_tlp_ready_int_reg}} & in_tlp_eop_reg;
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always @* begin
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// pass through selected packet data
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out_tlp_data_int = current_in_tlp_data;
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out_tlp_strb_int = current_in_tlp_strb;
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out_tlp_hdr_int = current_in_tlp_hdr;
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out_tlp_bar_id_int = current_in_tlp_bar_id;
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out_tlp_func_num_int = current_in_tlp_func_num;
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out_tlp_error_int = current_in_tlp_error;
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out_tlp_valid_int = current_in_tlp_valid && out_tlp_ready_int_reg && grant_valid;
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out_tlp_sop_int = current_in_tlp_sop;
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out_tlp_eop_int = current_in_tlp_eop;
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end
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integer i;
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always @(posedge clk) begin
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// register inputs
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for (i = 0; i < PORTS; i = i + 1) begin
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if (in_tlp_ready[i]) begin
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in_tlp_data_reg[i*TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH +: TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH] <= in_tlp_data[i*TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH +: TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH];
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in_tlp_strb_reg[i*TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH +: TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH] <= in_tlp_strb[i*TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH +: TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH];
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in_tlp_hdr_reg[i*TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH +: TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH] <= in_tlp_hdr[i*TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH +: TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH];
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in_tlp_bar_id_reg[i*TLP_SEG_COUNT*3 +: TLP_SEG_COUNT*3] <= in_tlp_bar_id[i*TLP_SEG_COUNT*3 +: TLP_SEG_COUNT*3];
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in_tlp_func_num_reg[i*TLP_SEG_COUNT*8 +: TLP_SEG_COUNT*8] <= in_tlp_func_num[i*TLP_SEG_COUNT*8 +: TLP_SEG_COUNT*8];
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in_tlp_error_reg[i*TLP_SEG_COUNT*4 +: TLP_SEG_COUNT*4] <= in_tlp_error[i*TLP_SEG_COUNT*4 +: TLP_SEG_COUNT*4];
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in_tlp_valid_reg[i*TLP_SEG_COUNT +: TLP_SEG_COUNT] <= in_tlp_valid[i*TLP_SEG_COUNT +: TLP_SEG_COUNT];
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in_tlp_sop_reg[i*TLP_SEG_COUNT +: TLP_SEG_COUNT] <= in_tlp_sop[i*TLP_SEG_COUNT +: TLP_SEG_COUNT];
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in_tlp_eop_reg[i*TLP_SEG_COUNT +: TLP_SEG_COUNT] <= in_tlp_eop[i*TLP_SEG_COUNT +: TLP_SEG_COUNT];
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end
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end
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if (rst) begin
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in_tlp_valid_reg <= 0;
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end
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end
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// output datapath logic
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reg [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] out_tlp_data_reg = 0;
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reg [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] out_tlp_strb_reg = 0;
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reg [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] out_tlp_hdr_reg = 0;
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reg [TLP_SEG_COUNT*3-1:0] out_tlp_bar_id_reg = 0;
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reg [TLP_SEG_COUNT*8-1:0] out_tlp_func_num_reg = 0;
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reg [TLP_SEG_COUNT*4-1:0] out_tlp_error_reg = 0;
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reg [TLP_SEG_COUNT-1:0] out_tlp_valid_reg = 0, out_tlp_valid_next;
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reg [TLP_SEG_COUNT-1:0] out_tlp_sop_reg = 0;
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reg [TLP_SEG_COUNT-1:0] out_tlp_eop_reg = 0;
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reg [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] temp_out_tlp_data_reg = 0;
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reg [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] temp_out_tlp_strb_reg = 0;
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reg [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] temp_out_tlp_hdr_reg = 0;
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reg [TLP_SEG_COUNT*3-1:0] temp_out_tlp_bar_id_reg = 0;
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reg [TLP_SEG_COUNT*8-1:0] temp_out_tlp_func_num_reg = 0;
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reg [TLP_SEG_COUNT*4-1:0] temp_out_tlp_error_reg = 0;
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reg [TLP_SEG_COUNT-1:0] temp_out_tlp_valid_reg = 0, temp_out_tlp_valid_next;
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reg [TLP_SEG_COUNT-1:0] temp_out_tlp_sop_reg = 0;
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reg [TLP_SEG_COUNT-1:0] temp_out_tlp_eop_reg = 0;
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// datapath control
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reg store_axis_int_to_output;
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reg store_axis_int_to_temp;
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reg store_axis_temp_to_output;
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assign out_tlp_data = out_tlp_data_reg;
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assign out_tlp_strb = out_tlp_strb_reg;
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assign out_tlp_hdr = out_tlp_hdr_reg;
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assign out_tlp_bar_id = out_tlp_bar_id_reg;
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assign out_tlp_func_num = out_tlp_func_num_reg;
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assign out_tlp_error = out_tlp_error_reg;
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assign out_tlp_valid = out_tlp_valid_reg;
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assign out_tlp_sop = out_tlp_sop_reg;
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assign out_tlp_eop = out_tlp_eop_reg;
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// enable ready input next cycle if output is ready or if both output registers are empty
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assign out_tlp_ready_int_early = out_tlp_ready || (!temp_out_tlp_valid_reg && !out_tlp_valid_reg);
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always @* begin
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// transfer sink ready state to source
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out_tlp_valid_next = out_tlp_valid_reg;
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temp_out_tlp_valid_next = temp_out_tlp_valid_reg;
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store_axis_int_to_output = 1'b0;
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store_axis_int_to_temp = 1'b0;
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store_axis_temp_to_output = 1'b0;
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if (out_tlp_ready_int_reg) begin
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// input is ready
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if (out_tlp_ready || !out_tlp_valid_reg) begin
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// output is ready or currently not valid, transfer data to output
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out_tlp_valid_next = out_tlp_valid_int;
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store_axis_int_to_output = 1'b1;
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end else begin
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// output is not ready, store input in temp
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temp_out_tlp_valid_next = out_tlp_valid_int;
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store_axis_int_to_temp = 1'b1;
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end
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end else if (out_tlp_ready) begin
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// input is not ready, but output is ready
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out_tlp_valid_next = temp_out_tlp_valid_reg;
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temp_out_tlp_valid_next = 1'b0;
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store_axis_temp_to_output = 1'b1;
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end
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end
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always @(posedge clk) begin
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out_tlp_valid_reg <= out_tlp_valid_next;
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out_tlp_ready_int_reg <= out_tlp_ready_int_early;
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temp_out_tlp_valid_reg <= temp_out_tlp_valid_next;
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// datapath
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if (store_axis_int_to_output) begin
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out_tlp_data_reg <= out_tlp_data_int;
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out_tlp_strb_reg <= out_tlp_strb_int;
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out_tlp_hdr_reg <= out_tlp_hdr_int;
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out_tlp_bar_id_reg <= out_tlp_bar_id_int;
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out_tlp_func_num_reg <= out_tlp_func_num_int;
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out_tlp_error_reg <= out_tlp_error_int;
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out_tlp_sop_reg <= out_tlp_sop_int;
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out_tlp_eop_reg <= out_tlp_eop_int;
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end else if (store_axis_temp_to_output) begin
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out_tlp_data_reg <= temp_out_tlp_data_reg;
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out_tlp_strb_reg <= temp_out_tlp_strb_reg;
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out_tlp_hdr_reg <= temp_out_tlp_hdr_reg;
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out_tlp_bar_id_reg <= temp_out_tlp_bar_id_reg;
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out_tlp_func_num_reg <= temp_out_tlp_func_num_reg;
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out_tlp_error_reg <= temp_out_tlp_error_reg;
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out_tlp_sop_reg <= temp_out_tlp_sop_reg;
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out_tlp_eop_reg <= temp_out_tlp_eop_reg;
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end
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if (store_axis_int_to_temp) begin
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temp_out_tlp_data_reg <= out_tlp_data_int;
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temp_out_tlp_strb_reg <= out_tlp_strb_int;
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temp_out_tlp_hdr_reg <= out_tlp_hdr_int;
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temp_out_tlp_bar_id_reg <= out_tlp_bar_id_int;
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temp_out_tlp_func_num_reg <= out_tlp_func_num_int;
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temp_out_tlp_error_reg <= out_tlp_error_int;
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temp_out_tlp_sop_reg <= out_tlp_sop_int;
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temp_out_tlp_eop_reg <= out_tlp_eop_int;
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end
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if (rst) begin
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out_tlp_valid_reg <= 1'b0;
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out_tlp_ready_int_reg <= 1'b0;
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temp_out_tlp_valid_reg <= 1'b0;
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end
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end
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endmodule
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`resetall
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