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457 lines
15 KiB
Python
Executable File
457 lines
15 KiB
Python
Executable File
#!/usr/bin/env python
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"""
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Copyright (c) 2014-2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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"""
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from myhdl import *
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import os
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import struct
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import axis_ep
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module = 'axis_frame_join_4'
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testbench = 'test_%s' % module
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srcs = []
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srcs.append("../rtl/%s.v" % module)
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srcs.append("%s.v" % testbench)
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src = ' '.join(srcs)
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build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
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def bench():
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# Parameters
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TAG_ENABLE = 1
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TAG_WIDTH = 16
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# Inputs
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clk = Signal(bool(0))
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rst = Signal(bool(0))
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current_test = Signal(intbv(0)[8:])
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input_0_axis_tdata = Signal(intbv(0)[8:])
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input_0_axis_tvalid = Signal(bool(0))
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input_0_axis_tlast = Signal(bool(0))
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input_0_axis_tuser = Signal(bool(0))
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input_1_axis_tdata = Signal(intbv(0)[8:])
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input_1_axis_tvalid = Signal(bool(0))
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input_1_axis_tlast = Signal(bool(0))
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input_1_axis_tuser = Signal(bool(0))
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input_2_axis_tdata = Signal(intbv(0)[8:])
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input_2_axis_tvalid = Signal(bool(0))
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input_2_axis_tlast = Signal(bool(0))
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input_2_axis_tuser = Signal(bool(0))
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input_3_axis_tdata = Signal(intbv(0)[8:])
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input_3_axis_tvalid = Signal(bool(0))
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input_3_axis_tlast = Signal(bool(0))
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input_3_axis_tuser = Signal(bool(0))
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output_axis_tready = Signal(bool(0))
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tag = Signal(intbv(0)[TAG_WIDTH:])
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# Outputs
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input_0_axis_tready = Signal(bool(0))
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input_1_axis_tready = Signal(bool(0))
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input_2_axis_tready = Signal(bool(0))
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input_3_axis_tready = Signal(bool(0))
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output_axis_tdata = Signal(intbv(0)[8:])
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output_axis_tvalid = Signal(bool(0))
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output_axis_tlast = Signal(bool(0))
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output_axis_tuser = Signal(bool(0))
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busy = Signal(bool(0))
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# sources and sinks
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source_0_pause = Signal(bool(0))
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source_1_pause = Signal(bool(0))
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source_2_pause = Signal(bool(0))
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source_3_pause = Signal(bool(0))
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sink_pause = Signal(bool(0))
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source_0 = axis_ep.AXIStreamSource()
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source_0_logic = source_0.create_logic(
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clk,
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rst,
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tdata=input_0_axis_tdata,
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tvalid=input_0_axis_tvalid,
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tready=input_0_axis_tready,
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tlast=input_0_axis_tlast,
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tuser=input_0_axis_tuser,
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pause=source_0_pause,
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name='source_0'
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)
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source_1 = axis_ep.AXIStreamSource()
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source_1_logic = source_1.create_logic(
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clk,
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rst,
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tdata=input_1_axis_tdata,
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tvalid=input_1_axis_tvalid,
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tready=input_1_axis_tready,
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tlast=input_1_axis_tlast,
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tuser=input_1_axis_tuser,
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pause=source_1_pause,
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name='source_1'
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)
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source_2 = axis_ep.AXIStreamSource()
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source_2_logic = source_2.create_logic(
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clk,
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rst,
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tdata=input_2_axis_tdata,
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tvalid=input_2_axis_tvalid,
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tready=input_2_axis_tready,
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tlast=input_2_axis_tlast,
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tuser=input_2_axis_tuser,
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pause=source_2_pause,
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name='source_2'
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)
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source_3 = axis_ep.AXIStreamSource()
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source_3_logic = source_3.create_logic(
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clk,
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rst,
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tdata=input_3_axis_tdata,
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tvalid=input_3_axis_tvalid,
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tready=input_3_axis_tready,
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tlast=input_3_axis_tlast,
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tuser=input_3_axis_tuser,
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pause=source_3_pause,
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name='source_3'
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)
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sink = axis_ep.AXIStreamSink()
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sink_logic = sink.create_logic(
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clk,
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rst,
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tdata=output_axis_tdata,
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tvalid=output_axis_tvalid,
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tready=output_axis_tready,
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tlast=output_axis_tlast,
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tuser=output_axis_tuser,
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pause=sink_pause,
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name='sink'
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)
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# DUT
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if os.system(build_cmd):
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raise Exception("Error running build command")
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dut = Cosimulation(
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"vvp -m myhdl %s.vvp -lxt2" % testbench,
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clk=clk,
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rst=rst,
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current_test=current_test,
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input_0_axis_tdata=input_0_axis_tdata,
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input_0_axis_tvalid=input_0_axis_tvalid,
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input_0_axis_tready=input_0_axis_tready,
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input_0_axis_tlast=input_0_axis_tlast,
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input_0_axis_tuser=input_0_axis_tuser,
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input_1_axis_tdata=input_1_axis_tdata,
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input_1_axis_tvalid=input_1_axis_tvalid,
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input_1_axis_tready=input_1_axis_tready,
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input_1_axis_tlast=input_1_axis_tlast,
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input_1_axis_tuser=input_1_axis_tuser,
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input_2_axis_tdata=input_2_axis_tdata,
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input_2_axis_tvalid=input_2_axis_tvalid,
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input_2_axis_tready=input_2_axis_tready,
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input_2_axis_tlast=input_2_axis_tlast,
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input_2_axis_tuser=input_2_axis_tuser,
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input_3_axis_tdata=input_3_axis_tdata,
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input_3_axis_tvalid=input_3_axis_tvalid,
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input_3_axis_tready=input_3_axis_tready,
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input_3_axis_tlast=input_3_axis_tlast,
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input_3_axis_tuser=input_3_axis_tuser,
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output_axis_tdata=output_axis_tdata,
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output_axis_tvalid=output_axis_tvalid,
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output_axis_tready=output_axis_tready,
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output_axis_tlast=output_axis_tlast,
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output_axis_tuser=output_axis_tuser,
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tag=tag,
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busy=busy
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)
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@always(delay(4))
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def clkgen():
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clk.next = not clk
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@instance
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def check():
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yield delay(100)
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yield clk.posedge
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rst.next = 1
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yield clk.posedge
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rst.next = 0
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yield clk.posedge
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yield delay(100)
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yield clk.posedge
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yield clk.posedge
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tag.next = 1
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yield clk.posedge
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print("test 1: test packet")
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current_test.next = 1
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test_frame_0 = axis_ep.AXIStreamFrame(b'\x00\xAA\xBB\xCC\xDD\x00')
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test_frame_1 = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
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test_frame_2 = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
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test_frame_3 = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
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source_0.send(test_frame_0)
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source_1.send(test_frame_1)
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source_2.send(test_frame_2)
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source_3.send(test_frame_3)
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yield sink.wait()
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rx_frame = sink.recv()
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assert rx_frame.data == struct.pack('>H', tag) + test_frame_0.data + test_frame_1.data + test_frame_2.data + test_frame_3.data
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yield delay(100)
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yield clk.posedge
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print("test 2: longer packet")
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current_test.next = 2
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test_frame_0 = axis_ep.AXIStreamFrame(b'\x00' + bytearray(range(256)) + b'\x00')
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test_frame_1 = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
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test_frame_2 = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
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test_frame_3 = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
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source_0.send(test_frame_0)
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source_1.send(test_frame_1)
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source_2.send(test_frame_2)
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source_3.send(test_frame_3)
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yield sink.wait()
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rx_frame = sink.recv()
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assert rx_frame.data == struct.pack('>H', tag) + test_frame_0.data + test_frame_1.data + test_frame_2.data + test_frame_3.data
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yield delay(100)
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yield clk.posedge
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print("test 3: test packet with pauses")
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current_test.next = 3
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test_frame_0 = axis_ep.AXIStreamFrame(b'\x00\xAA\xBB\xCC\xDD\x00')
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test_frame_1 = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
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test_frame_2 = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
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test_frame_3 = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
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source_0.send(test_frame_0)
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source_1.send(test_frame_1)
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source_2.send(test_frame_2)
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source_3.send(test_frame_3)
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yield clk.posedge
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yield delay(64)
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yield clk.posedge
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source_1_pause.next = True
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yield delay(32)
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yield clk.posedge
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source_1_pause.next = False
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yield delay(64)
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yield clk.posedge
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sink_pause.next = True
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yield delay(32)
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yield clk.posedge
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sink_pause.next = False
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yield sink.wait()
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rx_frame = sink.recv()
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assert rx_frame.data == struct.pack('>H', tag) + test_frame_0.data + test_frame_1.data + test_frame_2.data + test_frame_3.data
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yield delay(100)
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yield clk.posedge
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print("test 4: back-to-back packets")
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current_test.next = 4
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test_frame_0a = axis_ep.AXIStreamFrame(b'\x00\xAA\xBB\xCC\xDD\x00')
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test_frame_0b = axis_ep.AXIStreamFrame(b'\x00\xAA\xBB\xCC\xDD\x00')
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test_frame_1a = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
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test_frame_1b = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
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test_frame_2a = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
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test_frame_2b = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
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test_frame_3a = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
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test_frame_3b = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
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source_0.send(test_frame_0a)
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source_0.send(test_frame_0b)
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source_1.send(test_frame_1a)
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source_1.send(test_frame_1b)
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source_2.send(test_frame_2a)
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source_2.send(test_frame_2b)
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source_3.send(test_frame_3a)
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source_3.send(test_frame_3b)
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yield sink.wait()
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rx_frame = sink.recv()
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assert rx_frame.data == struct.pack('>H', tag) + test_frame_0a.data + test_frame_1a.data + test_frame_2a.data + test_frame_3a.data
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yield sink.wait()
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rx_frame = sink.recv()
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assert rx_frame.data == struct.pack('>H', tag) + test_frame_0b.data + test_frame_1b.data + test_frame_2b.data + test_frame_3b.data
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yield delay(100)
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yield clk.posedge
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print("test 5: alternate pause source")
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current_test.next = 5
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test_frame_0a = axis_ep.AXIStreamFrame(b'\x00\xAA\xBB\xCC\xDD\x00')
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test_frame_0b = axis_ep.AXIStreamFrame(b'\x00\xAA\xBB\xCC\xDD\x00')
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test_frame_1a = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
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test_frame_1b = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
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test_frame_2a = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
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test_frame_2b = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
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test_frame_3a = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
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test_frame_3b = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
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source_0.send(test_frame_0a)
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source_0.send(test_frame_0b)
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source_1.send(test_frame_1a)
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source_1.send(test_frame_1b)
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source_2.send(test_frame_2a)
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source_2.send(test_frame_2b)
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source_3.send(test_frame_3a)
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source_3.send(test_frame_3b)
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yield clk.posedge
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while input_3_axis_tvalid or output_axis_tvalid:
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source_0_pause.next = True
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source_1_pause.next = True
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source_2_pause.next = True
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source_3_pause.next = True
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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source_0_pause.next = False
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source_1_pause.next = False
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source_2_pause.next = False
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source_3_pause.next = False
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yield clk.posedge
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yield sink.wait()
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rx_frame = sink.recv()
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assert rx_frame.data == struct.pack('>H', tag) + test_frame_0a.data + test_frame_1a.data + test_frame_2a.data + test_frame_3a.data
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yield sink.wait()
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rx_frame = sink.recv()
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assert rx_frame.data == struct.pack('>H', tag) + test_frame_0b.data + test_frame_1b.data + test_frame_2b.data + test_frame_3b.data
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yield delay(100)
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yield clk.posedge
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print("test 6: alternate pause sink")
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current_test.next = 6
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test_frame_0a = axis_ep.AXIStreamFrame(b'\x00\xAA\xBB\xCC\xDD\x00')
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test_frame_0b = axis_ep.AXIStreamFrame(b'\x00\xAA\xBB\xCC\xDD\x00')
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test_frame_1a = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
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test_frame_1b = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
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test_frame_2a = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
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test_frame_2b = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
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test_frame_3a = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
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test_frame_3b = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
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source_0.send(test_frame_0a)
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source_0.send(test_frame_0b)
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source_1.send(test_frame_1a)
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source_1.send(test_frame_1b)
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source_2.send(test_frame_2a)
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source_2.send(test_frame_2b)
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source_3.send(test_frame_3a)
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source_3.send(test_frame_3b)
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yield clk.posedge
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while input_3_axis_tvalid or output_axis_tvalid:
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sink_pause.next = True
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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sink_pause.next = False
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yield clk.posedge
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yield sink.wait()
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rx_frame = sink.recv()
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assert rx_frame.data == struct.pack('>H', tag) + test_frame_0a.data + test_frame_1a.data + test_frame_2a.data + test_frame_3a.data
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yield sink.wait()
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rx_frame = sink.recv()
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assert rx_frame.data == struct.pack('>H', tag) + test_frame_0b.data + test_frame_1b.data + test_frame_2b.data + test_frame_3b.data
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yield delay(100)
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yield clk.posedge
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print("test 7: tuser assert")
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current_test.next = 7
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test_frame_0 = axis_ep.AXIStreamFrame(b'\x00\xAA\xBB\xCC\xDD\x00')
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test_frame_1 = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
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test_frame_2 = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
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test_frame_3 = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
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test_frame_0.last_cycle_user = 1
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|
source_0.send(test_frame_0)
|
|
source_1.send(test_frame_1)
|
|
source_2.send(test_frame_2)
|
|
source_3.send(test_frame_3)
|
|
|
|
yield sink.wait()
|
|
rx_frame = sink.recv()
|
|
|
|
assert rx_frame.data == struct.pack('>H', tag) + test_frame_0.data + test_frame_1.data + test_frame_2.data + test_frame_3.data
|
|
assert rx_frame.last_cycle_user
|
|
|
|
yield delay(100)
|
|
|
|
raise StopSimulation
|
|
|
|
return instances()
|
|
|
|
def test_bench():
|
|
os.chdir(os.path.dirname(os.path.abspath(__file__)))
|
|
sim = Simulation(bench())
|
|
sim.run()
|
|
|
|
if __name__ == '__main__':
|
|
print("Running test...")
|
|
test_bench()
|
|
|