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78 lines
2.1 KiB
Verilog
78 lines
2.1 KiB
Verilog
/*
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Copyright (c) 2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* Pulse merge module
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*/
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module pulse_merge #
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(
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parameter INPUT_WIDTH = 2,
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parameter COUNT_WIDTH = 4
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)
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(
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input wire clk,
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input wire rst,
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input wire [INPUT_WIDTH-1:0] pulse_in,
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output wire [COUNT_WIDTH-1:0] count_out,
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output wire pulse_out
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);
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reg [COUNT_WIDTH-1:0] count_reg = {COUNT_WIDTH{1'b0}}, count_next;
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reg pulse_reg = 1'b0, pulse_next;
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assign count_out = count_reg;
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assign pulse_out = pulse_reg;
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integer i;
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always @* begin
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count_next = count_reg;
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pulse_next = count_reg > 0;
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if (count_reg > 0) begin
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count_next = count_reg - 1;
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end
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for (i = 0; i < INPUT_WIDTH; i = i + 1) begin
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count_next = count_next + pulse_in[i];
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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count_reg <= {COUNT_WIDTH{1'b0}};
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pulse_reg <= 1'b0;
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end else begin
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count_reg <= count_next;
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pulse_reg <= pulse_next;
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end
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end
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endmodule
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