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117 lines
4.7 KiB
Makefile
117 lines
4.7 KiB
Makefile
# Copyright 2020, The Regents of the University of California.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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#
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# 1. Redistributions of source code must retain the above copyright notice,
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# this list of conditions and the following disclaimer.
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#
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# 2. Redistributions in binary form must reproduce the above copyright notice,
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# this list of conditions and the following disclaimer in the documentation
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# and/or other materials provided with the distribution.
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#
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# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
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# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
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# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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# OF SUCH DAMAGE.
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#
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# The views and conclusions contained in the software and documentation are those
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# of the authors and should not be interpreted as representing official policies,
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# either expressed or implied, of The Regents of the University of California.
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TOPLEVEL_LANG = verilog
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SIM ?= icarus
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WAVES ?= 0
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COCOTB_HDL_TIMEUNIT = 1ns
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COCOTB_HDL_TIMEPRECISION = 1ps
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DUT = queue_manager
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TOPLEVEL = $(DUT)
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MODULE = test_$(DUT)
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VERILOG_SOURCES += ../../rtl/$(DUT).v
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# module parameters
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export PARAM_ADDR_WIDTH = 64
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export PARAM_REQ_TAG_WIDTH = 8
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export PARAM_OP_TABLE_SIZE = 16
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export PARAM_OP_TAG_WIDTH = 8
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export PARAM_QUEUE_INDEX_WIDTH = 8
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export PARAM_CPL_INDEX_WIDTH = 8
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export PARAM_QUEUE_PTR_WIDTH = 16
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export PARAM_LOG_QUEUE_SIZE_WIDTH = 4
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export PARAM_DESC_SIZE = 16
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export PARAM_LOG_BLOCK_SIZE_WIDTH = 2
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export PARAM_PIPELINE = 2
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export PARAM_AXIL_DATA_WIDTH = 32
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export PARAM_AXIL_ADDR_WIDTH = 16
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export PARAM_AXIL_STRB_WIDTH = $(shell expr $(PARAM_AXIL_DATA_WIDTH) / 8 )
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ifeq ($(SIM), icarus)
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PLUSARGS += -fst
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COMPILE_ARGS += -P $(TOPLEVEL).ADDR_WIDTH=$(PARAM_ADDR_WIDTH)
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COMPILE_ARGS += -P $(TOPLEVEL).REQ_TAG_WIDTH=$(PARAM_REQ_TAG_WIDTH)
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COMPILE_ARGS += -P $(TOPLEVEL).OP_TABLE_SIZE=$(PARAM_OP_TABLE_SIZE)
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COMPILE_ARGS += -P $(TOPLEVEL).OP_TAG_WIDTH=$(PARAM_OP_TAG_WIDTH)
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COMPILE_ARGS += -P $(TOPLEVEL).QUEUE_INDEX_WIDTH=$(PARAM_QUEUE_INDEX_WIDTH)
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COMPILE_ARGS += -P $(TOPLEVEL).CPL_INDEX_WIDTH=$(PARAM_CPL_INDEX_WIDTH)
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COMPILE_ARGS += -P $(TOPLEVEL).QUEUE_PTR_WIDTH=$(PARAM_QUEUE_PTR_WIDTH)
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COMPILE_ARGS += -P $(TOPLEVEL).LOG_QUEUE_SIZE_WIDTH=$(PARAM_LOG_QUEUE_SIZE_WIDTH)
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COMPILE_ARGS += -P $(TOPLEVEL).DESC_SIZE=$(PARAM_DESC_SIZE)
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COMPILE_ARGS += -P $(TOPLEVEL).LOG_BLOCK_SIZE_WIDTH=$(PARAM_LOG_BLOCK_SIZE_WIDTH)
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COMPILE_ARGS += -P $(TOPLEVEL).PIPELINE=$(PARAM_PIPELINE)
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COMPILE_ARGS += -P $(TOPLEVEL).AXIL_DATA_WIDTH=$(PARAM_AXIL_DATA_WIDTH)
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COMPILE_ARGS += -P $(TOPLEVEL).AXIL_ADDR_WIDTH=$(PARAM_AXIL_ADDR_WIDTH)
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COMPILE_ARGS += -P $(TOPLEVEL).AXIL_STRB_WIDTH=$(PARAM_AXIL_STRB_WIDTH)
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ifeq ($(WAVES), 1)
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VERILOG_SOURCES += iverilog_dump.v
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COMPILE_ARGS += -s iverilog_dump
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endif
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else ifeq ($(SIM), verilator)
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COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
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COMPILE_ARGS += -GADDR_WIDTH=$(PARAM_ADDR_WIDTH)
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COMPILE_ARGS += -GREQ_TAG_WIDTH=$(PARAM_REQ_TAG_WIDTH)
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COMPILE_ARGS += -GOP_TABLE_SIZE=$(PARAM_OP_TABLE_SIZE)
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COMPILE_ARGS += -GOP_TAG_WIDTH=$(PARAM_OP_TAG_WIDTH)
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COMPILE_ARGS += -GQUEUE_INDEX_WIDTH=$(PARAM_QUEUE_INDEX_WIDTH)
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COMPILE_ARGS += -GCPL_INDEX_WIDTH=$(PARAM_CPL_INDEX_WIDTH)
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COMPILE_ARGS += -GQUEUE_PTR_WIDTH=$(PARAM_QUEUE_PTR_WIDTH)
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COMPILE_ARGS += -GLOG_QUEUE_SIZE_WIDTH=$(PARAM_LOG_QUEUE_SIZE_WIDTH)
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COMPILE_ARGS += -GDESC_SIZE=$(PARAM_DESC_SIZE)
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COMPILE_ARGS += -GLOG_BLOCK_SIZE_WIDTH=$(PARAM_LOG_BLOCK_SIZE_WIDTH)
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COMPILE_ARGS += -GPIPELINE=$(PARAM_PIPELINE)
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COMPILE_ARGS += -GAXIL_DATA_WIDTH=$(PARAM_AXIL_DATA_WIDTH)
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COMPILE_ARGS += -GAXIL_ADDR_WIDTH=$(PARAM_AXIL_ADDR_WIDTH)
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COMPILE_ARGS += -GAXIL_STRB_WIDTH=$(PARAM_AXIL_STRB_WIDTH)
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ifeq ($(WAVES), 1)
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COMPILE_ARGS += --trace-fst
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endif
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endif
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include $(shell cocotb-config --makefiles)/Makefile.sim
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iverilog_dump.v:
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echo 'module iverilog_dump();' > $@
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echo 'initial begin' >> $@
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echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@
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echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@
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echo 'end' >> $@
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echo 'endmodule' >> $@
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clean::
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@rm -rf iverilog_dump.v
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@rm -rf dump.fst $(TOPLEVEL).fst
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