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330 lines
12 KiB
Verilog
330 lines
12 KiB
Verilog
/*
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Copyright (c) 2014 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* ARP ethernet frame receiver (Ethernet frame in, ARP frame out, 64 bit datapath)
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*/
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module arp_eth_rx_64
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(
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input wire clk,
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input wire rst,
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/*
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* Ethernet frame input
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*/
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input wire input_eth_hdr_valid,
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output wire input_eth_hdr_ready,
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input wire [47:0] input_eth_dest_mac,
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input wire [47:0] input_eth_src_mac,
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input wire [15:0] input_eth_type,
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input wire [63:0] input_eth_payload_tdata,
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input wire [7:0] input_eth_payload_tkeep,
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input wire input_eth_payload_tvalid,
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output wire input_eth_payload_tready,
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input wire input_eth_payload_tlast,
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input wire input_eth_payload_tuser,
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/*
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* ARP frame output
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*/
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output wire output_frame_valid,
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input wire output_frame_ready,
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output wire [47:0] output_eth_dest_mac,
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output wire [47:0] output_eth_src_mac,
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output wire [15:0] output_eth_type,
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output wire [15:0] output_arp_htype,
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output wire [15:0] output_arp_ptype,
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output wire [7:0] output_arp_hlen,
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output wire [7:0] output_arp_plen,
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output wire [15:0] output_arp_oper,
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output wire [47:0] output_arp_sha,
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output wire [31:0] output_arp_spa,
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output wire [47:0] output_arp_tha,
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output wire [31:0] output_arp_tpa,
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/*
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* Status signals
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*/
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output wire busy,
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output wire error_header_early_termination,
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output wire error_invalid_header
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);
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/*
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ARP Frame
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Field Length
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Destination MAC address 6 octets
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Source MAC address 6 octets
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Ethertype (0x0806) 2 octets
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HTYPE (1) 2 octets
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PTYPE (0x0800) 2 octets
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HLEN (6) 1 octets
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PLEN (4) 1 octets
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OPER 2 octets
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SHA Sender MAC 6 octets
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SPA Sender IP 4 octets
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THA Target MAC 6 octets
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TPA Target IP 4 octets
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This module receives an Ethernet frame with decoded fields and decodes
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the ARP packet format. If the Ethertype does not match, the packet is
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discarded.
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*/
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localparam [2:0]
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STATE_IDLE = 3'd0,
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STATE_READ_HEADER = 3'd1,
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STATE_WAIT_LAST = 3'd2;
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reg [2:0] state_reg = STATE_IDLE, state_next;
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// datapath control signals
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reg store_eth_hdr;
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reg store_arp_hdr_word_0;
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reg store_arp_hdr_word_1;
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reg store_arp_hdr_word_2;
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reg store_arp_hdr_word_3;
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reg [7:0] frame_ptr_reg = 0, frame_ptr_next;
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reg input_eth_hdr_ready_reg = 0;
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reg input_eth_payload_tready_reg = 0;
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reg output_frame_valid_reg = 0, output_frame_valid_next;
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reg [47:0] output_eth_dest_mac_reg = 0;
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reg [47:0] output_eth_src_mac_reg = 0;
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reg [15:0] output_eth_type_reg = 0;
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reg [15:0] output_arp_htype_reg = 0;
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reg [15:0] output_arp_ptype_reg = 0;
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reg [7:0] output_arp_hlen_reg = 0;
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reg [7:0] output_arp_plen_reg = 0;
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reg [15:0] output_arp_oper_reg = 0;
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reg [47:0] output_arp_sha_reg = 0;
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reg [31:0] output_arp_spa_reg = 0;
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reg [47:0] output_arp_tha_reg = 0;
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reg [31:0] output_arp_tpa_reg = 0;
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reg busy_reg = 0;
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reg error_header_early_termination_reg = 0, error_header_early_termination_next;
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reg error_invalid_header_reg = 0, error_invalid_header_next;
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assign input_eth_hdr_ready = input_eth_hdr_ready_reg;
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assign input_eth_payload_tready = input_eth_payload_tready_reg;
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assign output_frame_valid = output_frame_valid_reg;
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assign output_eth_dest_mac = output_eth_dest_mac_reg;
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assign output_eth_src_mac = output_eth_src_mac_reg;
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assign output_eth_type = output_eth_type_reg;
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assign output_arp_htype = output_arp_htype_reg;
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assign output_arp_ptype = output_arp_ptype_reg;
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assign output_arp_hlen = output_arp_hlen_reg;
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assign output_arp_plen = output_arp_plen_reg;
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assign output_arp_oper = output_arp_oper_reg;
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assign output_arp_sha = output_arp_sha_reg;
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assign output_arp_spa = output_arp_spa_reg;
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assign output_arp_tha = output_arp_tha_reg;
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assign output_arp_tpa = output_arp_tpa_reg;
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assign busy = busy_reg;
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assign error_header_early_termination = error_header_early_termination_reg;
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assign error_invalid_header = error_invalid_header_reg;
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always @* begin
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state_next = 2'bz;
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store_eth_hdr = 0;
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store_arp_hdr_word_0 = 0;
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store_arp_hdr_word_1 = 0;
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store_arp_hdr_word_2 = 0;
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store_arp_hdr_word_3 = 0;
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frame_ptr_next = frame_ptr_reg;
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output_frame_valid_next = output_frame_valid_reg & ~output_frame_ready;
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error_header_early_termination_next = 0;
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error_invalid_header_next = 0;
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case (state_reg)
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STATE_IDLE: begin
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// idle state - wait for data
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frame_ptr_next = 0;
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if (input_eth_hdr_ready & input_eth_hdr_valid) begin
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frame_ptr_next = 0;
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store_eth_hdr = 1;
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state_next = STATE_READ_HEADER;
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end else begin
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state_next = STATE_IDLE;
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end
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end
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STATE_READ_HEADER: begin
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// read header state
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if (input_eth_payload_tvalid) begin
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// word transfer in - store it
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frame_ptr_next = frame_ptr_reg+1;
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state_next = STATE_READ_HEADER;
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case (frame_ptr_reg)
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8'h00: store_arp_hdr_word_0 = 1;
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8'h01: store_arp_hdr_word_1 = 1;
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8'h02: store_arp_hdr_word_2 = 1;
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8'h03: begin
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store_arp_hdr_word_3 = 1;
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state_next = STATE_WAIT_LAST;
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end
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endcase
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if (input_eth_payload_tlast) begin
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state_next = STATE_IDLE;
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if (frame_ptr_reg != 8'h03 | (input_eth_payload_tkeep & 8'h0F) != 8'h0F) begin
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error_header_early_termination_next = 1;
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end else if (output_arp_hlen != 6 || output_arp_plen != 4) begin
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error_invalid_header_next = 1;
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end else begin
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output_frame_valid_next = ~input_eth_payload_tuser;
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end
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end
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end else begin
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state_next = STATE_READ_HEADER;
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end
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end
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STATE_WAIT_LAST: begin
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// read last payload word; data in output register; do not accept new data
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if (input_eth_payload_tvalid) begin
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// word transfer out - done
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if (input_eth_payload_tlast) begin
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if (output_arp_hlen != 6 || output_arp_plen != 4) begin
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error_invalid_header_next = 1;
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end else begin
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output_frame_valid_next = ~input_eth_payload_tuser;
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end
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state_next = STATE_IDLE;
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end else begin
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state_next = STATE_WAIT_LAST;
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end
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end else begin
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// wait for end of frame; read and discard
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state_next = STATE_WAIT_LAST;
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end
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end
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endcase
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end
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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state_reg <= STATE_IDLE;
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frame_ptr_reg <= 0;
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input_eth_payload_tready_reg <= 0;
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output_frame_valid_reg <= 0;
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output_eth_dest_mac_reg <= 0;
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output_eth_src_mac_reg <= 0;
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output_eth_type_reg <= 0;
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busy_reg <= 0;
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error_header_early_termination_reg <= 0;
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error_invalid_header_reg <= 0;
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end else begin
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state_reg <= state_next;
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frame_ptr_reg <= frame_ptr_next;
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output_frame_valid_reg <= output_frame_valid_next;
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error_header_early_termination_reg <= error_header_early_termination_next;
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error_invalid_header_reg <= error_invalid_header_next;
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busy_reg <= state_next != STATE_IDLE;
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// generate valid outputs
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case (state_next)
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STATE_IDLE: begin
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// idle; accept new data
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input_eth_hdr_ready_reg <= ~output_frame_valid;
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input_eth_payload_tready_reg <= 0;
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end
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STATE_READ_HEADER: begin
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// read header; accept new data
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input_eth_hdr_ready_reg <= 0;
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input_eth_payload_tready_reg <= 1;
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end
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STATE_WAIT_LAST: begin
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// wait for end of frame; read and discard
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input_eth_hdr_ready_reg <= 0;
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input_eth_payload_tready_reg <= 1;
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end
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endcase
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// datapath
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if (store_eth_hdr) begin
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output_eth_dest_mac_reg <= input_eth_dest_mac;
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output_eth_src_mac_reg <= input_eth_src_mac;
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output_eth_type_reg <= input_eth_type;
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end
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if (store_arp_hdr_word_0) begin
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output_arp_htype_reg[15: 8] <= input_eth_payload_tdata[ 7: 0];
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output_arp_htype_reg[ 7: 0] <= input_eth_payload_tdata[15: 8];
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output_arp_ptype_reg[15: 8] <= input_eth_payload_tdata[23:16];
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output_arp_ptype_reg[ 7: 0] <= input_eth_payload_tdata[31:24];
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output_arp_hlen_reg <= input_eth_payload_tdata[39:32];
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output_arp_plen_reg <= input_eth_payload_tdata[47:40];
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output_arp_oper_reg[15: 8] <= input_eth_payload_tdata[55:48];
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output_arp_oper_reg[ 7: 0] <= input_eth_payload_tdata[63:56];
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end
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if (store_arp_hdr_word_1) begin
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output_arp_sha_reg[47:40] <= input_eth_payload_tdata[ 7: 0];
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output_arp_sha_reg[39:32] <= input_eth_payload_tdata[15: 8];
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output_arp_sha_reg[31:24] <= input_eth_payload_tdata[23:16];
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output_arp_sha_reg[23:16] <= input_eth_payload_tdata[31:24];
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output_arp_sha_reg[15: 8] <= input_eth_payload_tdata[39:32];
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output_arp_sha_reg[ 7: 0] <= input_eth_payload_tdata[47:40];
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output_arp_spa_reg[31:24] <= input_eth_payload_tdata[55:48];
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output_arp_spa_reg[23:16] <= input_eth_payload_tdata[63:56];
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end
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if (store_arp_hdr_word_2) begin
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output_arp_spa_reg[15: 8] <= input_eth_payload_tdata[ 7: 0];
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output_arp_spa_reg[ 7: 0] <= input_eth_payload_tdata[15: 8];
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output_arp_tha_reg[47:40] <= input_eth_payload_tdata[23:16];
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output_arp_tha_reg[39:32] <= input_eth_payload_tdata[31:24];
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output_arp_tha_reg[31:24] <= input_eth_payload_tdata[39:32];
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output_arp_tha_reg[23:16] <= input_eth_payload_tdata[47:40];
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output_arp_tha_reg[15: 8] <= input_eth_payload_tdata[55:48];
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output_arp_tha_reg[ 7: 0] <= input_eth_payload_tdata[63:56];
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end
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if (store_arp_hdr_word_3) begin
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output_arp_tpa_reg[31:24] <= input_eth_payload_tdata[ 7: 0];
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output_arp_tpa_reg[23:16] <= input_eth_payload_tdata[15: 8];
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output_arp_tpa_reg[15: 8] <= input_eth_payload_tdata[23:16];
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output_arp_tpa_reg[ 7: 0] <= input_eth_payload_tdata[31:24];
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end
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end
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end
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endmodule
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