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441 lines
17 KiB
Verilog
441 lines
17 KiB
Verilog
// SPDX-License-Identifier: BSD-2-Clause-Views
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/*
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* Copyright (c) 2019-2023 The Regents of the University of California
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* TDMA BER module
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*/
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module tdma_ber #
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(
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// Channel count
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parameter COUNT = 1,
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// Timeslot index width
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parameter INDEX_WIDTH = 6,
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// Slice index width
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parameter SLICE_WIDTH = 5,
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// Width of AXI lite data bus in bits
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parameter AXIL_DATA_WIDTH = 32,
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// Width of AXI lite address bus in bits
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parameter AXIL_ADDR_WIDTH = INDEX_WIDTH+4+1+$clog2(COUNT),
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// Width of AXI lite wstrb (width of data bus in words)
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parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8),
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// Schedule absolute PTP start time, seconds part
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parameter SCHEDULE_START_S = 48'h0,
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// Schedule absolute PTP start time, nanoseconds part
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parameter SCHEDULE_START_NS = 30'h0,
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// Schedule period, seconds part
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parameter SCHEDULE_PERIOD_S = 48'd0,
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// Schedule period, nanoseconds part
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parameter SCHEDULE_PERIOD_NS = 30'd1000000,
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// Timeslot period, seconds part
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parameter TIMESLOT_PERIOD_S = 48'd0,
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// Timeslot period, nanoseconds part
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parameter TIMESLOT_PERIOD_NS = 30'd100000,
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// Timeslot active period, seconds part
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parameter ACTIVE_PERIOD_S = 48'd0,
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// Timeslot active period, nanoseconds part
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parameter ACTIVE_PERIOD_NS = 30'd100000,
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// pipeline stages on PHY interface ports
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parameter PHY_PIPELINE = 0
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)
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(
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input wire clk,
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input wire rst,
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/*
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* PHY connections
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*/
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input wire [COUNT-1:0] phy_tx_clk,
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input wire [COUNT-1:0] phy_rx_clk,
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input wire [COUNT*7-1:0] phy_rx_error_count,
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output wire [COUNT-1:0] phy_cfg_tx_prbs31_enable,
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output wire [COUNT-1:0] phy_cfg_rx_prbs31_enable,
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/*
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* AXI-Lite slave interface
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*/
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input wire [AXIL_ADDR_WIDTH-1:0] s_axil_awaddr,
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input wire [2:0] s_axil_awprot,
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input wire s_axil_awvalid,
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output wire s_axil_awready,
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input wire [AXIL_DATA_WIDTH-1:0] s_axil_wdata,
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input wire [AXIL_STRB_WIDTH-1:0] s_axil_wstrb,
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input wire s_axil_wvalid,
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output wire s_axil_wready,
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output wire [1:0] s_axil_bresp,
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output wire s_axil_bvalid,
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input wire s_axil_bready,
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input wire [AXIL_ADDR_WIDTH-1:0] s_axil_araddr,
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input wire [2:0] s_axil_arprot,
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input wire s_axil_arvalid,
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output wire s_axil_arready,
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output wire [AXIL_DATA_WIDTH-1:0] s_axil_rdata,
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output wire [1:0] s_axil_rresp,
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output wire s_axil_rvalid,
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input wire s_axil_rready,
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/*
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* PTP clock
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*/
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input wire [95:0] ptp_ts_96,
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input wire ptp_ts_step
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);
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// check configuration
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initial begin
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if (AXIL_ADDR_WIDTH < INDEX_WIDTH+4+1+$clog2(COUNT)) begin
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$error("Error: AXI address width too narrow (instance %m)");
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$finish;
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end
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if (AXIL_DATA_WIDTH != 32) begin
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$error("Error: AXI data width must be 32 (instance %m)");
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$finish;
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end
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if (AXIL_STRB_WIDTH * 8 != AXIL_DATA_WIDTH) begin
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$error("Error: Interface requires byte (8-bit) granularity (instance %m)");
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$finish;
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end
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end
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wire [AXIL_ADDR_WIDTH-1:0] axil_csr_awaddr;
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wire [2:0] axil_csr_awprot;
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wire axil_csr_awvalid;
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wire axil_csr_awready;
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wire [AXIL_DATA_WIDTH-1:0] axil_csr_wdata;
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wire [AXIL_STRB_WIDTH-1:0] axil_csr_wstrb;
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wire axil_csr_wvalid;
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wire axil_csr_wready;
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wire [1:0] axil_csr_bresp;
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wire axil_csr_bvalid;
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wire axil_csr_bready;
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wire [AXIL_ADDR_WIDTH-1:0] axil_csr_araddr;
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wire [2:0] axil_csr_arprot;
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wire axil_csr_arvalid;
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wire axil_csr_arready;
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wire [AXIL_DATA_WIDTH-1:0] axil_csr_rdata;
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wire [1:0] axil_csr_rresp;
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wire axil_csr_rvalid;
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wire axil_csr_rready;
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// control registers
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reg axil_csr_awready_reg = 1'b0;
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reg axil_csr_wready_reg = 1'b0;
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reg axil_csr_bvalid_reg = 1'b0;
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reg axil_csr_arready_reg = 1'b0;
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reg [AXIL_DATA_WIDTH-1:0] axil_csr_rdata_reg = {AXIL_DATA_WIDTH{1'b0}};
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reg axil_csr_rvalid_reg = 1'b0;
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reg tdma_enable_reg = 1'b0;
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wire tdma_locked;
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wire tdma_error;
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reg [79:0] set_tdma_schedule_start_reg = 0;
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reg set_tdma_schedule_start_valid_reg = 0;
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reg [79:0] set_tdma_schedule_period_reg = 0;
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reg set_tdma_schedule_period_valid_reg = 0;
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reg [79:0] set_tdma_timeslot_period_reg = 0;
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reg set_tdma_timeslot_period_valid_reg = 0;
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reg [79:0] set_tdma_active_period_reg = 0;
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reg set_tdma_active_period_valid_reg = 0;
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wire tdma_schedule_start;
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wire [INDEX_WIDTH-1:0] tdma_timeslot_index;
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wire tdma_timeslot_start;
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wire tdma_timeslot_end;
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wire tdma_timeslot_active;
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assign axil_csr_awready = axil_csr_awready_reg;
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assign axil_csr_wready = axil_csr_wready_reg;
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assign axil_csr_bresp = 2'b00;
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assign axil_csr_bvalid = axil_csr_bvalid_reg;
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assign axil_csr_arready = axil_csr_arready_reg;
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assign axil_csr_rdata = axil_csr_rdata_reg;
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assign axil_csr_rresp = 2'b00;
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assign axil_csr_rvalid = axil_csr_rvalid_reg;
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always @(posedge clk) begin
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axil_csr_awready_reg <= 1'b0;
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axil_csr_wready_reg <= 1'b0;
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axil_csr_bvalid_reg <= axil_csr_bvalid_reg && !axil_csr_bready;
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axil_csr_arready_reg <= 1'b0;
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axil_csr_rvalid_reg <= axil_csr_rvalid_reg && !axil_csr_rready;
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set_tdma_schedule_start_valid_reg <= 1'b0;
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set_tdma_schedule_period_valid_reg <= 1'b0;
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set_tdma_timeslot_period_valid_reg <= 1'b0;
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set_tdma_active_period_valid_reg <= 1'b0;
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if (axil_csr_awvalid && axil_csr_wvalid && !axil_csr_bvalid) begin
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// write operation
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axil_csr_awready_reg <= 1'b1;
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axil_csr_wready_reg <= 1'b1;
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axil_csr_bvalid_reg <= 1'b1;
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case (axil_csr_awaddr & ({AXIL_ADDR_WIDTH{1'b1}} << 2))
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16'h0100: begin
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// TDMA control
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tdma_enable_reg <= axil_csr_wdata[0];
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end
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16'h0114: set_tdma_schedule_start_reg[29:0] <= axil_csr_wdata; // TDMA schedule start ns
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16'h0118: set_tdma_schedule_start_reg[63:32] <= axil_csr_wdata; // TDMA schedule start sec l
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16'h011C: begin
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// TDMA schedule start sec h
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set_tdma_schedule_start_reg[79:64] <= axil_csr_wdata;
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set_tdma_schedule_start_valid_reg <= 1'b1;
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end
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16'h0124: set_tdma_schedule_period_reg[29:0] <= axil_csr_wdata; // TDMA schedule period ns
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16'h0128: set_tdma_schedule_period_reg[63:32] <= axil_csr_wdata; // TDMA schedule period sec l
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16'h012C: begin
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// TDMA schedule period sec h
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set_tdma_schedule_period_reg[79:64] <= axil_csr_wdata;
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set_tdma_schedule_period_valid_reg <= 1'b1;
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end
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16'h0134: set_tdma_timeslot_period_reg[29:0] <= axil_csr_wdata; // TDMA timeslot period ns
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16'h0138: set_tdma_timeslot_period_reg[63:32] <= axil_csr_wdata; // TDMA timeslot period sec l
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16'h013C: begin
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// TDMA timeslot period sec h
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set_tdma_timeslot_period_reg[79:64] <= axil_csr_wdata;
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set_tdma_timeslot_period_valid_reg <= 1'b1;
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end
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16'h0144: set_tdma_active_period_reg[29:0] <= axil_csr_wdata; // TDMA active period ns
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16'h0148: set_tdma_active_period_reg[63:32] <= axil_csr_wdata; // TDMA active period sec l
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16'h014C: begin
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// TDMA active period sec h
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set_tdma_active_period_reg[79:64] <= axil_csr_wdata;
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set_tdma_active_period_valid_reg <= 1'b1;
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end
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endcase
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end
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if (axil_csr_arvalid && !axil_csr_rvalid) begin
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// read operation
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axil_csr_arready_reg <= 1'b1;
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axil_csr_rvalid_reg <= 1'b1;
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axil_csr_rdata_reg <= {AXIL_DATA_WIDTH{1'b0}};
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case (axil_csr_araddr & ({AXIL_ADDR_WIDTH{1'b1}} << 2))
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16'h0000: axil_csr_rdata_reg <= 0;
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16'h0010: axil_csr_rdata_reg <= COUNT;
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16'h0014: axil_csr_rdata_reg <= INDEX_WIDTH;
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16'h0018: axil_csr_rdata_reg <= SLICE_WIDTH;
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16'h0100: begin
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// TDMA control
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axil_csr_rdata_reg[0] <= tdma_enable_reg;
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end
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16'h0104: begin
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// TDMA status
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axil_csr_rdata_reg[0] <= tdma_locked;
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axil_csr_rdata_reg[1] <= tdma_error;
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end
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16'h0114: axil_csr_rdata_reg <= set_tdma_schedule_start_reg[29:0]; // TDMA schedule start ns
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16'h0118: axil_csr_rdata_reg <= set_tdma_schedule_start_reg[63:32]; // TDMA schedule start sec l
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16'h011C: axil_csr_rdata_reg <= set_tdma_schedule_start_reg[79:64]; // TDMA schedule start sec h
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16'h0124: axil_csr_rdata_reg <= set_tdma_schedule_period_reg[29:0]; // TDMA schedule period ns
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16'h0128: axil_csr_rdata_reg <= set_tdma_schedule_period_reg[63:32]; // TDMA schedule period sec l
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16'h012C: axil_csr_rdata_reg <= set_tdma_schedule_period_reg[79:64]; // TDMA schedule period sec h
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16'h0134: axil_csr_rdata_reg <= set_tdma_timeslot_period_reg[29:0]; // TDMA timeslot period ns
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16'h0138: axil_csr_rdata_reg <= set_tdma_timeslot_period_reg[63:32]; // TDMA timeslot period sec l
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16'h013C: axil_csr_rdata_reg <= set_tdma_timeslot_period_reg[79:64]; // TDMA timeslot period sec h
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16'h0144: axil_csr_rdata_reg <= set_tdma_active_period_reg[29:0]; // TDMA active period ns
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16'h0148: axil_csr_rdata_reg <= set_tdma_active_period_reg[63:32]; // TDMA active period sec l
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16'h014C: axil_csr_rdata_reg <= set_tdma_active_period_reg[79:64]; // TDMA active period sec h
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endcase
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end
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if (rst) begin
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axil_csr_awready_reg <= 1'b0;
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axil_csr_wready_reg <= 1'b0;
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axil_csr_bvalid_reg <= 1'b0;
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axil_csr_arready_reg <= 1'b0;
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axil_csr_rvalid_reg <= 1'b0;
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tdma_enable_reg <= 1'b0;
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end
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end
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tdma_scheduler #(
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.INDEX_WIDTH(INDEX_WIDTH),
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.SCHEDULE_START_S(SCHEDULE_START_S),
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.SCHEDULE_START_NS(SCHEDULE_START_NS),
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.SCHEDULE_PERIOD_S(SCHEDULE_PERIOD_S),
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.SCHEDULE_PERIOD_NS(SCHEDULE_PERIOD_NS),
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.TIMESLOT_PERIOD_S(TIMESLOT_PERIOD_S),
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.TIMESLOT_PERIOD_NS(TIMESLOT_PERIOD_NS),
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.ACTIVE_PERIOD_S(ACTIVE_PERIOD_S),
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.ACTIVE_PERIOD_NS(ACTIVE_PERIOD_NS)
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)
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tdma_scheduler_inst (
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.clk(clk),
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.rst(rst),
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.input_ts_96(ptp_ts_96),
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.input_ts_step(ptp_ts_step),
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.enable(tdma_enable_reg),
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.input_schedule_start(set_tdma_schedule_start_reg),
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.input_schedule_start_valid(set_tdma_schedule_start_valid_reg),
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.input_schedule_period(set_tdma_schedule_period_reg),
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.input_schedule_period_valid(set_tdma_schedule_period_valid_reg),
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.input_timeslot_period(set_tdma_timeslot_period_reg),
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.input_timeslot_period_valid(set_tdma_timeslot_period_valid_reg),
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.input_active_period(set_tdma_active_period_reg),
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.input_active_period_valid(set_tdma_active_period_valid_reg),
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.locked(tdma_locked),
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.error(tdma_error),
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.schedule_start(tdma_schedule_start),
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.timeslot_index(tdma_timeslot_index),
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.timeslot_start(tdma_timeslot_start),
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.timeslot_end(tdma_timeslot_end),
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.timeslot_active(tdma_timeslot_active)
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);
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wire [COUNT*AXIL_ADDR_WIDTH-1:0] axil_ch_awaddr;
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wire [COUNT*3-1:0] axil_ch_awprot;
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wire [COUNT-1:0] axil_ch_awvalid;
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wire [COUNT-1:0] axil_ch_awready;
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wire [COUNT*AXIL_DATA_WIDTH-1:0] axil_ch_wdata;
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wire [COUNT*AXIL_STRB_WIDTH-1:0] axil_ch_wstrb;
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wire [COUNT-1:0] axil_ch_wvalid;
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wire [COUNT-1:0] axil_ch_wready;
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wire [COUNT*2-1:0] axil_ch_bresp;
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wire [COUNT-1:0] axil_ch_bvalid;
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wire [COUNT-1:0] axil_ch_bready;
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wire [COUNT*AXIL_ADDR_WIDTH-1:0] axil_ch_araddr;
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wire [COUNT*3-1:0] axil_ch_arprot;
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wire [COUNT-1:0] axil_ch_arvalid;
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wire [COUNT-1:0] axil_ch_arready;
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wire [COUNT*AXIL_DATA_WIDTH-1:0] axil_ch_rdata;
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wire [COUNT*2-1:0] axil_ch_rresp;
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wire [COUNT-1:0] axil_ch_rvalid;
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wire [COUNT-1:0] axil_ch_rready;
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parameter CH_ADDR_WIDTH = INDEX_WIDTH+4;
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parameter CH_BASE_ADDR_WIDTH = (COUNT+1)*AXIL_ADDR_WIDTH;
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parameter CH_BASE_ADDR = calcBaseAddrs(CH_ADDR_WIDTH);
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function [CH_BASE_ADDR_WIDTH-1:0] calcBaseAddrs(input [31:0] width);
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integer i;
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begin
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calcBaseAddrs = {CH_BASE_ADDR_WIDTH{1'b0}};
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for (i = 0; i < COUNT+1; i = i + 1) begin
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calcBaseAddrs[i * AXIL_ADDR_WIDTH +: AXIL_ADDR_WIDTH] = i * (2**width);
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end
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end
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endfunction
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function [31:0] w_32(input [31:0] val);
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w_32 = val;
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endfunction
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axil_interconnect #(
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.DATA_WIDTH(AXIL_DATA_WIDTH),
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.ADDR_WIDTH(AXIL_ADDR_WIDTH),
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.S_COUNT(1),
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.M_COUNT(COUNT+1),
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.M_BASE_ADDR(CH_BASE_ADDR),
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.M_ADDR_WIDTH({COUNT+1{w_32(CH_ADDR_WIDTH)}}),
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.M_CONNECT_READ({COUNT+1{1'b1}}),
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.M_CONNECT_WRITE({COUNT+1{1'b1}})
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)
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axil_csr_interconnect_inst (
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.clk(clk),
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.rst(rst),
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.s_axil_awaddr(s_axil_awaddr),
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.s_axil_awprot(s_axil_awprot),
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.s_axil_awvalid(s_axil_awvalid),
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.s_axil_awready(s_axil_awready),
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.s_axil_wdata(s_axil_wdata),
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.s_axil_wstrb(s_axil_wstrb),
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.s_axil_wvalid(s_axil_wvalid),
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.s_axil_wready(s_axil_wready),
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.s_axil_bresp(s_axil_bresp),
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.s_axil_bvalid(s_axil_bvalid),
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.s_axil_bready(s_axil_bready),
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.s_axil_araddr(s_axil_araddr),
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.s_axil_arprot(s_axil_arprot),
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.s_axil_arvalid(s_axil_arvalid),
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.s_axil_arready(s_axil_arready),
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.s_axil_rdata(s_axil_rdata),
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.s_axil_rresp(s_axil_rresp),
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.s_axil_rvalid(s_axil_rvalid),
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.s_axil_rready(s_axil_rready),
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.m_axil_awaddr( {axil_ch_awaddr, axil_csr_awaddr}),
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.m_axil_awprot( {axil_ch_awprot, axil_csr_awprot}),
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.m_axil_awvalid( {axil_ch_awvalid, axil_csr_awvalid}),
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.m_axil_awready( {axil_ch_awready, axil_csr_awready}),
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.m_axil_wdata( {axil_ch_wdata, axil_csr_wdata}),
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.m_axil_wstrb( {axil_ch_wstrb, axil_csr_wstrb}),
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.m_axil_wvalid( {axil_ch_wvalid, axil_csr_wvalid}),
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.m_axil_wready( {axil_ch_wready, axil_csr_wready}),
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.m_axil_bresp( {axil_ch_bresp, axil_csr_bresp}),
|
|
.m_axil_bvalid( {axil_ch_bvalid, axil_csr_bvalid}),
|
|
.m_axil_bready( {axil_ch_bready, axil_csr_bready}),
|
|
.m_axil_araddr( {axil_ch_araddr, axil_csr_araddr}),
|
|
.m_axil_arprot( {axil_ch_arprot, axil_csr_arprot}),
|
|
.m_axil_arvalid( {axil_ch_arvalid, axil_csr_arvalid}),
|
|
.m_axil_arready( {axil_ch_arready, axil_csr_arready}),
|
|
.m_axil_rdata( {axil_ch_rdata, axil_csr_rdata}),
|
|
.m_axil_rresp( {axil_ch_rresp, axil_csr_rresp}),
|
|
.m_axil_rvalid( {axil_ch_rvalid, axil_csr_rvalid}),
|
|
.m_axil_rready( {axil_ch_rready, axil_csr_rready})
|
|
);
|
|
|
|
generate
|
|
genvar n;
|
|
|
|
for (n = 0; n < COUNT; n = n + 1) begin
|
|
|
|
tdma_ber_ch #(
|
|
.INDEX_WIDTH(INDEX_WIDTH),
|
|
.SLICE_WIDTH(SLICE_WIDTH),
|
|
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
|
|
.AXIL_ADDR_WIDTH(CH_ADDR_WIDTH),
|
|
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
|
|
.PHY_PIPELINE(PHY_PIPELINE)
|
|
)
|
|
tdma_ber_ch_inst (
|
|
.clk(clk),
|
|
.rst(rst),
|
|
.phy_tx_clk(phy_tx_clk[n]),
|
|
.phy_rx_clk(phy_rx_clk[n]),
|
|
.phy_rx_error_count(phy_rx_error_count[n*7 +: 7]),
|
|
.phy_cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable[n]),
|
|
.phy_cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable[n]),
|
|
.s_axil_awaddr(axil_ch_awaddr[n*AXIL_ADDR_WIDTH +: AXIL_ADDR_WIDTH]),
|
|
.s_axil_awprot(axil_ch_awprot[n*3 +: 3]),
|
|
.s_axil_awvalid(axil_ch_awvalid[n]),
|
|
.s_axil_awready(axil_ch_awready[n]),
|
|
.s_axil_wdata(axil_ch_wdata[n*AXIL_DATA_WIDTH +: AXIL_DATA_WIDTH]),
|
|
.s_axil_wstrb(axil_ch_wstrb[n*AXIL_STRB_WIDTH +: AXIL_STRB_WIDTH]),
|
|
.s_axil_wvalid(axil_ch_wvalid[n]),
|
|
.s_axil_wready(axil_ch_wready[n]),
|
|
.s_axil_bresp(axil_ch_bresp[n*2 +: 2]),
|
|
.s_axil_bvalid(axil_ch_bvalid[n]),
|
|
.s_axil_bready(axil_ch_bready[n]),
|
|
.s_axil_araddr(axil_ch_araddr[n*AXIL_ADDR_WIDTH +: AXIL_ADDR_WIDTH]),
|
|
.s_axil_arprot(axil_ch_arprot[n*3 +: 3]),
|
|
.s_axil_arvalid(axil_ch_arvalid[n]),
|
|
.s_axil_arready(axil_ch_arready[n]),
|
|
.s_axil_rdata(axil_ch_rdata[n*AXIL_DATA_WIDTH +: AXIL_DATA_WIDTH]),
|
|
.s_axil_rresp(axil_ch_rresp[n*2 +: 2]),
|
|
.s_axil_rvalid(axil_ch_rvalid[n]),
|
|
.s_axil_rready(axil_ch_rready[n]),
|
|
.tdma_timeslot_index(tdma_timeslot_index),
|
|
.tdma_timeslot_start(tdma_timeslot_start),
|
|
.tdma_timeslot_active(tdma_timeslot_active)
|
|
);
|
|
|
|
end
|
|
endgenerate
|
|
|
|
endmodule
|
|
|
|
`resetall
|