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112 lines
2.8 KiB
Verilog
112 lines
2.8 KiB
Verilog
/*
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Copyright (c) 2019 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ps / 1fs
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/*
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* Testbench for ptp_clock_cdc
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*/
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module test_ptp_clock_cdc_64;
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// Parameters
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parameter TS_WIDTH = 64;
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parameter NS_WIDTH = 4;
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parameter FNS_WIDTH = 16;
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parameter INPUT_PERIOD_NS = 4'h6;
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parameter INPUT_PERIOD_FNS = 16'h6666;
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parameter OUTPUT_PERIOD_NS = 4'h6;
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parameter OUTPUT_PERIOD_FNS = 16'h6666;
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parameter USE_SAMPLE_CLOCK = 1;
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parameter LOG_FIFO_DEPTH = 3;
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parameter LOG_RATE = 3;
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// Inputs
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reg clk = 0;
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reg rst = 0;
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reg [7:0] current_test = 0;
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reg input_clk = 0;
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reg input_rst = 0;
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reg output_clk = 0;
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reg output_rst = 0;
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reg sample_clk = 0;
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reg [TS_WIDTH-1:0] input_ts = 0;
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// Outputs
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wire [TS_WIDTH-1:0] output_ts;
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wire output_ts_step;
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wire output_pps;
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initial begin
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// myhdl integration
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$from_myhdl(
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clk,
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rst,
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current_test,
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input_clk,
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input_rst,
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output_clk,
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output_rst,
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sample_clk,
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input_ts
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);
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$to_myhdl(
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output_ts,
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output_ts_step,
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output_pps
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);
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// dump file
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$dumpfile("test_ptp_clock_cdc_64.lxt");
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$dumpvars(0, test_ptp_clock_cdc_64);
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end
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ptp_clock_cdc #(
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.TS_WIDTH(TS_WIDTH),
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.NS_WIDTH(NS_WIDTH),
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.FNS_WIDTH(FNS_WIDTH),
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.INPUT_PERIOD_NS(INPUT_PERIOD_NS),
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.INPUT_PERIOD_FNS(INPUT_PERIOD_FNS),
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.OUTPUT_PERIOD_NS(OUTPUT_PERIOD_NS),
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.OUTPUT_PERIOD_FNS(OUTPUT_PERIOD_FNS),
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.USE_SAMPLE_CLOCK(USE_SAMPLE_CLOCK),
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.LOG_FIFO_DEPTH(LOG_FIFO_DEPTH),
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.LOG_RATE(LOG_RATE)
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)
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UUT (
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.input_clk(input_clk),
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.input_rst(input_rst),
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.output_clk(output_clk),
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.output_rst(output_rst),
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.sample_clk(sample_clk),
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.input_ts(input_ts),
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.output_ts(output_ts),
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.output_ts_step(output_ts_step),
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.output_pps(output_pps)
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);
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endmodule
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