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612 lines
22 KiB
Verilog
612 lines
22 KiB
Verilog
/*
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Copyright (c) 2023 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4 virtual FIFO
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*/
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module axi_vfifo #
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(
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// AXI channel count
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parameter AXI_CH = 1,
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// Width of AXI data bus in bits
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parameter AXI_DATA_WIDTH = 32,
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// Width of AXI address bus in bits
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parameter AXI_ADDR_WIDTH = 16,
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// Width of AXI wstrb (width of data bus in words)
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parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8),
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// Width of AXI ID signal
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parameter AXI_ID_WIDTH = 8,
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// Maximum AXI burst length to generate
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parameter AXI_MAX_BURST_LEN = 16,
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// Width of AXI stream interfaces in bits
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parameter AXIS_DATA_WIDTH = AXI_DATA_WIDTH*AXI_CH/2,
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// Use AXI stream tkeep signal
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parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8),
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// AXI stream tkeep signal width (words per cycle)
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parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8),
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// Use AXI stream tlast signal
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parameter AXIS_LAST_ENABLE = 1,
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// Propagate AXI stream tid signal
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parameter AXIS_ID_ENABLE = 0,
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// AXI stream tid signal width
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parameter AXIS_ID_WIDTH = 8,
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// Propagate AXI stream tdest signal
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parameter AXIS_DEST_ENABLE = 0,
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// AXI stream tdest signal width
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parameter AXIS_DEST_WIDTH = 8,
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// Propagate AXI stream tuser signal
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parameter AXIS_USER_ENABLE = 1,
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// AXI stream tuser signal width
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parameter AXIS_USER_WIDTH = 1,
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// Width of length field
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parameter LEN_WIDTH = AXI_ADDR_WIDTH,
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// Maximum segment width
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parameter MAX_SEG_WIDTH = 256,
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// Input FIFO depth for AXI write data (full-width words)
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parameter WRITE_FIFO_DEPTH = 64,
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// Max AXI write burst length
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parameter WRITE_MAX_BURST_LEN = WRITE_FIFO_DEPTH/4,
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// Output FIFO depth for AXI read data (full-width words)
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parameter READ_FIFO_DEPTH = 128,
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// Max AXI read burst length
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parameter READ_MAX_BURST_LEN = WRITE_MAX_BURST_LEN
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI stream data input
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*/
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input wire s_axis_clk,
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input wire s_axis_rst,
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output wire s_axis_rst_out,
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input wire [AXIS_DATA_WIDTH-1:0] s_axis_tdata,
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input wire [AXIS_KEEP_WIDTH-1:0] s_axis_tkeep,
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input wire s_axis_tvalid,
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output wire s_axis_tready,
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input wire s_axis_tlast,
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input wire [AXIS_ID_WIDTH-1:0] s_axis_tid,
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input wire [AXIS_DEST_WIDTH-1:0] s_axis_tdest,
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input wire [AXIS_USER_WIDTH-1:0] s_axis_tuser,
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/*
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* AXI stream data output
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*/
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input wire m_axis_clk,
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input wire m_axis_rst,
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output wire m_axis_rst_out,
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output wire [AXIS_DATA_WIDTH-1:0] m_axis_tdata,
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output wire [AXIS_KEEP_WIDTH-1:0] m_axis_tkeep,
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output wire m_axis_tvalid,
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input wire m_axis_tready,
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output wire m_axis_tlast,
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output wire [AXIS_ID_WIDTH-1:0] m_axis_tid,
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output wire [AXIS_DEST_WIDTH-1:0] m_axis_tdest,
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output wire [AXIS_USER_WIDTH-1:0] m_axis_tuser,
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/*
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* AXI master interfaces
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*/
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input wire [AXI_CH-1:0] m_axi_clk,
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input wire [AXI_CH-1:0] m_axi_rst,
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output wire [AXI_CH*AXI_ID_WIDTH-1:0] m_axi_awid,
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output wire [AXI_CH*AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
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output wire [AXI_CH*8-1:0] m_axi_awlen,
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output wire [AXI_CH*3-1:0] m_axi_awsize,
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output wire [AXI_CH*2-1:0] m_axi_awburst,
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output wire [AXI_CH-1:0] m_axi_awlock,
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output wire [AXI_CH*4-1:0] m_axi_awcache,
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output wire [AXI_CH*3-1:0] m_axi_awprot,
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output wire [AXI_CH-1:0] m_axi_awvalid,
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input wire [AXI_CH-1:0] m_axi_awready,
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output wire [AXI_CH*AXI_DATA_WIDTH-1:0] m_axi_wdata,
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output wire [AXI_CH*AXI_STRB_WIDTH-1:0] m_axi_wstrb,
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output wire [AXI_CH-1:0] m_axi_wlast,
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output wire [AXI_CH-1:0] m_axi_wvalid,
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input wire [AXI_CH-1:0] m_axi_wready,
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input wire [AXI_CH*AXI_ID_WIDTH-1:0] m_axi_bid,
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input wire [AXI_CH*2-1:0] m_axi_bresp,
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input wire [AXI_CH-1:0] m_axi_bvalid,
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output wire [AXI_CH-1:0] m_axi_bready,
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output wire [AXI_CH*AXI_ID_WIDTH-1:0] m_axi_arid,
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output wire [AXI_CH*AXI_ADDR_WIDTH-1:0] m_axi_araddr,
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output wire [AXI_CH*8-1:0] m_axi_arlen,
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output wire [AXI_CH*3-1:0] m_axi_arsize,
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output wire [AXI_CH*2-1:0] m_axi_arburst,
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output wire [AXI_CH-1:0] m_axi_arlock,
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output wire [AXI_CH*4-1:0] m_axi_arcache,
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output wire [AXI_CH*3-1:0] m_axi_arprot,
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output wire [AXI_CH-1:0] m_axi_arvalid,
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input wire [AXI_CH-1:0] m_axi_arready,
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input wire [AXI_CH*AXI_ID_WIDTH-1:0] m_axi_rid,
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input wire [AXI_CH*AXI_DATA_WIDTH-1:0] m_axi_rdata,
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input wire [AXI_CH*2-1:0] m_axi_rresp,
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input wire [AXI_CH-1:0] m_axi_rlast,
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input wire [AXI_CH-1:0] m_axi_rvalid,
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output wire [AXI_CH-1:0] m_axi_rready,
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/*
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* Configuration
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*/
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input wire [AXI_CH*AXI_ADDR_WIDTH-1:0] cfg_fifo_base_addr,
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input wire [LEN_WIDTH-1:0] cfg_fifo_size_mask,
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input wire cfg_enable,
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input wire cfg_reset,
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/*
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* Status
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*/
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output wire [AXI_CH*(LEN_WIDTH+1)-1:0] sts_fifo_occupancy,
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output wire [AXI_CH-1:0] sts_fifo_empty,
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output wire [AXI_CH-1:0] sts_fifo_full,
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output wire [AXI_CH-1:0] sts_reset,
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output wire [AXI_CH-1:0] sts_active,
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output wire sts_hdr_parity_err
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);
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parameter CH_SEG_CNT = AXI_DATA_WIDTH > MAX_SEG_WIDTH ? AXI_DATA_WIDTH / MAX_SEG_WIDTH : 1;
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parameter SEG_CNT = CH_SEG_CNT * AXI_CH;
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parameter SEG_WIDTH = AXI_DATA_WIDTH / CH_SEG_CNT;
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wire [AXI_CH-1:0] ch_input_rst_out;
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wire [AXI_CH-1:0] ch_input_watermark;
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wire [SEG_CNT*SEG_WIDTH-1:0] ch_input_data;
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wire [SEG_CNT-1:0] ch_input_valid;
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wire [SEG_CNT-1:0] ch_input_ready;
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wire [AXI_CH-1:0] ch_output_rst_out;
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wire [SEG_CNT*SEG_WIDTH-1:0] ch_output_data;
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wire [SEG_CNT-1:0] ch_output_valid;
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wire [SEG_CNT-1:0] ch_output_ready;
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wire [SEG_CNT*SEG_WIDTH-1:0] ch_output_ctrl_data;
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wire [SEG_CNT-1:0] ch_output_ctrl_valid;
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wire [SEG_CNT-1:0] ch_output_ctrl_ready;
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wire [AXI_CH-1:0] ch_rst_req;
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// config management
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reg [AXI_CH*AXI_ADDR_WIDTH-1:0] cfg_fifo_base_addr_reg = 0;
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reg [LEN_WIDTH-1:0] cfg_fifo_size_mask_reg = 0;
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reg cfg_enable_reg = 0;
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reg cfg_reset_reg = 0;
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always @(posedge clk) begin
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if (cfg_enable_reg) begin
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if (cfg_reset) begin
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cfg_enable_reg <= 1'b0;
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end
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end else begin
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if (cfg_enable) begin
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cfg_enable_reg <= 1'b1;
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end
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cfg_fifo_base_addr_reg <= cfg_fifo_base_addr;
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cfg_fifo_size_mask_reg <= cfg_fifo_size_mask;
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end
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cfg_reset_reg <= cfg_reset;
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if (rst) begin
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cfg_enable_reg <= 0;
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cfg_reset_reg <= 0;
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end
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end
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// status sync
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wire [AXI_CH*(LEN_WIDTH+1)-1:0] sts_fifo_occupancy_int;
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wire [AXI_CH-1:0] sts_fifo_empty_int;
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wire [AXI_CH-1:0] sts_fifo_full_int;
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wire [AXI_CH-1:0] sts_reset_int;
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wire [AXI_CH-1:0] sts_active_int;
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wire sts_hdr_parity_err_int;
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reg [3:0] sts_hdr_parity_err_cnt_reg = 0;
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reg sts_hdr_parity_err_reg = 1'b0;
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reg [2:0] sts_sync_count_reg = 0;
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reg sts_sync_flag_reg = 1'b0;
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(* shreg_extract = "no" *)
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reg [AXI_CH*(LEN_WIDTH+1)-1:0] sts_fifo_occupancy_sync_reg = 0;
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(* shreg_extract = "no" *)
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reg [AXI_CH-1:0] sts_fifo_empty_sync_1_reg = 0, sts_fifo_empty_sync_2_reg = 0;
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(* shreg_extract = "no" *)
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reg [AXI_CH-1:0] sts_fifo_full_sync_1_reg = 0, sts_fifo_full_sync_2_reg = 0;
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(* shreg_extract = "no" *)
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reg [AXI_CH-1:0] sts_reset_sync_1_reg = 0, sts_reset_sync_2_reg = 0;
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(* shreg_extract = "no" *)
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reg [AXI_CH-1:0] sts_active_sync_1_reg = 0, sts_active_sync_2_reg = 0;
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(* shreg_extract = "no" *)
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reg sts_hdr_parity_err_sync_1_reg = 0, sts_hdr_parity_err_sync_2_reg = 0;
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assign sts_fifo_occupancy = sts_fifo_occupancy_sync_reg;
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assign sts_fifo_empty = sts_fifo_empty_sync_2_reg;
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assign sts_fifo_full = sts_fifo_full_sync_2_reg;
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assign sts_reset = sts_reset_sync_2_reg;
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assign sts_active = sts_active_sync_2_reg;
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assign sts_hdr_parity_err = sts_hdr_parity_err_sync_2_reg;
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always @(posedge m_axis_clk) begin
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sts_hdr_parity_err_reg <= 1'b0;
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if (sts_hdr_parity_err_cnt_reg) begin
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sts_hdr_parity_err_reg <= 1'b1;
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sts_hdr_parity_err_cnt_reg <= sts_hdr_parity_err_cnt_reg - 1;
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end
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if (sts_hdr_parity_err_int) begin
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sts_hdr_parity_err_cnt_reg <= 4'hf;
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end
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if (m_axis_rst) begin
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sts_hdr_parity_err_cnt_reg <= 4'h0;
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sts_hdr_parity_err_reg <= 1'b0;
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end
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end
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always @(posedge clk) begin
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sts_sync_count_reg <= sts_sync_count_reg + 1;
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if (sts_sync_count_reg == 0) begin
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sts_sync_flag_reg <= !sts_sync_flag_reg;
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sts_fifo_occupancy_sync_reg <= sts_fifo_occupancy_int;
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end
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sts_fifo_empty_sync_1_reg <= sts_fifo_empty_int;
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sts_fifo_empty_sync_2_reg <= sts_fifo_empty_sync_1_reg;
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sts_fifo_full_sync_1_reg <= sts_fifo_full_int;
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sts_fifo_full_sync_2_reg <= sts_fifo_full_sync_1_reg;
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sts_reset_sync_1_reg <= sts_reset_int;
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sts_reset_sync_2_reg <= sts_reset_sync_1_reg;
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sts_active_sync_1_reg <= sts_active_int;
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sts_active_sync_2_reg <= sts_active_sync_1_reg;
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sts_hdr_parity_err_sync_1_reg <= sts_hdr_parity_err_reg;
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sts_hdr_parity_err_sync_2_reg <= sts_hdr_parity_err_sync_1_reg;
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end
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assign s_axis_rst_out = |ch_input_rst_out;
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axi_vfifo_enc #(
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.SEG_WIDTH(SEG_WIDTH),
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.SEG_CNT(SEG_CNT),
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.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
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.AXIS_KEEP_ENABLE(AXIS_KEEP_ENABLE),
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.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
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.AXIS_LAST_ENABLE(AXIS_LAST_ENABLE),
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.AXIS_ID_ENABLE(AXIS_ID_ENABLE),
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.AXIS_ID_WIDTH(AXIS_ID_WIDTH),
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.AXIS_DEST_ENABLE(AXIS_DEST_ENABLE),
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.AXIS_DEST_WIDTH(AXIS_DEST_WIDTH),
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.AXIS_USER_ENABLE(AXIS_USER_ENABLE),
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.AXIS_USER_WIDTH(AXIS_USER_WIDTH)
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)
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axi_vfifo_enc_inst (
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.clk(s_axis_clk),
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.rst(s_axis_rst),
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/*
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* AXI stream data input
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*/
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.s_axis_tdata(s_axis_tdata),
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.s_axis_tkeep(s_axis_tkeep),
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.s_axis_tvalid(s_axis_tvalid),
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.s_axis_tready(s_axis_tready),
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.s_axis_tlast(s_axis_tlast),
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.s_axis_tid(s_axis_tid),
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.s_axis_tdest(s_axis_tdest),
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.s_axis_tuser(s_axis_tuser),
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/*
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* Segmented data output (to virtual FIFO channel)
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*/
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.fifo_rst_in(s_axis_rst_out),
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.output_data(ch_input_data),
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.output_valid(ch_input_valid),
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.fifo_watermark_in(|ch_input_watermark)
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);
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generate
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genvar n;
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for (n = 0; n < AXI_CH; n = n + 1) begin : axi_ch
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wire ch_clk = m_axi_clk[1*n +: 1];
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wire ch_rst = m_axi_rst[1*n +: 1];
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wire [AXI_ID_WIDTH-1:0] ch_axi_awid;
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wire [AXI_ADDR_WIDTH-1:0] ch_axi_awaddr;
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wire [7:0] ch_axi_awlen;
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wire [2:0] ch_axi_awsize;
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wire [1:0] ch_axi_awburst;
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wire ch_axi_awlock;
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wire [3:0] ch_axi_awcache;
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wire [2:0] ch_axi_awprot;
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wire ch_axi_awvalid;
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wire ch_axi_awready;
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wire [AXI_DATA_WIDTH-1:0] ch_axi_wdata;
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wire [AXI_STRB_WIDTH-1:0] ch_axi_wstrb;
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wire ch_axi_wlast;
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wire ch_axi_wvalid;
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wire ch_axi_wready;
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wire [AXI_ID_WIDTH-1:0] ch_axi_bid;
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wire [1:0] ch_axi_bresp;
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wire ch_axi_bvalid;
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wire ch_axi_bready;
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wire [AXI_ID_WIDTH-1:0] ch_axi_arid;
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wire [AXI_ADDR_WIDTH-1:0] ch_axi_araddr;
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wire [7:0] ch_axi_arlen;
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wire [2:0] ch_axi_arsize;
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wire [1:0] ch_axi_arburst;
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wire ch_axi_arlock;
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wire [3:0] ch_axi_arcache;
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wire [2:0] ch_axi_arprot;
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wire ch_axi_arvalid;
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wire ch_axi_arready;
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wire [AXI_ID_WIDTH-1:0] ch_axi_rid;
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wire [AXI_DATA_WIDTH-1:0] ch_axi_rdata;
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wire [1:0] ch_axi_rresp;
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wire ch_axi_rlast;
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wire ch_axi_rvalid;
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wire ch_axi_rready;
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assign m_axi_awid[AXI_ID_WIDTH*n +: AXI_ID_WIDTH] = ch_axi_awid;
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assign m_axi_awaddr[AXI_ADDR_WIDTH*n +: AXI_ADDR_WIDTH] = ch_axi_awaddr;
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assign m_axi_awlen[8*n +: 8] = ch_axi_awlen;
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assign m_axi_awsize[3*n +: 3] = ch_axi_awsize;
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assign m_axi_awburst[2*n +: 2] = ch_axi_awburst;
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assign m_axi_awlock[1*n +: 1] = ch_axi_awlock;
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assign m_axi_awcache[4*n +: 4] = ch_axi_awcache;
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assign m_axi_awprot[3*n +: 3] = ch_axi_awprot;
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assign m_axi_awvalid[1*n +: 1] = ch_axi_awvalid;
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assign ch_axi_awready = m_axi_awready[1*n +: 1];
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assign m_axi_wdata[AXI_DATA_WIDTH*n +: AXI_DATA_WIDTH] = ch_axi_wdata;
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assign m_axi_wstrb[AXI_STRB_WIDTH*n +: AXI_STRB_WIDTH] = ch_axi_wstrb;
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assign m_axi_wlast[1*n +: 1] = ch_axi_wlast;
|
|
assign m_axi_wvalid[1*n +: 1] = ch_axi_wvalid;
|
|
assign ch_axi_wready = m_axi_wready[1*n +: 1];
|
|
assign ch_axi_bid = m_axi_bid[AXI_ID_WIDTH*n +: AXI_ID_WIDTH];
|
|
assign ch_axi_bresp = m_axi_bresp[2*n +: 2];
|
|
assign ch_axi_bvalid = m_axi_bvalid[1*n +: 1];
|
|
assign m_axi_bready[1*n +: 1] = ch_axi_bready;
|
|
assign m_axi_arid[AXI_ID_WIDTH*n +: AXI_ID_WIDTH] = ch_axi_arid;
|
|
assign m_axi_araddr[AXI_ADDR_WIDTH*n +: AXI_ADDR_WIDTH] = ch_axi_araddr;
|
|
assign m_axi_arlen[8*n +: 8] = ch_axi_arlen;
|
|
assign m_axi_arsize[3*n +: 3] = ch_axi_arsize;
|
|
assign m_axi_arburst[2*n +: 2] = ch_axi_arburst;
|
|
assign m_axi_arlock[1*n +: 1] = ch_axi_arlock;
|
|
assign m_axi_arcache[4*n +: 4] = ch_axi_arcache;
|
|
assign m_axi_arprot[3*n +: 3] = ch_axi_arprot;
|
|
assign m_axi_arvalid[1*n +: 1] = ch_axi_arvalid;
|
|
assign ch_axi_arready = m_axi_arready[1*n +: 1];
|
|
assign ch_axi_rid = m_axi_rid[AXI_ID_WIDTH*n +: AXI_ID_WIDTH];
|
|
assign ch_axi_rdata = m_axi_rdata[AXI_DATA_WIDTH*n +: AXI_DATA_WIDTH];
|
|
assign ch_axi_rresp = m_axi_rresp[2*n +: 2];
|
|
assign ch_axi_rlast = m_axi_rlast[1*n +: 1];
|
|
assign ch_axi_rvalid = m_axi_rvalid[1*n +: 1];
|
|
assign m_axi_rready[1*n +: 1] = ch_axi_rready;
|
|
|
|
// control sync
|
|
(* shreg_extract = "no" *)
|
|
reg ch_cfg_enable_sync_1_reg = 1'b0, ch_cfg_enable_sync_2_reg = 1'b0;
|
|
(* shreg_extract = "no" *)
|
|
reg ch_cfg_reset_sync_1_reg = 1'b0, ch_cfg_reset_sync_2_reg = 1'b0;
|
|
|
|
always @(posedge ch_clk) begin
|
|
ch_cfg_enable_sync_1_reg <= cfg_enable_reg;
|
|
ch_cfg_enable_sync_2_reg <= ch_cfg_enable_sync_1_reg;
|
|
ch_cfg_reset_sync_1_reg <= cfg_reset_reg;
|
|
ch_cfg_reset_sync_2_reg <= ch_cfg_reset_sync_1_reg;
|
|
end
|
|
|
|
// status sync
|
|
wire [LEN_WIDTH+1-1:0] ch_sts_fifo_occupancy;
|
|
reg [LEN_WIDTH+1-1:0] ch_sts_fifo_occupancy_reg;
|
|
|
|
(* shreg_extract = "no" *)
|
|
reg ch_sts_flag_sync_1_reg = 1'b0, ch_sts_flag_sync_2_reg = 1'b0, ch_sts_flag_sync_3_reg = 1'b0;
|
|
|
|
assign sts_fifo_occupancy_int[(LEN_WIDTH+1)*n +: LEN_WIDTH+1] = ch_sts_fifo_occupancy_reg;
|
|
|
|
always @(posedge ch_clk) begin
|
|
ch_sts_flag_sync_1_reg <= sts_sync_flag_reg;
|
|
ch_sts_flag_sync_2_reg <= ch_sts_flag_sync_1_reg;
|
|
ch_sts_flag_sync_3_reg <= ch_sts_flag_sync_2_reg;
|
|
|
|
if (ch_sts_flag_sync_3_reg ^ ch_sts_flag_sync_2_reg) begin
|
|
ch_sts_fifo_occupancy_reg <= ch_sts_fifo_occupancy;
|
|
end
|
|
end
|
|
|
|
axi_vfifo_raw #(
|
|
.SEG_WIDTH(SEG_WIDTH),
|
|
.SEG_CNT(CH_SEG_CNT),
|
|
.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
|
|
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
|
|
.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
|
|
.AXI_ID_WIDTH(AXI_ID_WIDTH),
|
|
.AXI_MAX_BURST_LEN(AXI_MAX_BURST_LEN),
|
|
.LEN_WIDTH(LEN_WIDTH),
|
|
.WRITE_FIFO_DEPTH(WRITE_FIFO_DEPTH),
|
|
.WRITE_MAX_BURST_LEN(WRITE_MAX_BURST_LEN),
|
|
.READ_FIFO_DEPTH(READ_FIFO_DEPTH),
|
|
.READ_MAX_BURST_LEN(READ_MAX_BURST_LEN),
|
|
.WATERMARK_LEVEL(WRITE_FIFO_DEPTH-4),
|
|
.CTRL_OUT_EN(1)
|
|
)
|
|
axi_vfifo_raw_inst (
|
|
.clk(ch_clk),
|
|
.rst(ch_rst),
|
|
|
|
/*
|
|
* Segmented data input (from encode logic)
|
|
*/
|
|
.input_clk(s_axis_clk),
|
|
.input_rst(s_axis_rst),
|
|
.input_rst_out(ch_input_rst_out[n]),
|
|
.input_watermark(ch_input_watermark[n]),
|
|
.input_data(ch_input_data[SEG_WIDTH*CH_SEG_CNT*n +: SEG_WIDTH*CH_SEG_CNT]),
|
|
.input_valid(ch_input_valid[CH_SEG_CNT*n +: CH_SEG_CNT]),
|
|
.input_ready(ch_input_ready[CH_SEG_CNT*n +: CH_SEG_CNT]),
|
|
|
|
/*
|
|
* Segmented data output (to decode logic)
|
|
*/
|
|
.output_clk(m_axis_clk),
|
|
.output_rst(m_axis_rst),
|
|
.output_rst_out(ch_output_rst_out[n]),
|
|
.output_data(ch_output_data[SEG_WIDTH*CH_SEG_CNT*n +: SEG_WIDTH*CH_SEG_CNT]),
|
|
.output_valid(ch_output_valid[CH_SEG_CNT*n +: CH_SEG_CNT]),
|
|
.output_ready(ch_output_ready[CH_SEG_CNT*n +: CH_SEG_CNT]),
|
|
.output_ctrl_data(ch_output_ctrl_data[SEG_WIDTH*CH_SEG_CNT*n +: SEG_WIDTH*CH_SEG_CNT]),
|
|
.output_ctrl_valid(ch_output_ctrl_valid[CH_SEG_CNT*n +: CH_SEG_CNT]),
|
|
.output_ctrl_ready(ch_output_ctrl_ready[CH_SEG_CNT*n +: CH_SEG_CNT]),
|
|
|
|
/*
|
|
* AXI master interface
|
|
*/
|
|
.m_axi_awid(ch_axi_awid),
|
|
.m_axi_awaddr(ch_axi_awaddr),
|
|
.m_axi_awlen(ch_axi_awlen),
|
|
.m_axi_awsize(ch_axi_awsize),
|
|
.m_axi_awburst(ch_axi_awburst),
|
|
.m_axi_awlock(ch_axi_awlock),
|
|
.m_axi_awcache(ch_axi_awcache),
|
|
.m_axi_awprot(ch_axi_awprot),
|
|
.m_axi_awvalid(ch_axi_awvalid),
|
|
.m_axi_awready(ch_axi_awready),
|
|
.m_axi_wdata(ch_axi_wdata),
|
|
.m_axi_wstrb(ch_axi_wstrb),
|
|
.m_axi_wlast(ch_axi_wlast),
|
|
.m_axi_wvalid(ch_axi_wvalid),
|
|
.m_axi_wready(ch_axi_wready),
|
|
.m_axi_bid(ch_axi_bid),
|
|
.m_axi_bresp(ch_axi_bresp),
|
|
.m_axi_bvalid(ch_axi_bvalid),
|
|
.m_axi_bready(ch_axi_bready),
|
|
.m_axi_arid(ch_axi_arid),
|
|
.m_axi_araddr(ch_axi_araddr),
|
|
.m_axi_arlen(ch_axi_arlen),
|
|
.m_axi_arsize(ch_axi_arsize),
|
|
.m_axi_arburst(ch_axi_arburst),
|
|
.m_axi_arlock(ch_axi_arlock),
|
|
.m_axi_arcache(ch_axi_arcache),
|
|
.m_axi_arprot(ch_axi_arprot),
|
|
.m_axi_arvalid(ch_axi_arvalid),
|
|
.m_axi_arready(ch_axi_arready),
|
|
.m_axi_rid(ch_axi_rid),
|
|
.m_axi_rdata(ch_axi_rdata),
|
|
.m_axi_rresp(ch_axi_rresp),
|
|
.m_axi_rlast(ch_axi_rlast),
|
|
.m_axi_rvalid(ch_axi_rvalid),
|
|
.m_axi_rready(ch_axi_rready),
|
|
|
|
/*
|
|
* Reset sync
|
|
*/
|
|
.rst_req_out(ch_rst_req[n]),
|
|
.rst_req_in(|ch_rst_req),
|
|
|
|
/*
|
|
* Configuration
|
|
*/
|
|
.cfg_fifo_base_addr(cfg_fifo_base_addr_reg[AXI_ADDR_WIDTH*n +: AXI_ADDR_WIDTH]),
|
|
.cfg_fifo_size_mask(cfg_fifo_size_mask_reg),
|
|
.cfg_enable(ch_cfg_enable_sync_2_reg),
|
|
.cfg_reset(ch_cfg_reset_sync_2_reg),
|
|
|
|
/*
|
|
* Status
|
|
*/
|
|
.sts_fifo_occupancy(ch_sts_fifo_occupancy),
|
|
.sts_fifo_empty(sts_fifo_empty_int[n]),
|
|
.sts_fifo_full(sts_fifo_full_int[n]),
|
|
.sts_reset(sts_reset_int[n]),
|
|
.sts_active(sts_active_int[n]),
|
|
.sts_write_active(),
|
|
.sts_read_active()
|
|
);
|
|
|
|
end
|
|
|
|
endgenerate
|
|
|
|
assign m_axis_rst_out = |ch_output_rst_out;
|
|
|
|
axi_vfifo_dec #(
|
|
.SEG_WIDTH(SEG_WIDTH),
|
|
.SEG_CNT(SEG_CNT),
|
|
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
|
|
.AXIS_KEEP_ENABLE(AXIS_KEEP_ENABLE),
|
|
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
|
|
.AXIS_LAST_ENABLE(AXIS_LAST_ENABLE),
|
|
.AXIS_ID_ENABLE(AXIS_ID_ENABLE),
|
|
.AXIS_ID_WIDTH(AXIS_ID_WIDTH),
|
|
.AXIS_DEST_ENABLE(AXIS_DEST_ENABLE),
|
|
.AXIS_DEST_WIDTH(AXIS_DEST_WIDTH),
|
|
.AXIS_USER_ENABLE(AXIS_USER_ENABLE),
|
|
.AXIS_USER_WIDTH(AXIS_USER_WIDTH)
|
|
)
|
|
axi_vfifo_dec_inst (
|
|
.clk(m_axis_clk),
|
|
.rst(m_axis_rst),
|
|
|
|
/*
|
|
* Segmented data input (from virtual FIFO channel)
|
|
*/
|
|
.fifo_rst_in(m_axis_rst_out),
|
|
.input_data(ch_output_data),
|
|
.input_valid(ch_output_valid),
|
|
.input_ready(ch_output_ready),
|
|
.input_ctrl_data(ch_output_ctrl_data),
|
|
.input_ctrl_valid(ch_output_ctrl_valid),
|
|
.input_ctrl_ready(ch_output_ctrl_ready),
|
|
|
|
/*
|
|
* AXI stream data output
|
|
*/
|
|
.m_axis_tdata(m_axis_tdata),
|
|
.m_axis_tkeep(m_axis_tkeep),
|
|
.m_axis_tvalid(m_axis_tvalid),
|
|
.m_axis_tready(m_axis_tready),
|
|
.m_axis_tlast(m_axis_tlast),
|
|
.m_axis_tid(m_axis_tid),
|
|
.m_axis_tdest(m_axis_tdest),
|
|
.m_axis_tuser(m_axis_tuser),
|
|
|
|
/*
|
|
* Status
|
|
*/
|
|
.sts_hdr_parity_err(sts_hdr_parity_err_int)
|
|
);
|
|
|
|
endmodule
|
|
|
|
`resetall
|