mirror of
https://github.com/corundum/corundum.git
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239 lines
8.7 KiB
C
239 lines
8.7 KiB
C
/*
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Copyright 2020, The Regents of the University of California.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
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IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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The views and conclusions contained in the software and documentation are those
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of the authors and should not be interpreted as representing official policies,
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either expressed or implied, of The Regents of the University of California.
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*/
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#ifndef FPGA_ID_H
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#define FPGA_ID_H
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#define FPGA_ID_MASK_FULL 0xFFFFFFFF
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#define FPGA_ID_MASK_VER 0xF0000000
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#define FPGA_ID_MASK_PART 0x0FFFF000
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#define FPGA_ID_MASK_MFR 0x00000FFE
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#define FPGA_ID_MASK_NOVER 0x0FFFFFFF
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// Xilinx
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// Spartan 7
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#define FPGA_ID_XC7S6 0x3622093
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#define FPGA_ID_XC7S15 0x3620093
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#define FPGA_ID_XC7S25 0x37C4093
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#define FPGA_ID_XC7S50 0x362F093
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#define FPGA_ID_XC7S75 0x37C8093
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#define FPGA_ID_XC7S100 0x37C7093
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// Artix 7
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#define FPGA_ID_XC7A15T 0x362D093
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#define FPGA_ID_XC7A35T 0x362D093
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#define FPGA_ID_XC7A50T 0x362C093
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#define FPGA_ID_XC7A75T 0x3632093
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#define FPGA_ID_XC7A100T 0x3631093
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#define FPGA_ID_XC7A200T 0x3636093
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// Kintex 7
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#define FPGA_ID_XC7K70T 0x3647093
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#define FPGA_ID_XC7K160T 0x364C093
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#define FPGA_ID_XC7K325T 0x3651093
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#define FPGA_ID_XC7K355T 0x3747093
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#define FPGA_ID_XC7K410T 0x3656093
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#define FPGA_ID_XC7K420T 0x3752093
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#define FPGA_ID_XC7K480T 0x3751093
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// Virtex 7
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#define FPGA_ID_XC7V585T 0x3671093
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#define FPGA_ID_XC7V2000T 0x36B3093
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#define FPGA_ID_XC7VX330T 0x3667093
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#define FPGA_ID_XC7VX415T 0x3682093
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#define FPGA_ID_XC7VX485T 0x3687093
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#define FPGA_ID_XC7VX550T 0x3692093
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#define FPGA_ID_XC7VX690T 0x3691093
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#define FPGA_ID_XC7VX980T 0x3696093
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#define FPGA_ID_XC7VX1140T 0x36D5093
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#define FPGA_ID_XC7VH580T 0x36D9093
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#define FPGA_ID_XC7VH870T 0x36DB093
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// Zynq 7000
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#define FPGA_ID_XC7Z007 0x3723093
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#define FPGA_ID_XC7Z010 0x3722093
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#define FPGA_ID_XC7Z012 0x373C093
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#define FPGA_ID_XC7Z014 0x3728093
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#define FPGA_ID_XC7Z015 0x373B093
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#define FPGA_ID_XC7Z020 0x3727093
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#define FPGA_ID_XC7Z030 0x372C093
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#define FPGA_ID_XC7Z035 0x3732093
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#define FPGA_ID_XC7Z045 0x3731093
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#define FPGA_ID_XC7Z100 0x3736093
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// Kintex UltraScale
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#define FPGA_ID_XCKU025 0x3824093
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#define FPGA_ID_XCKU035 0x3823093
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#define FPGA_ID_XCKU040 0x3822093
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#define FPGA_ID_XCKU060 0x3919093
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#define FPGA_ID_XCKU085 0x380F093
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#define FPGA_ID_XCKU095 0x3844093
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#define FPGA_ID_XCKU115 0x390D093
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// Virtex UltraScale
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#define FPGA_ID_XCVU065 0x3939093
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#define FPGA_ID_XCVU080 0x3843093
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#define FPGA_ID_XCVU095 0x3842093
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#define FPGA_ID_XCVU125 0x392D093
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#define FPGA_ID_XCVU160 0x3933093
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#define FPGA_ID_XCVU190 0x3931093
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#define FPGA_ID_XCVU440 0x396D093
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// Artix UltraScale+
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#define FPGA_ID_XCAU10P 0x4AC5093
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#define FPGA_ID_XCAU15P 0x4AC4093
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#define FPGA_ID_XCAU20P 0x4A65093
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#define FPGA_ID_XCAU25P 0x4A64093
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// Kintex UltraScale+
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#define FPGA_ID_XCKU3P 0x4A63093
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#define FPGA_ID_XCKU5P 0x4A62093
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#define FPGA_ID_XCKU9P 0x484A093
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#define FPGA_ID_XCKU11P 0x4A4E093
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#define FPGA_ID_XCKU13P 0x4A52093
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#define FPGA_ID_XCKU15P 0x4A56093
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#define FPGA_ID_XCKU19P 0x4ACF093
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// Virtex UltraScale+
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#define FPGA_ID_XCVU3P 0x4B39093
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#define FPGA_ID_XCVU5P 0x4B2B093
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#define FPGA_ID_XCVU7P 0x4B29093
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#define FPGA_ID_XCVU9P 0x4B31093
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#define FPGA_ID_XCVU11P 0x4B49093
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#define FPGA_ID_XCVU13P 0x4B51093
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#define FPGA_ID_XCVU19P 0x4BA1093
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#define FPGA_ID_XCVU23P 0x4ACE093
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#define FPGA_ID_XCVU27P 0x4B43093
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#define FPGA_ID_XCVU29P 0x4B41093
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#define FPGA_ID_XCVU31P 0x4B6B093
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#define FPGA_ID_XCVU33P 0x4B69093
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#define FPGA_ID_XCVU35P 0x4B71093
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#define FPGA_ID_XCVU37P 0x4B79093
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#define FPGA_ID_XCVU45P 0x4B73093
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#define FPGA_ID_XCVU47P 0x4B7B093
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#define FPGA_ID_XCVU57P 0x4B61093
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// Zynq UltraScale+
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#define FPGA_ID_XCZU2 0x4711093
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#define FPGA_ID_XCZU3 0x4710093
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#define FPGA_ID_XCZU4 0x4721093
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#define FPGA_ID_XCZU5 0x4720093
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#define FPGA_ID_XCZU6 0x4739093
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#define FPGA_ID_XCZU7 0x4730093
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#define FPGA_ID_XCZU9 0x4738093
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#define FPGA_ID_XCZU11 0x4740093
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#define FPGA_ID_XCZU15 0x4750093
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#define FPGA_ID_XCZU17 0x4759093
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#define FPGA_ID_XCZU19 0x4758093
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#define FPGA_ID_XCZU21 0x47E1093
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#define FPGA_ID_XCZU25 0x47E5093
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#define FPGA_ID_XCZU27 0x47E4093
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#define FPGA_ID_XCZU28 0x47E0093
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#define FPGA_ID_XCZU29 0x47E2093
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#define FPGA_ID_XCZU39 0x47E6093
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#define FPGA_ID_XCZU43 0x47FD093
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#define FPGA_ID_XCZU46 0x47F8093
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#define FPGA_ID_XCZU47 0x47FF093
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#define FPGA_ID_XCZU48 0x47FB093
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#define FPGA_ID_XCZU49 0x47FE093
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// Alveo
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#define FPGA_ID_XCU50 0x4B77093
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#define FPGA_ID_XCU200 0x4B37093
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#define FPGA_ID_XCU250 0x4B57093
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#define FPGA_ID_XCU280 0x4B7D093
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// Intel
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// Stratix 10
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#define FPGA_ID_1SG10MH_U1 0x032270DD
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#define FPGA_ID_1SG10MH_U2 0x0322F0DD
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#define FPGA_ID_1SG040H 0x032200DD
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#define FPGA_ID_1SG040H_NL 0x032A00DD
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#define FPGA_ID_1SG065H 0x032210DD
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#define FPGA_ID_1SG065H_NL 0x032A10DD
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#define FPGA_ID_1SG085H 0x132220DD
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#define FPGA_ID_1SG110H 0x032220DD
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#define FPGA_ID_1SG110H_NL 0x032A20DD
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#define FPGA_ID_1SG165H 0xF32250DD
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#define FPGA_ID_1SG166H 0x532240DD
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#define FPGA_ID_1SG166H_NL 0x5322C0DD
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#define FPGA_ID_1SG210H 0xE32250DD
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#define FPGA_ID_1SG210H_ES1 0x232250DD
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#define FPGA_ID_1SG211H 0x432240DD
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#define FPGA_ID_1SG250L 0xD32150DD
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#define FPGA_ID_1SG250H 0xD32250DD
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#define FPGA_ID_1SG280L 0xC32150DD
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#define FPGA_ID_1SG280L_NL 0xC32950DD
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#define FPGA_ID_1SG280L_ES1 0x032150DD
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#define FPGA_ID_1SG280L_ES2 0x032250DD
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#define FPGA_ID_1SG280L_ES3 0xC32150DD
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#define FPGA_ID_1SG280H 0xC32250DD
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#define FPGA_ID_1SG280H_NL 0xC32A50DD
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#define FPGA_ID_1SG280H_ES1 0x032250DD
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#define FPGA_ID_1SG280H_ES2 0xC32150DD
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#define FPGA_ID_1SG280H_ES3 0xC32250DD
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#define FPGA_ID_1SX040H 0x032280DD
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#define FPGA_ID_1SX065H 0x032290DD
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#define FPGA_ID_1SX085H 0x1322A0DD
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#define FPGA_ID_1SX110H 0x0322A0DD
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#define FPGA_ID_1SX165H 0xF322D0DD
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#define FPGA_ID_1SX210H 0xE322D0DD
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#define FPGA_ID_1SX250L 0xD321D0DD
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#define FPGA_ID_1SX250H 0xD322D0DD
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#define FPGA_ID_1SX280L 0xC321D0DD
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#define FPGA_ID_1SX280L_ES1 0x4321D0DD
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#define FPGA_ID_1SX280L_ES2 0x4321D0DD
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#define FPGA_ID_1SX280H 0xC322D0DD
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#define FPGA_ID_1SX280H_ES1 0x4322D0DD
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#define FPGA_ID_1SX280H_ES2 0xC322D0DD
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#define FPGA_ID_1ST040E 0x032380DD
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#define FPGA_ID_1ST040E_NL 0x032B00DD
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#define FPGA_ID_1ST085E 0x1323A0DD
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#define FPGA_ID_1ST110E 0x0323A0DD
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#define FPGA_ID_1ST110E_NL 0x032B20DD
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#define FPGA_ID_1ST165E 0x532340DD
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#define FPGA_ID_1ST210E 0x432340DD
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#define FPGA_ID_1ST210E_ES1 0x032340DD
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#define FPGA_ID_1ST250E 0xD323D0DD
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#define FPGA_ID_1ST280E 0xC323D0DD
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#define FPGA_ID_1ST280E_ES1 0xC323D0DD
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#define FPGA_ID_1SM16BE 0x732BC0DD
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#define FPGA_ID_1SM16BE_ES1 0x732BC0DD
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#define FPGA_ID_1SM16BH 0x732AC0DD
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#define FPGA_ID_1SM16BH_ES1 0x332AC0DD
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#define FPGA_ID_1SM16CH 0x532AC0DD
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#define FPGA_ID_1SM16CH_ES1 0x132AC0DD
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#define FPGA_ID_1SM21BE 0x632BC0DD
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#define FPGA_ID_1SM21BE_ES1 0x632BC0DD
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#define FPGA_ID_1SM21BH 0x632AC0DD
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#define FPGA_ID_1SM21BH_ES1 0x232AC0DD
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#define FPGA_ID_1SM21CH 0x432AC0DD
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#define FPGA_ID_1SM21CH_ES1 0x032AC0DD
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#define FPGA_ID_1SD110P 0x0324A0DD
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#define FPGA_ID_1SD110P_NL 0x032C20DD
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#define FPGA_ID_1SD21BP 0x632CC0DD
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#define FPGA_ID_1SD280P 0xC32450DD
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const char *get_fpga_part(int id);
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#endif /* FPGA_ID_H */
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