mirror of
https://github.com/corundum/corundum.git
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413 lines
12 KiB
Python
Executable File
413 lines
12 KiB
Python
Executable File
#!/usr/bin/env python
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"""
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Copyright (c) 2014-2017 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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"""
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from myhdl import *
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import os
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import axis_ep
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module = 'axis_srl_fifo'
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testbench = 'test_%s' % module
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srcs = []
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srcs.append("../rtl/%s.v" % module)
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srcs.append("%s.v" % testbench)
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src = ' '.join(srcs)
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build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
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def bench():
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# Parameters
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DEPTH = 4
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DATA_WIDTH = 8
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# Inputs
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clk = Signal(bool(0))
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rst = Signal(bool(0))
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current_test = Signal(intbv(0)[8:])
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input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
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input_axis_tvalid = Signal(bool(0))
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input_axis_tlast = Signal(bool(0))
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input_axis_tuser = Signal(bool(0))
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output_axis_tready = Signal(bool(0))
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# Outputs
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input_axis_tready = Signal(bool(0))
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output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
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output_axis_tvalid = Signal(bool(0))
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output_axis_tlast = Signal(bool(0))
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output_axis_tuser = Signal(bool(0))
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count = Signal(intbv(0)[3:])
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# sources and sinks
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source_pause = Signal(bool(0))
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sink_pause = Signal(bool(0))
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source = axis_ep.AXIStreamSource()
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source_logic = source.create_logic(
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clk,
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rst,
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tdata=input_axis_tdata,
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tvalid=input_axis_tvalid,
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tready=input_axis_tready,
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tlast=input_axis_tlast,
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tuser=input_axis_tuser,
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pause=source_pause,
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name='source'
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)
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sink = axis_ep.AXIStreamSink()
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sink_logic = sink.create_logic(
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clk,
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rst,
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tdata=output_axis_tdata,
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tvalid=output_axis_tvalid,
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tready=output_axis_tready,
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tlast=output_axis_tlast,
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tuser=output_axis_tuser,
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pause=sink_pause,
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name='sink'
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)
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# DUT
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if os.system(build_cmd):
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raise Exception("Error running build command")
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dut = Cosimulation(
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"vvp -m myhdl %s.vvp -lxt2" % testbench,
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clk=clk,
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rst=rst,
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current_test=current_test,
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input_axis_tdata=input_axis_tdata,
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input_axis_tvalid=input_axis_tvalid,
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input_axis_tready=input_axis_tready,
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input_axis_tlast=input_axis_tlast,
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input_axis_tuser=input_axis_tuser,
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output_axis_tdata=output_axis_tdata,
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output_axis_tvalid=output_axis_tvalid,
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output_axis_tready=output_axis_tready,
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output_axis_tlast=output_axis_tlast,
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output_axis_tuser=output_axis_tuser,
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count=count
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)
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@always(delay(4))
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def clkgen():
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clk.next = not clk
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@instance
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def check():
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yield delay(100)
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yield clk.posedge
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rst.next = 1
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yield clk.posedge
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rst.next = 0
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yield clk.posedge
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yield delay(100)
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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print("test 1: test packet")
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current_test.next = 1
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test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
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b'\x5A\x51\x52\x53\x54\x55' +
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b'\x80\x00' +
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b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
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source.send(test_frame)
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yield clk.posedge
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yield output_axis_tlast.posedge
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yield clk.posedge
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yield clk.posedge
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rx_frame = sink.recv()
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assert rx_frame == test_frame
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yield delay(100)
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yield clk.posedge
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print("test 2: longer packet")
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current_test.next = 2
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test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
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b'\x5A\x51\x52\x53\x54\x55' +
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b'\x80\x00' +
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bytearray(range(256)))
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source.send(test_frame)
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yield clk.posedge
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yield output_axis_tlast.posedge
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yield clk.posedge
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yield clk.posedge
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rx_frame = sink.recv()
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assert rx_frame == test_frame
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yield clk.posedge
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print("test 3: test packet with pauses")
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current_test.next = 3
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test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
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b'\x5A\x51\x52\x53\x54\x55' +
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b'\x80\x00' +
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b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
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source.send(test_frame)
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yield clk.posedge
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yield delay(64)
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yield clk.posedge
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source_pause.next = True
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yield delay(32)
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yield clk.posedge
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source_pause.next = False
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yield delay(64)
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yield clk.posedge
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sink_pause.next = True
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yield delay(32)
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yield clk.posedge
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sink_pause.next = False
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yield output_axis_tlast.posedge
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yield clk.posedge
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yield clk.posedge
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rx_frame = sink.recv()
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assert rx_frame == test_frame
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yield delay(100)
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yield clk.posedge
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print("test 4: back-to-back packets")
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current_test.next = 4
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test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
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b'\x5A\x51\x52\x53\x54\x55' +
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b'\x80\x00' +
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b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
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test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
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b'\x5A\x51\x52\x53\x54\x55' +
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b'\x80\x00' +
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b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
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source.send(test_frame1)
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source.send(test_frame2)
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yield clk.posedge
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yield output_axis_tlast.posedge
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yield clk.posedge
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yield output_axis_tlast.posedge
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yield clk.posedge
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yield clk.posedge
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rx_frame = sink.recv()
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assert rx_frame == test_frame1
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rx_frame = sink.recv()
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assert rx_frame == test_frame2
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yield delay(100)
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yield clk.posedge
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print("test 5: alternate pause source")
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current_test.next = 5
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test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
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b'\x5A\x51\x52\x53\x54\x55' +
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b'\x80\x00' +
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b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
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test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
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b'\x5A\x51\x52\x53\x54\x55' +
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b'\x80\x00' +
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b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
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source.send(test_frame1)
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source.send(test_frame2)
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yield clk.posedge
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while input_axis_tvalid or output_axis_tvalid:
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source_pause.next = True
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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source_pause.next = False
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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rx_frame = sink.recv()
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assert rx_frame == test_frame1
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rx_frame = sink.recv()
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assert rx_frame == test_frame2
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yield delay(100)
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yield clk.posedge
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print("test 6: alternate pause sink")
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current_test.next = 6
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test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
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b'\x5A\x51\x52\x53\x54\x55' +
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b'\x80\x00' +
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b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
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test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
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b'\x5A\x51\x52\x53\x54\x55' +
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b'\x80\x00' +
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b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
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source.send(test_frame1)
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source.send(test_frame2)
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yield clk.posedge
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while input_axis_tvalid or output_axis_tvalid:
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sink_pause.next = True
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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sink_pause.next = False
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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rx_frame = sink.recv()
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assert rx_frame == test_frame1
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rx_frame = sink.recv()
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assert rx_frame == test_frame2
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yield delay(100)
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yield clk.posedge
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print("test 7: tuser assert")
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current_test.next = 7
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test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
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b'\x5A\x51\x52\x53\x54\x55' +
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b'\x80\x00' +
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b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
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test_frame.user = 1
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source.send(test_frame)
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yield clk.posedge
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yield output_axis_tlast.posedge
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yield clk.posedge
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yield clk.posedge
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rx_frame = sink.recv()
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assert rx_frame == test_frame
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assert rx_frame.user[-1]
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yield delay(100)
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yield clk.posedge
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print("test 8: initial sink pause")
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current_test.next = 8
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test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
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sink_pause.next = 1
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source.send(test_frame)
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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sink_pause.next = 0
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yield output_axis_tlast.posedge
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yield clk.posedge
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yield clk.posedge
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rx_frame = sink.recv()
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assert rx_frame == test_frame
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yield delay(100)
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yield clk.posedge
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print("test 9: initial sink pause, reset")
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current_test.next = 9
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test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
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sink_pause.next = 1
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source.send(test_frame)
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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rst.next = 1
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yield clk.posedge
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rst.next = 0
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sink_pause.next = 0
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yield delay(100)
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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assert sink.empty()
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yield delay(100)
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raise StopSimulation
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return dut, source_logic, sink_logic, clkgen, check
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def test_bench():
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os.chdir(os.path.dirname(os.path.abspath(__file__)))
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sim = Simulation(bench())
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sim.run()
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if __name__ == '__main__':
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print("Running test...")
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test_bench()
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