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corundum/example/S10DX_DK/fpga/rtl
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Alex Forencich a53509de68 Add instance names 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-07-22 22:34:04 -07:00
..
common
Add example design for Stratix 10 DX dev kit
2022-07-13 00:31:39 -07:00
debounce_switch.v
Add example design for Stratix 10 DX dev kit
2022-07-13 00:31:39 -07:00
fpga_core.v
Add example design for Stratix 10 DX dev kit
2022-07-13 00:31:39 -07:00
fpga.v
Add instance names
2022-07-22 22:34:04 -07:00
sync_reset.v
Add example design for Stratix 10 DX dev kit
2022-07-13 00:31:39 -07:00
sync_signal.v
Add example design for Stratix 10 DX dev kit
2022-07-13 00:31:39 -07:00