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corundum/fpga/mqnic/DE10_Agilex/fpga_100g
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Alex Forencich 3f57c2143b fpga/mqnic: PCIe interface updates 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-08-03 12:28:49 -07:00
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common
Add 100G mqnic design for DE10-Agilex
2022-07-21 18:49:35 -07:00
fpga_24AR0
fpga/mqnic: PCIe interface updates
2022-08-03 12:28:49 -07:00
fpga_24B
fpga/mqnic: PCIe interface updates
2022-08-03 12:28:49 -07:00
ip
Add 100G mqnic design for DE10-Agilex
2022-07-21 18:49:35 -07:00
rtl
fpga/mqnic: Disable PTP on 100G E-tile designs
2022-08-03 00:41:53 -07:00
tb/fpga_core
fpga/mqnic: PCIe interface updates
2022-08-03 12:28:49 -07:00
app
Add 100G mqnic design for DE10-Agilex
2022-07-21 18:49:35 -07:00
fpga.qsf
Add 100G mqnic design for DE10-Agilex
2022-07-21 18:49:35 -07:00
fpga.sdc
Add 100G mqnic design for DE10-Agilex
2022-07-21 18:49:35 -07:00
lib
Add 100G mqnic design for DE10-Agilex
2022-07-21 18:49:35 -07:00
README.md
Add 100G mqnic design for DE10-Agilex
2022-07-21 18:49:35 -07:00

README.md

Corundum mqnic for DE10-Agilex

Introduction

This design targets the Terasic DE10-Agilex FPGA development board.

  • FPGA: AGFB014R24B2E2V
  • PHY: E-Tile

How to build

Run make to build. Ensure that the Intel Quartus Prime Pro toolchain components are in PATH.

Run make to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled.

How to test

Run make program to program the DE10-Agilex board with the Intel software. Then load the driver with insmod mqnic.ko. Check dmesg for output from driver initialization.