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264 lines
9.6 KiB
Verilog
264 lines
9.6 KiB
Verilog
/*
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Copyright (c) 2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* Ultrascale PCIe RC demultiplexer
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*/
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module pcie_us_axis_rc_demux #
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(
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// Output count
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parameter M_COUNT = 2,
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// Width of PCIe AXI stream interfaces in bits
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parameter AXIS_PCIE_DATA_WIDTH = 256,
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// PCIe AXI stream tkeep signal width (words per cycle)
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parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32),
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// PCIe AXI stream RC tuser signal width
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parameter AXIS_PCIE_RC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 75 : 161
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI input (RC)
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*/
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input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rc_tdata,
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input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rc_tkeep,
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input wire s_axis_rc_tvalid,
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output wire s_axis_rc_tready,
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input wire s_axis_rc_tlast,
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input wire [AXIS_PCIE_RC_USER_WIDTH-1:0] s_axis_rc_tuser,
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/*
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* AXI output (RC)
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*/
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output wire [M_COUNT*AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rc_tdata,
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output wire [M_COUNT*AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rc_tkeep,
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output wire [M_COUNT-1:0] m_axis_rc_tvalid,
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input wire [M_COUNT-1:0] m_axis_rc_tready,
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output wire [M_COUNT-1:0] m_axis_rc_tlast,
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output wire [M_COUNT*AXIS_PCIE_RC_USER_WIDTH-1:0] m_axis_rc_tuser,
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/*
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* Fields
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*/
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output wire [15:0] requester_id,
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/*
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* Control
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*/
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input wire enable,
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input wire drop,
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input wire [M_COUNT-1:0] select
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);
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parameter CL_M_COUNT = $clog2(M_COUNT);
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// bus width assertions
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initial begin
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if (AXIS_PCIE_DATA_WIDTH != 64 && AXIS_PCIE_DATA_WIDTH != 128 && AXIS_PCIE_DATA_WIDTH != 256 && AXIS_PCIE_DATA_WIDTH != 512) begin
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$error("Error: PCIe interface width must be 64, 128, 256, or 512 (instance %m)");
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$finish;
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end
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if (AXIS_PCIE_KEEP_WIDTH * 32 != AXIS_PCIE_DATA_WIDTH) begin
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$error("Error: PCIe interface requires dword (32-bit) granularity (instance %m)");
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$finish;
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end
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end
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reg [CL_M_COUNT-1:0] select_reg = {CL_M_COUNT{1'b0}}, select_ctl, select_next;
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reg drop_reg = 1'b0, drop_ctl, drop_next;
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reg frame_reg = 1'b0, frame_ctl, frame_next;
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reg s_axis_rc_tready_reg = 1'b0, s_axis_rc_tready_next;
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// internal datapath
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reg [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rc_tdata_int;
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reg [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rc_tkeep_int;
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reg [M_COUNT-1:0] m_axis_rc_tvalid_int;
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reg m_axis_rc_tready_int_reg = 1'b0;
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reg m_axis_rc_tlast_int;
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reg [AXIS_PCIE_RC_USER_WIDTH-1:0] m_axis_rc_tuser_int;
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wire m_axis_rc_tready_int_early;
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assign s_axis_rc_tready = s_axis_rc_tready_reg && enable;
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assign requester_id = s_axis_rc_tdata[63:48];
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integer i;
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always @* begin
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select_next = select_reg;
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select_ctl = select_reg;
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drop_next = drop_reg;
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drop_ctl = drop_reg;
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frame_next = frame_reg;
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frame_ctl = frame_reg;
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s_axis_rc_tready_next = 1'b0;
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if (s_axis_rc_tvalid && s_axis_rc_tready) begin
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// end of frame detection
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if (s_axis_rc_tlast) begin
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frame_next = 1'b0;
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drop_next = 1'b0;
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end
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end
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if (!frame_reg && s_axis_rc_tvalid && s_axis_rc_tready) begin
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// start of frame, grab select value
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select_ctl = 0;
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drop_ctl = 1'b1;
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frame_ctl = 1'b1;
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for (i = M_COUNT-1; i >= 0; i = i - 1) begin
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if (select[i]) begin
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select_ctl = i;
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drop_ctl = 1'b0;
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end
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end
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drop_ctl = drop_ctl || drop;
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if (!(s_axis_rc_tready && s_axis_rc_tvalid && s_axis_rc_tlast)) begin
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select_next = select_ctl;
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drop_next = drop_ctl;
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frame_next = 1'b1;
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end
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end
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s_axis_rc_tready_next = m_axis_rc_tready_int_early || drop_ctl;
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m_axis_rc_tdata_int = s_axis_rc_tdata;
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m_axis_rc_tkeep_int = s_axis_rc_tkeep;
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m_axis_rc_tvalid_int = (s_axis_rc_tvalid && s_axis_rc_tready && !drop_ctl) << select_ctl;
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m_axis_rc_tlast_int = s_axis_rc_tlast;
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m_axis_rc_tuser_int = s_axis_rc_tuser;
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end
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always @(posedge clk) begin
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if (rst) begin
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select_reg <= 2'd0;
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drop_reg <= 1'b0;
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frame_reg <= 1'b0;
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s_axis_rc_tready_reg <= 1'b0;
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end else begin
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select_reg <= select_next;
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drop_reg <= drop_next;
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frame_reg <= frame_next;
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s_axis_rc_tready_reg <= s_axis_rc_tready_next;
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end
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end
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// output datapath logic
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reg [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rc_tdata_reg = {AXIS_PCIE_DATA_WIDTH{1'b0}};
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reg [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rc_tkeep_reg = {AXIS_PCIE_KEEP_WIDTH{1'b0}};
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reg [M_COUNT-1:0] m_axis_rc_tvalid_reg = {M_COUNT{1'b0}}, m_axis_rc_tvalid_next;
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reg m_axis_rc_tlast_reg = 1'b0;
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reg [AXIS_PCIE_RC_USER_WIDTH-1:0] m_axis_rc_tuser_reg = {AXIS_PCIE_RC_USER_WIDTH{1'b0}};
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reg [AXIS_PCIE_DATA_WIDTH-1:0] temp_m_axis_rc_tdata_reg = {AXIS_PCIE_DATA_WIDTH{1'b0}};
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reg [AXIS_PCIE_KEEP_WIDTH-1:0] temp_m_axis_rc_tkeep_reg = {AXIS_PCIE_KEEP_WIDTH{1'b0}};
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reg [M_COUNT-1:0] temp_m_axis_rc_tvalid_reg = {M_COUNT{1'b0}}, temp_m_axis_rc_tvalid_next;
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reg temp_m_axis_rc_tlast_reg = 1'b0;
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reg [AXIS_PCIE_RC_USER_WIDTH-1:0] temp_m_axis_rc_tuser_reg = {AXIS_PCIE_RC_USER_WIDTH{1'b0}};
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// datapath control
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reg store_axis_int_to_output;
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reg store_axis_int_to_temp;
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reg store_axis_rc_temp_to_output;
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assign m_axis_rc_tdata = {M_COUNT{m_axis_rc_tdata_reg}};
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assign m_axis_rc_tkeep = {M_COUNT{m_axis_rc_tkeep_reg}};
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assign m_axis_rc_tvalid = m_axis_rc_tvalid_reg;
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assign m_axis_rc_tlast = {M_COUNT{m_axis_rc_tlast_reg}};
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assign m_axis_rc_tuser = {M_COUNT{m_axis_rc_tuser_reg}};
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// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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assign m_axis_rc_tready_int_early = (m_axis_rc_tready & m_axis_rc_tvalid) || (!temp_m_axis_rc_tvalid_reg && (!m_axis_rc_tvalid || !m_axis_rc_tvalid_int));
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always @* begin
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// transfer sink ready state to source
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m_axis_rc_tvalid_next = m_axis_rc_tvalid_reg;
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temp_m_axis_rc_tvalid_next = temp_m_axis_rc_tvalid_reg;
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store_axis_int_to_output = 1'b0;
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store_axis_int_to_temp = 1'b0;
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store_axis_rc_temp_to_output = 1'b0;
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if (m_axis_rc_tready_int_reg) begin
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// input is ready
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if ((m_axis_rc_tready & m_axis_rc_tvalid) || !m_axis_rc_tvalid) begin
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// output is ready or currently not valid, transfer data to output
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m_axis_rc_tvalid_next = m_axis_rc_tvalid_int;
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store_axis_int_to_output = 1'b1;
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end else begin
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// output is not ready, store input in temp
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temp_m_axis_rc_tvalid_next = m_axis_rc_tvalid_int;
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store_axis_int_to_temp = 1'b1;
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end
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end else if (m_axis_rc_tready & m_axis_rc_tvalid) begin
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// input is not ready, but output is ready
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m_axis_rc_tvalid_next = temp_m_axis_rc_tvalid_reg;
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temp_m_axis_rc_tvalid_next = 1'b0;
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store_axis_rc_temp_to_output = 1'b1;
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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m_axis_rc_tvalid_reg <= {M_COUNT{1'b0}};
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m_axis_rc_tready_int_reg <= 1'b0;
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temp_m_axis_rc_tvalid_reg <= 1'b0;
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end else begin
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m_axis_rc_tvalid_reg <= m_axis_rc_tvalid_next;
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m_axis_rc_tready_int_reg <= m_axis_rc_tready_int_early;
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temp_m_axis_rc_tvalid_reg <= temp_m_axis_rc_tvalid_next;
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end
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// datapath
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if (store_axis_int_to_output) begin
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m_axis_rc_tdata_reg <= m_axis_rc_tdata_int;
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m_axis_rc_tkeep_reg <= m_axis_rc_tkeep_int;
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m_axis_rc_tlast_reg <= m_axis_rc_tlast_int;
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m_axis_rc_tuser_reg <= m_axis_rc_tuser_int;
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end else if (store_axis_rc_temp_to_output) begin
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m_axis_rc_tdata_reg <= temp_m_axis_rc_tdata_reg;
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m_axis_rc_tkeep_reg <= temp_m_axis_rc_tkeep_reg;
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m_axis_rc_tlast_reg <= temp_m_axis_rc_tlast_reg;
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m_axis_rc_tuser_reg <= temp_m_axis_rc_tuser_reg;
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end
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if (store_axis_int_to_temp) begin
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temp_m_axis_rc_tdata_reg <= m_axis_rc_tdata_int;
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temp_m_axis_rc_tkeep_reg <= m_axis_rc_tkeep_int;
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temp_m_axis_rc_tlast_reg <= m_axis_rc_tlast_int;
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temp_m_axis_rc_tuser_reg <= m_axis_rc_tuser_int;
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end
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end
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endmodule
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