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75 lines
2.1 KiB
Verilog
75 lines
2.1 KiB
Verilog
/*
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Copyright (c) 2020 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* 7 segment display hexadecimal encoding
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*/
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module hex_display #(
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parameter INVERT = 0
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)
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(
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input wire [3:0] in,
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input wire enable,
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output wire [6:0] out
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);
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reg [6:0] enc;
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always @* begin
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enc <= 7'b0000000;
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if (enable) begin
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case (in)
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4'h0: enc <= 7'b0111111;
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4'h1: enc <= 7'b0000110;
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4'h2: enc <= 7'b1011011;
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4'h3: enc <= 7'b1001111;
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4'h4: enc <= 7'b1100110;
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4'h5: enc <= 7'b1101101;
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4'h6: enc <= 7'b1111101;
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4'h7: enc <= 7'b0000111;
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4'h8: enc <= 7'b1111111;
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4'h9: enc <= 7'b1101111;
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4'ha: enc <= 7'b1110111;
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4'hb: enc <= 7'b1111100;
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4'hc: enc <= 7'b0111001;
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4'hd: enc <= 7'b1011110;
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4'he: enc <= 7'b1111001;
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4'hf: enc <= 7'b1110001;
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endcase
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end
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end
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assign out = INVERT ? ~enc : enc;
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endmodule
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`resetall
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