mirror of
https://github.com/corundum/corundum.git
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1140 lines
27 KiB
Verilog
1140 lines
27 KiB
Verilog
/*
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Copyright (c) 2016-2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1 ns / 1 ps
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`default_nettype none
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module fpga (
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/*
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* Clock: 50MHz
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*/
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input wire sys_clk,
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/*
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* Clock: 200MHz
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*/
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//input wire clk_ddr3_p,
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//input wire clk_ddr3_n,
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/*
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* Clock: User
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*/
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//input wire clk_usr_p,
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//input wire clk_usr_pr_n,
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/*
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* Reset: Push button, active low
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*/
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input wire reset_n,
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/*
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* GPIO
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*/
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input wire [1:0] sw,
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input wire [3:0] jp,
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output wire [3:0] led,
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/*
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* Silicon Labs CP2102 USB UART
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*/
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output wire uart_rst,
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input wire uart_suspend,
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output wire uart_ri,
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output wire uart_dcd,
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input wire uart_dtr,
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output wire uart_dsr,
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input wire uart_txd,
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output wire uart_rxd,
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input wire uart_rts,
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output wire uart_cts,
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/*
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* Clock muxes
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*/
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inout wire clk_gth_scl,
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inout wire clk_gth_sda,
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output wire clk_gth_rst_n,
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input wire clk_gthl_alm,
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input wire clk_gthl_lol,
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input wire clk_gthr_alm,
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input wire clk_gthr_lol,
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/*
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* AirMax I/O
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*/
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output wire amh_right_mdc,
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inout wire amh_right_mdio,
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output wire amh_right_phy_rst_n,
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output wire amh_left_mdc,
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inout wire amh_left_mdio,
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output wire amh_left_phy_rst_n,
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/*
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* 10G Ethernet
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*/
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input wire gth_quad_A_refclk_p,
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input wire gth_quad_A_refclk_n,
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output wire gth_quad_A_txp_0,
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output wire gth_quad_A_txn_0,
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input wire gth_quad_A_rxp_0,
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input wire gth_quad_A_rxn_0,
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output wire gth_quad_A_txp_1,
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output wire gth_quad_A_txn_1,
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input wire gth_quad_A_rxp_1,
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input wire gth_quad_A_rxn_1,
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output wire gth_quad_A_txp_2,
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output wire gth_quad_A_txn_2,
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input wire gth_quad_A_rxp_2,
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input wire gth_quad_A_rxn_2,
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output wire gth_quad_A_txp_3,
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output wire gth_quad_A_txn_3,
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input wire gth_quad_A_rxp_3,
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input wire gth_quad_A_rxn_3,
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input wire gth_quad_B_refclk_p,
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input wire gth_quad_B_refclk_n,
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output wire gth_quad_B_txp_0,
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output wire gth_quad_B_txn_0,
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input wire gth_quad_B_rxp_0,
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input wire gth_quad_B_rxn_0,
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output wire gth_quad_B_txp_1,
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output wire gth_quad_B_txn_1,
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input wire gth_quad_B_rxp_1,
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input wire gth_quad_B_rxn_1,
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output wire gth_quad_B_txp_2,
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output wire gth_quad_B_txn_2,
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input wire gth_quad_B_rxp_2,
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input wire gth_quad_B_rxn_2,
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output wire gth_quad_B_txp_3,
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output wire gth_quad_B_txn_3,
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input wire gth_quad_B_rxp_3,
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input wire gth_quad_B_rxn_3,
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input wire gth_quad_C_refclk_p,
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input wire gth_quad_C_refclk_n,
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output wire gth_quad_C_txp_0,
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output wire gth_quad_C_txn_0,
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input wire gth_quad_C_rxp_0,
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input wire gth_quad_C_rxn_0,
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output wire gth_quad_C_txp_1,
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output wire gth_quad_C_txn_1,
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input wire gth_quad_C_rxp_1,
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input wire gth_quad_C_rxn_1,
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output wire gth_quad_C_txp_2,
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output wire gth_quad_C_txn_2,
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input wire gth_quad_C_rxp_2,
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input wire gth_quad_C_rxn_2,
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output wire gth_quad_C_txp_3,
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output wire gth_quad_C_txn_3,
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input wire gth_quad_C_rxp_3,
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input wire gth_quad_C_rxn_3,
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input wire gth_quad_D_refclk_p,
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input wire gth_quad_D_refclk_n,
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output wire gth_quad_D_txp_0,
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output wire gth_quad_D_txn_0,
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input wire gth_quad_D_rxp_0,
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input wire gth_quad_D_rxn_0,
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output wire gth_quad_D_txp_1,
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output wire gth_quad_D_txn_1,
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input wire gth_quad_D_rxp_1,
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input wire gth_quad_D_rxn_1,
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output wire gth_quad_D_txp_2,
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output wire gth_quad_D_txn_2,
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input wire gth_quad_D_rxp_2,
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input wire gth_quad_D_rxn_2,
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output wire gth_quad_D_txp_3,
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output wire gth_quad_D_txn_3,
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input wire gth_quad_D_rxp_3,
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input wire gth_quad_D_rxn_3,
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input wire gth_quad_E_refclk_p,
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input wire gth_quad_E_refclk_n,
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output wire gth_quad_E_txp_0,
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output wire gth_quad_E_txn_0,
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input wire gth_quad_E_rxp_0,
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input wire gth_quad_E_rxn_0,
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output wire gth_quad_E_txp_1,
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output wire gth_quad_E_txn_1,
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input wire gth_quad_E_rxp_1,
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input wire gth_quad_E_rxn_1,
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output wire gth_quad_E_txp_2,
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output wire gth_quad_E_txn_2,
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input wire gth_quad_E_rxp_2,
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input wire gth_quad_E_rxn_2,
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output wire gth_quad_E_txp_3,
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output wire gth_quad_E_txn_3,
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input wire gth_quad_E_rxp_3,
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input wire gth_quad_E_rxn_3,
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input wire gth_quad_F_refclk_p,
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input wire gth_quad_F_refclk_n,
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output wire gth_quad_F_txp_0,
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output wire gth_quad_F_txn_0,
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input wire gth_quad_F_rxp_0,
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input wire gth_quad_F_rxn_0,
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output wire gth_quad_F_txp_1,
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output wire gth_quad_F_txn_1,
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input wire gth_quad_F_rxp_1,
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input wire gth_quad_F_rxn_1,
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output wire gth_quad_F_txp_2,
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output wire gth_quad_F_txn_2,
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input wire gth_quad_F_rxp_2,
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input wire gth_quad_F_rxn_2,
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output wire gth_quad_F_txp_3,
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output wire gth_quad_F_txn_3,
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input wire gth_quad_F_rxp_3,
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input wire gth_quad_F_rxn_3
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);
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/*
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* Clock: 50MHz
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*/
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wire sys_clk_ibufg;
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wire sys_clk_int;
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/*
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* Clock: 156.25 MHz
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*/
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wire clk_156mhz;
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/*
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* Synchronous reset
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*/
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wire sys_rst;
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wire rst_156mhz;
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/*
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* GPIO
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*/
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wire [1:0] sw_int;
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wire [3:0] jp_int;
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wire [3:0] led_int;
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/*
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* Silicon Labs CP2102 USB UART
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*/
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wire uart_sys_rst;
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wire uart_suspend_int;
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wire uart_ri_int;
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wire uart_dcd_int;
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wire uart_dtr_int;
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wire uart_dsr_int;
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wire uart_txd_int;
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wire uart_rxd_int;
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wire uart_rts_int;
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wire uart_cts_int;
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/*
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* Clock muxes
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*/
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wire clk_gth_scl_i;
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wire clk_gth_scl_o;
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wire clk_gth_scl_t;
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wire clk_gth_sda_i;
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wire clk_gth_sda_o;
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wire clk_gth_sda_t;
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wire clk_gthl_alm_int;
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wire clk_gthl_lol_int;
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wire clk_gthr_alm_int;
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wire clk_gthr_lol_int;
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/*
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* AirMax I/O
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*/
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wire amh_right_mdc_int;
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wire amh_right_mdio_i_int;
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wire amh_right_mdio_o_int;
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wire amh_right_mdio_t_int;
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wire amh_left_mdc_int;
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wire amh_left_mdio_i_int;
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wire amh_left_mdio_o_int;
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wire amh_left_mdio_t_int;
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/*
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* 10G Ethernet
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*/
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wire [63:0] eth_r0_txd;
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wire [7:0] eth_r0_txc;
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wire [63:0] eth_r0_rxd;
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wire [7:0] eth_r0_rxc;
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wire [63:0] eth_r1_txd;
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wire [7:0] eth_r1_txc;
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wire [63:0] eth_r1_rxd;
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wire [7:0] eth_r1_rxc;
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wire [63:0] eth_r2_txd;
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wire [7:0] eth_r2_txc;
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wire [63:0] eth_r2_rxd;
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wire [7:0] eth_r2_rxc;
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wire [63:0] eth_r3_txd;
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wire [7:0] eth_r3_txc;
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wire [63:0] eth_r3_rxd;
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wire [7:0] eth_r3_rxc;
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wire [63:0] eth_r4_txd;
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wire [7:0] eth_r4_txc;
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wire [63:0] eth_r4_rxd;
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wire [7:0] eth_r4_rxc;
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wire [63:0] eth_r5_txd;
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wire [7:0] eth_r5_txc;
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wire [63:0] eth_r5_rxd;
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wire [7:0] eth_r5_rxc;
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wire [63:0] eth_r6_txd;
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wire [7:0] eth_r6_txc;
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wire [63:0] eth_r6_rxd;
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wire [7:0] eth_r6_rxc;
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wire [63:0] eth_r7_txd;
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wire [7:0] eth_r7_txc;
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wire [63:0] eth_r7_rxd;
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wire [7:0] eth_r7_rxc;
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wire [63:0] eth_r8_txd;
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wire [7:0] eth_r8_txc;
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wire [63:0] eth_r8_rxd;
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wire [7:0] eth_r8_rxc;
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wire [63:0] eth_r9_txd;
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wire [7:0] eth_r9_txc;
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wire [63:0] eth_r9_rxd;
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wire [7:0] eth_r9_rxc;
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wire [63:0] eth_r10_txd;
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wire [7:0] eth_r10_txc;
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wire [63:0] eth_r10_rxd;
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wire [7:0] eth_r10_rxc;
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wire [63:0] eth_r11_txd;
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wire [7:0] eth_r11_txc;
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wire [63:0] eth_r11_rxd;
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wire [7:0] eth_r11_rxc;
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wire [63:0] eth_l0_txd;
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wire [7:0] eth_l0_txc;
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wire [63:0] eth_l0_rxd;
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wire [7:0] eth_l0_rxc;
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wire [63:0] eth_l1_txd;
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wire [7:0] eth_l1_txc;
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wire [63:0] eth_l1_rxd;
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wire [7:0] eth_l1_rxc;
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wire [63:0] eth_l2_txd;
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wire [7:0] eth_l2_txc;
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wire [63:0] eth_l2_rxd;
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wire [7:0] eth_l2_rxc;
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wire [63:0] eth_l3_txd;
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wire [7:0] eth_l3_txc;
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wire [63:0] eth_l3_rxd;
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wire [7:0] eth_l3_rxc;
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wire [63:0] eth_l4_txd;
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wire [7:0] eth_l4_txc;
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wire [63:0] eth_l4_rxd;
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wire [7:0] eth_l4_rxc;
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wire [63:0] eth_l5_txd;
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wire [7:0] eth_l5_txc;
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wire [63:0] eth_l5_rxd;
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wire [7:0] eth_l5_rxc;
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wire [63:0] eth_l6_txd;
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wire [7:0] eth_l6_txc;
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wire [63:0] eth_l6_rxd;
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wire [7:0] eth_l6_rxc;
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wire [63:0] eth_l7_txd;
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wire [7:0] eth_l7_txc;
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wire [63:0] eth_l7_rxd;
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wire [7:0] eth_l7_rxc;
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wire [63:0] eth_l8_txd;
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wire [7:0] eth_l8_txc;
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wire [63:0] eth_l8_rxd;
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wire [7:0] eth_l8_rxc;
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wire [63:0] eth_l9_txd;
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wire [7:0] eth_l9_txc;
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wire [63:0] eth_l9_rxd;
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wire [7:0] eth_l9_rxc;
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wire [63:0] eth_l10_txd;
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wire [7:0] eth_l10_txc;
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wire [63:0] eth_l10_rxd;
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wire [7:0] eth_l10_rxc;
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wire [63:0] eth_l11_txd;
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wire [7:0] eth_l11_txc;
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wire [63:0] eth_l11_rxd;
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wire [7:0] eth_l11_rxc;
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// Clock buffering for 50 MHz sys_clk
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IBUFG
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sys_clk_ibufg_inst (
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.I(sys_clk),
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.O(sys_clk_ibufg)
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);
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BUFG
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sys_clk_bufg_inst (
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.I(sys_clk_ibufg),
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.O(sys_clk_int)
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);
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// 156.25 MHz clock from GTH
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wire txclk156;
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BUFG
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clk156_bufg_inst (
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.I(txclk156),
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.O(clk_156mhz)
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);
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// Synchronize reset signal
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sync_reset #(
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.N(6)
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)
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sync_reset_inst (
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.clk(sys_clk_int),
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.rst(~reset_n),
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.out(sys_rst)
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);
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sync_signal #(
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.WIDTH(4),
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.N(2)
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)
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sync_signal_50mhz_inst (
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.clk(sys_clk_int),
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.in({clk_gthl_alm,
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clk_gthl_lol,
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clk_gthr_alm,
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clk_gthr_lol}),
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.out({clk_gthl_alm_int,
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clk_gthl_lol_int,
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clk_gthr_alm_int,
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clk_gthr_lol_int})
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);
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sync_signal #(
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.WIDTH(4),
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.N(2)
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)
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sync_signal_156mhz_inst (
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.clk(clk_156mhz),
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.in({uart_suspend,
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uart_dtr,
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uart_txd,
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uart_rts}),
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.out({uart_suspend_int,
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uart_dtr_int,
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uart_txd_int,
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uart_rts_int})
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);
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// Debounce switch inputs
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debounce_switch #(
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.WIDTH(6),
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.N(4),
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.RATE(50000)
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)
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debounce_switch_inst (
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.clk(sys_clk_int),
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.rst(sys_rst),
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.in({sw, jp}),
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.out({sw_int, jp_int})
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);
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// pass through outputs
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assign led = led_int;
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assign uart_rst = uart_rst_int;
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assign uart_ri = uart_ri_int;
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assign uart_dcd = uart_dcd_int;
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assign uart_dsr = uart_dsr_int;
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assign uart_rxd = uart_rxd_int;
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assign uart_cts = uart_cts_int;
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// clock mux I2C
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assign clk_gth_scl_i = clk_gth_scl;
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assign clk_gth_scl = clk_gth_scl_t ? 1'bz : clk_gth_scl_o;
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assign clk_gth_sda_i = clk_gth_sda;
|
|
assign clk_gth_sda = clk_gth_sda_t ? 1'bz : clk_gth_sda_o;
|
|
|
|
assign clk_gth_rst_n = ~sys_rst;
|
|
|
|
wire [6:0] clk_gth_i2c_cmd_address;
|
|
wire clk_gth_i2c_cmd_start;
|
|
wire clk_gth_i2c_cmd_read;
|
|
wire clk_gth_i2c_cmd_write;
|
|
wire clk_gth_i2c_cmd_write_multiple;
|
|
wire clk_gth_i2c_cmd_stop;
|
|
wire clk_gth_i2c_cmd_valid;
|
|
wire clk_gth_i2c_cmd_ready;
|
|
|
|
wire [7:0] clk_gth_i2c_data;
|
|
wire clk_gth_i2c_data_valid;
|
|
wire clk_gth_i2c_data_ready;
|
|
wire clk_gth_i2c_data_last;
|
|
|
|
gth_i2c_init
|
|
clk_gth_i2c_init (
|
|
.clk(sys_clk_int),
|
|
.rst(sys_rst),
|
|
.cmd_address(clk_gth_i2c_cmd_address),
|
|
.cmd_start(clk_gth_i2c_cmd_start),
|
|
.cmd_read(clk_gth_i2c_cmd_read),
|
|
.cmd_write(clk_gth_i2c_cmd_write),
|
|
.cmd_write_multiple(clk_gth_i2c_cmd_write_multiple),
|
|
.cmd_stop(clk_gth_i2c_cmd_stop),
|
|
.cmd_valid(clk_gth_i2c_cmd_valid),
|
|
.cmd_ready(clk_gth_i2c_cmd_ready),
|
|
.data_out(clk_gth_i2c_data),
|
|
.data_out_valid(clk_gth_i2c_data_valid),
|
|
.data_out_ready(clk_gth_i2c_data_ready),
|
|
.data_out_last(clk_gth_i2c_data_last),
|
|
.busy(),
|
|
.start(1)
|
|
);
|
|
|
|
i2c_master
|
|
clk_gth_i2c_master (
|
|
.clk(sys_clk_int),
|
|
.rst(sys_rst),
|
|
.cmd_address(clk_gth_i2c_cmd_address),
|
|
.cmd_start(clk_gth_i2c_cmd_start),
|
|
.cmd_read(clk_gth_i2c_cmd_read),
|
|
.cmd_write(clk_gth_i2c_cmd_write),
|
|
.cmd_write_multiple(clk_gth_i2c_cmd_write_multiple),
|
|
.cmd_stop(clk_gth_i2c_cmd_stop),
|
|
.cmd_valid(clk_gth_i2c_cmd_valid),
|
|
.cmd_ready(clk_gth_i2c_cmd_ready),
|
|
.data_in(clk_gth_i2c_data),
|
|
.data_in_valid(clk_gth_i2c_data_valid),
|
|
.data_in_ready(clk_gth_i2c_data_ready),
|
|
.data_in_last(clk_gth_i2c_data_last),
|
|
.data_out(),
|
|
.data_out_valid(),
|
|
.data_out_ready(1),
|
|
.data_out_last(),
|
|
.scl_i(clk_gth_scl_i),
|
|
.scl_o(clk_gth_scl_o),
|
|
.scl_t(clk_gth_scl_t),
|
|
.sda_i(clk_gth_sda_i),
|
|
.sda_o(clk_gth_sda_o),
|
|
.sda_t(clk_gth_sda_t),
|
|
.busy(),
|
|
.bus_control(),
|
|
.bus_active(),
|
|
.missed_ack(),
|
|
.prescale(312),
|
|
.stop_on_idle(1)
|
|
);
|
|
|
|
// reset logic
|
|
wire gth_reset;
|
|
|
|
wire gth_reset_done_A;
|
|
wire gth_reset_done_B;
|
|
wire gth_reset_done_C;
|
|
wire gth_reset_done_D;
|
|
wire gth_reset_done_E;
|
|
wire gth_reset_done_F;
|
|
|
|
wire gth_reset_done = gth_reset_done_A & gth_reset_done_B & gth_reset_done_C & gth_reset_done_D & gth_reset_done_E & gth_reset_done_F;
|
|
|
|
wire clk_gth_ready = ~clk_gthl_lol_int & ~clk_gthr_lol_int;
|
|
|
|
sync_reset #(
|
|
.N(6)
|
|
)
|
|
sync_reset_gth_inst (
|
|
.clk(sys_clk_int),
|
|
.rst(sys_rst | ~clk_gth_ready),
|
|
.out(gth_reset)
|
|
);
|
|
|
|
sync_reset #(
|
|
.N(6)
|
|
)
|
|
sync_reset_156mhz_inst (
|
|
.clk(clk_156mhz),
|
|
.rst(gth_reset | ~gth_reset_done),
|
|
.out(rst_156mhz)
|
|
);
|
|
|
|
assign amh_right_phy_rst_n = ~rst_156mhz;
|
|
assign amh_left_phy_rst_n = ~rst_156mhz;
|
|
|
|
// AirMax I/O
|
|
|
|
assign amh_right_mdc = amh_right_mdc_int;
|
|
|
|
assign amh_right_mdio_i_int = amh_right_mdio;
|
|
assign amh_right_mdio = amh_right_mdio_t_int ? 1'bz : amh_right_mdio_o_int;
|
|
|
|
assign amh_left_mdc = amh_left_mdc_int;
|
|
|
|
assign amh_left_mdio_i_int = amh_left_mdio;
|
|
assign amh_left_mdio = amh_left_mdio_t_int ? 1'bz : amh_left_mdio_o_int;
|
|
|
|
// 10G Ethernet PCS/PMA
|
|
|
|
// Quad A X0Y0
|
|
eth_gth_phy_quad
|
|
eth_gth_phy_quad_A_inst (
|
|
/*
|
|
* Clock and reset
|
|
*/
|
|
.clk156(clk_156mhz),
|
|
.rst156(rst_156mhz),
|
|
.dclk(sys_clk_int),
|
|
.dclk_reset(sys_rst),
|
|
.txclk156(txclk156), // pickoff one transmit clock for 156.25 MHz core clock
|
|
|
|
.gth_reset(gth_reset),
|
|
.gth_reset_done(gth_reset_done_A),
|
|
|
|
/*
|
|
* Transciever pins
|
|
*/
|
|
.refclk_p(gth_quad_A_refclk_p),
|
|
.refclk_n(gth_quad_A_refclk_n),
|
|
.txn_0(gth_quad_A_txn_0),
|
|
.txp_0(gth_quad_A_txp_0),
|
|
.rxn_0(gth_quad_A_rxn_0),
|
|
.rxp_0(gth_quad_A_rxp_0),
|
|
.txn_1(gth_quad_A_txn_1),
|
|
.txp_1(gth_quad_A_txp_1),
|
|
.rxn_1(gth_quad_A_rxn_1),
|
|
.rxp_1(gth_quad_A_rxp_1),
|
|
.txn_2(gth_quad_A_txn_2),
|
|
.txp_2(gth_quad_A_txp_2),
|
|
.rxn_2(gth_quad_A_rxn_2),
|
|
.rxp_2(gth_quad_A_rxp_2),
|
|
.txn_3(gth_quad_A_txn_3),
|
|
.txp_3(gth_quad_A_txp_3),
|
|
.rxn_3(gth_quad_A_rxn_3),
|
|
.rxp_3(gth_quad_A_rxp_3),
|
|
|
|
/*
|
|
* XGMII interfaces
|
|
*/
|
|
.xgmii_txd_0(eth_r0_txd),
|
|
.xgmii_txc_0(eth_r0_txc),
|
|
.xgmii_rxd_0(eth_r0_rxd),
|
|
.xgmii_rxc_0(eth_r0_rxc),
|
|
.xgmii_txd_1(eth_r2_txd),
|
|
.xgmii_txc_1(eth_r2_txc),
|
|
.xgmii_rxd_1(eth_r2_rxd),
|
|
.xgmii_rxc_1(eth_r2_rxc),
|
|
.xgmii_txd_2(eth_r4_txd),
|
|
.xgmii_txc_2(eth_r4_txc),
|
|
.xgmii_rxd_2(eth_r4_rxd),
|
|
.xgmii_rxc_2(eth_r4_rxc),
|
|
.xgmii_txd_3(eth_r6_txd),
|
|
.xgmii_txc_3(eth_r6_txc),
|
|
.xgmii_rxd_3(eth_r6_rxd),
|
|
.xgmii_rxc_3(eth_r6_rxc),
|
|
|
|
/*
|
|
* Control
|
|
*/
|
|
.tx_powerdown_0(1'b0),
|
|
.rx_powerdown_0(1'b0),
|
|
.tx_powerdown_1(1'b0),
|
|
.rx_powerdown_1(1'b0),
|
|
.tx_powerdown_2(1'b0),
|
|
.rx_powerdown_2(1'b0),
|
|
.tx_powerdown_3(1'b0),
|
|
.rx_powerdown_3(1'b0)
|
|
);
|
|
|
|
// Quad B X0Y1
|
|
eth_gth_phy_quad
|
|
eth_gth_phy_quad_B_inst (
|
|
/*
|
|
* Clock and reset
|
|
*/
|
|
.clk156(clk_156mhz),
|
|
.rst156(rst_156mhz),
|
|
.dclk(sys_clk_int),
|
|
.dclk_reset(sys_rst),
|
|
.txclk156(),
|
|
|
|
.gth_reset(gth_reset),
|
|
.gth_reset_done(gth_reset_done_B),
|
|
|
|
/*
|
|
* Transciever pins
|
|
*/
|
|
.refclk_p(gth_quad_B_refclk_p),
|
|
.refclk_n(gth_quad_B_refclk_n),
|
|
.txn_0(gth_quad_B_txn_0),
|
|
.txp_0(gth_quad_B_txp_0),
|
|
.rxn_0(gth_quad_B_rxn_0),
|
|
.rxp_0(gth_quad_B_rxp_0),
|
|
.txn_1(gth_quad_B_txn_1),
|
|
.txp_1(gth_quad_B_txp_1),
|
|
.rxn_1(gth_quad_B_rxn_1),
|
|
.rxp_1(gth_quad_B_rxp_1),
|
|
.txn_2(gth_quad_B_txn_2),
|
|
.txp_2(gth_quad_B_txp_2),
|
|
.rxn_2(gth_quad_B_rxn_2),
|
|
.rxp_2(gth_quad_B_rxp_2),
|
|
.txn_3(gth_quad_B_txn_3),
|
|
.txp_3(gth_quad_B_txp_3),
|
|
.rxn_3(gth_quad_B_rxn_3),
|
|
.rxp_3(gth_quad_B_rxp_3),
|
|
|
|
/*
|
|
* XGMII interfaces
|
|
*/
|
|
.xgmii_txd_0(eth_r3_txd),
|
|
.xgmii_txc_0(eth_r3_txc),
|
|
.xgmii_rxd_0(eth_r3_rxd),
|
|
.xgmii_rxc_0(eth_r3_rxc),
|
|
.xgmii_txd_1(eth_r5_txd),
|
|
.xgmii_txc_1(eth_r5_txc),
|
|
.xgmii_rxd_1(eth_r5_rxd),
|
|
.xgmii_rxc_1(eth_r5_rxc),
|
|
.xgmii_txd_2(eth_r1_txd),
|
|
.xgmii_txc_2(eth_r1_txc),
|
|
.xgmii_rxd_2(eth_r1_rxd),
|
|
.xgmii_rxc_2(eth_r1_rxc),
|
|
.xgmii_txd_3(eth_r7_txd),
|
|
.xgmii_txc_3(eth_r7_txc),
|
|
.xgmii_rxd_3(eth_r7_rxd),
|
|
.xgmii_rxc_3(eth_r7_rxc),
|
|
|
|
/*
|
|
* Control
|
|
*/
|
|
.tx_powerdown_0(1'b0),
|
|
.rx_powerdown_0(1'b0),
|
|
.tx_powerdown_1(1'b0),
|
|
.rx_powerdown_1(1'b0),
|
|
.tx_powerdown_2(1'b0),
|
|
.rx_powerdown_2(1'b0),
|
|
.tx_powerdown_3(1'b0),
|
|
.rx_powerdown_3(1'b0)
|
|
);
|
|
|
|
// Quad C X0Y2
|
|
eth_gth_phy_quad
|
|
eth_gth_phy_quad_C_inst (
|
|
/*
|
|
* Clock and reset
|
|
*/
|
|
.clk156(clk_156mhz),
|
|
.rst156(rst_156mhz),
|
|
.dclk(sys_clk_int),
|
|
.dclk_reset(sys_rst),
|
|
.txclk156(),
|
|
|
|
.gth_reset(gth_reset),
|
|
.gth_reset_done(gth_reset_done_C),
|
|
|
|
/*
|
|
* Transciever pins
|
|
*/
|
|
.refclk_p(gth_quad_C_refclk_p),
|
|
.refclk_n(gth_quad_C_refclk_n),
|
|
.txn_0(gth_quad_C_txn_0),
|
|
.txp_0(gth_quad_C_txp_0),
|
|
.rxn_0(gth_quad_C_rxn_0),
|
|
.rxp_0(gth_quad_C_rxp_0),
|
|
.txn_1(gth_quad_C_txn_1),
|
|
.txp_1(gth_quad_C_txp_1),
|
|
.rxn_1(gth_quad_C_rxn_1),
|
|
.rxp_1(gth_quad_C_rxp_1),
|
|
.txn_2(gth_quad_C_txn_2),
|
|
.txp_2(gth_quad_C_txp_2),
|
|
.rxn_2(gth_quad_C_rxn_2),
|
|
.rxp_2(gth_quad_C_rxp_2),
|
|
.txn_3(gth_quad_C_txn_3),
|
|
.txp_3(gth_quad_C_txp_3),
|
|
.rxn_3(gth_quad_C_rxn_3),
|
|
.rxp_3(gth_quad_C_rxp_3),
|
|
|
|
/*
|
|
* XGMII interfaces
|
|
*/
|
|
.xgmii_txd_0(eth_r8_txd),
|
|
.xgmii_txc_0(eth_r8_txc),
|
|
.xgmii_rxd_0(eth_r8_rxd),
|
|
.xgmii_rxc_0(eth_r8_rxc),
|
|
.xgmii_txd_1(eth_r9_txd),
|
|
.xgmii_txc_1(eth_r9_txc),
|
|
.xgmii_rxd_1(eth_r9_rxd),
|
|
.xgmii_rxc_1(eth_r9_rxc),
|
|
.xgmii_txd_2(eth_r11_txd),
|
|
.xgmii_txc_2(eth_r11_txc),
|
|
.xgmii_rxd_2(eth_r11_rxd),
|
|
.xgmii_rxc_2(eth_r11_rxc),
|
|
.xgmii_txd_3(eth_r10_txd),
|
|
.xgmii_txc_3(eth_r10_txc),
|
|
.xgmii_rxd_3(eth_r10_rxd),
|
|
.xgmii_rxc_3(eth_r10_rxc),
|
|
|
|
/*
|
|
* Control
|
|
*/
|
|
.tx_powerdown_0(1'b0),
|
|
.rx_powerdown_0(1'b0),
|
|
.tx_powerdown_1(1'b0),
|
|
.rx_powerdown_1(1'b0),
|
|
.tx_powerdown_2(1'b0),
|
|
.rx_powerdown_2(1'b0),
|
|
.tx_powerdown_3(1'b0),
|
|
.rx_powerdown_3(1'b0)
|
|
);
|
|
|
|
// Quad D X1Y0
|
|
eth_gth_phy_quad
|
|
eth_gth_phy_quad_D_inst (
|
|
/*
|
|
* Clock and reset
|
|
*/
|
|
.clk156(clk_156mhz),
|
|
.rst156(rst_156mhz),
|
|
.dclk(sys_clk_int),
|
|
.dclk_reset(sys_rst),
|
|
.txclk156(),
|
|
|
|
.gth_reset(gth_reset),
|
|
.gth_reset_done(gth_reset_done_D),
|
|
|
|
/*
|
|
* Transciever pins
|
|
*/
|
|
.refclk_p(gth_quad_D_refclk_p),
|
|
.refclk_n(gth_quad_D_refclk_n),
|
|
.txn_0(gth_quad_D_txn_0),
|
|
.txp_0(gth_quad_D_txp_0),
|
|
.rxn_0(gth_quad_D_rxn_0),
|
|
.rxp_0(gth_quad_D_rxp_0),
|
|
.txn_1(gth_quad_D_txn_1),
|
|
.txp_1(gth_quad_D_txp_1),
|
|
.rxn_1(gth_quad_D_rxn_1),
|
|
.rxp_1(gth_quad_D_rxp_1),
|
|
.txn_2(gth_quad_D_txn_2),
|
|
.txp_2(gth_quad_D_txp_2),
|
|
.rxn_2(gth_quad_D_rxn_2),
|
|
.rxp_2(gth_quad_D_rxp_2),
|
|
.txn_3(gth_quad_D_txn_3),
|
|
.txp_3(gth_quad_D_txp_3),
|
|
.rxn_3(gth_quad_D_rxn_3),
|
|
.rxp_3(gth_quad_D_rxp_3),
|
|
|
|
/*
|
|
* XGMII interfaces
|
|
*/
|
|
.xgmii_txd_0(eth_l0_txd),
|
|
.xgmii_txc_0(eth_l0_txc),
|
|
.xgmii_rxd_0(eth_l0_rxd),
|
|
.xgmii_rxc_0(eth_l0_rxc),
|
|
.xgmii_txd_1(eth_l2_txd),
|
|
.xgmii_txc_1(eth_l2_txc),
|
|
.xgmii_rxd_1(eth_l2_rxd),
|
|
.xgmii_rxc_1(eth_l2_rxc),
|
|
.xgmii_txd_2(eth_l4_txd),
|
|
.xgmii_txc_2(eth_l4_txc),
|
|
.xgmii_rxd_2(eth_l4_rxd),
|
|
.xgmii_rxc_2(eth_l4_rxc),
|
|
.xgmii_txd_3(eth_l6_txd),
|
|
.xgmii_txc_3(eth_l6_txc),
|
|
.xgmii_rxd_3(eth_l6_rxd),
|
|
.xgmii_rxc_3(eth_l6_rxc),
|
|
|
|
/*
|
|
* Control
|
|
*/
|
|
.tx_powerdown_0(1'b0),
|
|
.rx_powerdown_0(1'b0),
|
|
.tx_powerdown_1(1'b0),
|
|
.rx_powerdown_1(1'b0),
|
|
.tx_powerdown_2(1'b0),
|
|
.rx_powerdown_2(1'b0),
|
|
.tx_powerdown_3(1'b0),
|
|
.rx_powerdown_3(1'b0)
|
|
);
|
|
|
|
// Quad E X1Y1
|
|
eth_gth_phy_quad
|
|
eth_gth_phy_quad_E_inst (
|
|
/*
|
|
* Clock and reset
|
|
*/
|
|
.clk156(clk_156mhz),
|
|
.rst156(rst_156mhz),
|
|
.dclk(sys_clk_int),
|
|
.dclk_reset(sys_rst),
|
|
.txclk156(),
|
|
|
|
.gth_reset(gth_reset),
|
|
.gth_reset_done(gth_reset_done_E),
|
|
|
|
/*
|
|
* Transciever pins
|
|
*/
|
|
.refclk_p(gth_quad_E_refclk_p),
|
|
.refclk_n(gth_quad_E_refclk_n),
|
|
.txn_0(gth_quad_E_txn_0),
|
|
.txp_0(gth_quad_E_txp_0),
|
|
.rxn_0(gth_quad_E_rxn_0),
|
|
.rxp_0(gth_quad_E_rxp_0),
|
|
.txn_1(gth_quad_E_txn_1),
|
|
.txp_1(gth_quad_E_txp_1),
|
|
.rxn_1(gth_quad_E_rxn_1),
|
|
.rxp_1(gth_quad_E_rxp_1),
|
|
.txn_2(gth_quad_E_txn_2),
|
|
.txp_2(gth_quad_E_txp_2),
|
|
.rxn_2(gth_quad_E_rxn_2),
|
|
.rxp_2(gth_quad_E_rxp_2),
|
|
.txn_3(gth_quad_E_txn_3),
|
|
.txp_3(gth_quad_E_txp_3),
|
|
.rxn_3(gth_quad_E_rxn_3),
|
|
.rxp_3(gth_quad_E_rxp_3),
|
|
|
|
/*
|
|
* XGMII interfaces
|
|
*/
|
|
.xgmii_txd_0(eth_l3_txd),
|
|
.xgmii_txc_0(eth_l3_txc),
|
|
.xgmii_rxd_0(eth_l3_rxd),
|
|
.xgmii_rxc_0(eth_l3_rxc),
|
|
.xgmii_txd_1(eth_l5_txd),
|
|
.xgmii_txc_1(eth_l5_txc),
|
|
.xgmii_rxd_1(eth_l5_rxd),
|
|
.xgmii_rxc_1(eth_l5_rxc),
|
|
.xgmii_txd_2(eth_l1_txd),
|
|
.xgmii_txc_2(eth_l1_txc),
|
|
.xgmii_rxd_2(eth_l1_rxd),
|
|
.xgmii_rxc_2(eth_l1_rxc),
|
|
.xgmii_txd_3(eth_l7_txd),
|
|
.xgmii_txc_3(eth_l7_txc),
|
|
.xgmii_rxd_3(eth_l7_rxd),
|
|
.xgmii_rxc_3(eth_l7_rxc),
|
|
|
|
/*
|
|
* Control
|
|
*/
|
|
.tx_powerdown_0(1'b0),
|
|
.rx_powerdown_0(1'b0),
|
|
.tx_powerdown_1(1'b0),
|
|
.rx_powerdown_1(1'b0),
|
|
.tx_powerdown_2(1'b0),
|
|
.rx_powerdown_2(1'b0),
|
|
.tx_powerdown_3(1'b0),
|
|
.rx_powerdown_3(1'b0)
|
|
);
|
|
|
|
// Quad F X1Y2
|
|
eth_gth_phy_quad
|
|
eth_gth_phy_quad_F_inst (
|
|
/*
|
|
* Clock and reset
|
|
*/
|
|
.clk156(clk_156mhz),
|
|
.rst156(rst_156mhz),
|
|
.dclk(sys_clk_int),
|
|
.dclk_reset(sys_rst),
|
|
.txclk156(),
|
|
|
|
.gth_reset(gth_reset),
|
|
.gth_reset_done(gth_reset_done_F),
|
|
|
|
/*
|
|
* Transciever pins
|
|
*/
|
|
.refclk_p(gth_quad_F_refclk_p),
|
|
.refclk_n(gth_quad_F_refclk_n),
|
|
.txn_0(gth_quad_F_txn_0),
|
|
.txp_0(gth_quad_F_txp_0),
|
|
.rxn_0(gth_quad_F_rxn_0),
|
|
.rxp_0(gth_quad_F_rxp_0),
|
|
.txn_1(gth_quad_F_txn_1),
|
|
.txp_1(gth_quad_F_txp_1),
|
|
.rxn_1(gth_quad_F_rxn_1),
|
|
.rxp_1(gth_quad_F_rxp_1),
|
|
.txn_2(gth_quad_F_txn_2),
|
|
.txp_2(gth_quad_F_txp_2),
|
|
.rxn_2(gth_quad_F_rxn_2),
|
|
.rxp_2(gth_quad_F_rxp_2),
|
|
.txn_3(gth_quad_F_txn_3),
|
|
.txp_3(gth_quad_F_txp_3),
|
|
.rxn_3(gth_quad_F_rxn_3),
|
|
.rxp_3(gth_quad_F_rxp_3),
|
|
|
|
/*
|
|
* XGMII interfaces
|
|
*/
|
|
.xgmii_txd_0(eth_l8_txd),
|
|
.xgmii_txc_0(eth_l8_txc),
|
|
.xgmii_rxd_0(eth_l8_rxd),
|
|
.xgmii_rxc_0(eth_l8_rxc),
|
|
.xgmii_txd_1(eth_l9_txd),
|
|
.xgmii_txc_1(eth_l9_txc),
|
|
.xgmii_rxd_1(eth_l9_rxd),
|
|
.xgmii_rxc_1(eth_l9_rxc),
|
|
.xgmii_txd_2(eth_l11_txd),
|
|
.xgmii_txc_2(eth_l11_txc),
|
|
.xgmii_rxd_2(eth_l11_rxd),
|
|
.xgmii_rxc_2(eth_l11_rxc),
|
|
.xgmii_txd_3(eth_l10_txd),
|
|
.xgmii_txc_3(eth_l10_txc),
|
|
.xgmii_rxd_3(eth_l10_rxd),
|
|
.xgmii_rxc_3(eth_l10_rxc),
|
|
|
|
/*
|
|
* Control
|
|
*/
|
|
.tx_powerdown_0(1'b0),
|
|
.rx_powerdown_0(1'b0),
|
|
.tx_powerdown_1(1'b0),
|
|
.rx_powerdown_1(1'b0),
|
|
.tx_powerdown_2(1'b0),
|
|
.rx_powerdown_2(1'b0),
|
|
.tx_powerdown_3(1'b0),
|
|
.rx_powerdown_3(1'b0)
|
|
);
|
|
|
|
|
|
fpga_core
|
|
core_inst (
|
|
/*
|
|
* Clock: 156.25 MHz
|
|
* Synchronous reset
|
|
*/
|
|
.clk(clk_156mhz),
|
|
.rst(rst_156mhz),
|
|
/*
|
|
* GPIO
|
|
*/
|
|
.sw(sw_int),
|
|
.jp(jp_int),
|
|
.led(led_int),
|
|
/*
|
|
* Silicon Labs CP2102 USB UART
|
|
*/
|
|
.uart_rst(uart_rst_int),
|
|
.uart_suspend(uart_suspend_int),
|
|
.uart_ri(uart_ri_int),
|
|
.uart_dcd(uart_dcd_int),
|
|
.uart_dtr(uart_dtr_int),
|
|
.uart_dsr(uart_dsr_int),
|
|
.uart_txd(uart_txd_int),
|
|
.uart_rxd(uart_rxd_int),
|
|
.uart_rts(uart_rts_int),
|
|
.uart_cts(uart_cts_int),
|
|
/*
|
|
* AirMax I/O
|
|
*/
|
|
.amh_right_mdc(amh_right_mdc_int),
|
|
.amh_right_mdio_i(amh_right_mdio_i_int),
|
|
.amh_right_mdio_o(amh_right_mdio_o_int),
|
|
.amh_right_mdio_t(amh_right_mdio_t_int),
|
|
.amh_left_mdc(amh_left_mdc_int),
|
|
.amh_left_mdio_i(amh_left_mdio_i_int),
|
|
.amh_left_mdio_o(amh_left_mdio_o_int),
|
|
.amh_left_mdio_t(amh_left_mdio_t_int),
|
|
/*
|
|
* 10G Ethernet XGMII
|
|
*/
|
|
.eth_r0_txd(eth_r0_txd),
|
|
.eth_r0_txc(eth_r0_txc),
|
|
.eth_r0_rxd(eth_r0_rxd),
|
|
.eth_r0_rxc(eth_r0_rxc),
|
|
.eth_r1_txd(eth_r1_txd),
|
|
.eth_r1_txc(eth_r1_txc),
|
|
.eth_r1_rxd(eth_r1_rxd),
|
|
.eth_r1_rxc(eth_r1_rxc),
|
|
.eth_r2_txd(eth_r2_txd),
|
|
.eth_r2_txc(eth_r2_txc),
|
|
.eth_r2_rxd(eth_r2_rxd),
|
|
.eth_r2_rxc(eth_r2_rxc),
|
|
.eth_r3_txd(eth_r3_txd),
|
|
.eth_r3_txc(eth_r3_txc),
|
|
.eth_r3_rxd(eth_r3_rxd),
|
|
.eth_r3_rxc(eth_r3_rxc),
|
|
.eth_r4_txd(eth_r4_txd),
|
|
.eth_r4_txc(eth_r4_txc),
|
|
.eth_r4_rxd(eth_r4_rxd),
|
|
.eth_r4_rxc(eth_r4_rxc),
|
|
.eth_r5_txd(eth_r5_txd),
|
|
.eth_r5_txc(eth_r5_txc),
|
|
.eth_r5_rxd(eth_r5_rxd),
|
|
.eth_r5_rxc(eth_r5_rxc),
|
|
.eth_r6_txd(eth_r6_txd),
|
|
.eth_r6_txc(eth_r6_txc),
|
|
.eth_r6_rxd(eth_r6_rxd),
|
|
.eth_r6_rxc(eth_r6_rxc),
|
|
.eth_r7_txd(eth_r7_txd),
|
|
.eth_r7_txc(eth_r7_txc),
|
|
.eth_r7_rxd(eth_r7_rxd),
|
|
.eth_r7_rxc(eth_r7_rxc),
|
|
.eth_r8_txd(eth_r8_txd),
|
|
.eth_r8_txc(eth_r8_txc),
|
|
.eth_r8_rxd(eth_r8_rxd),
|
|
.eth_r8_rxc(eth_r8_rxc),
|
|
.eth_r9_txd(eth_r9_txd),
|
|
.eth_r9_txc(eth_r9_txc),
|
|
.eth_r9_rxd(eth_r9_rxd),
|
|
.eth_r9_rxc(eth_r9_rxc),
|
|
.eth_r10_txd(eth_r10_txd),
|
|
.eth_r10_txc(eth_r10_txc),
|
|
.eth_r10_rxd(eth_r10_rxd),
|
|
.eth_r10_rxc(eth_r10_rxc),
|
|
.eth_r11_txd(eth_r11_txd),
|
|
.eth_r11_txc(eth_r11_txc),
|
|
.eth_r11_rxd(eth_r11_rxd),
|
|
.eth_r11_rxc(eth_r11_rxc),
|
|
.eth_l0_txd(eth_l0_txd),
|
|
.eth_l0_txc(eth_l0_txc),
|
|
.eth_l0_rxd(eth_l0_rxd),
|
|
.eth_l0_rxc(eth_l0_rxc),
|
|
.eth_l1_txd(eth_l1_txd),
|
|
.eth_l1_txc(eth_l1_txc),
|
|
.eth_l1_rxd(eth_l1_rxd),
|
|
.eth_l1_rxc(eth_l1_rxc),
|
|
.eth_l2_txd(eth_l2_txd),
|
|
.eth_l2_txc(eth_l2_txc),
|
|
.eth_l2_rxd(eth_l2_rxd),
|
|
.eth_l2_rxc(eth_l2_rxc),
|
|
.eth_l3_txd(eth_l3_txd),
|
|
.eth_l3_txc(eth_l3_txc),
|
|
.eth_l3_rxd(eth_l3_rxd),
|
|
.eth_l3_rxc(eth_l3_rxc),
|
|
.eth_l4_txd(eth_l4_txd),
|
|
.eth_l4_txc(eth_l4_txc),
|
|
.eth_l4_rxd(eth_l4_rxd),
|
|
.eth_l4_rxc(eth_l4_rxc),
|
|
.eth_l5_txd(eth_l5_txd),
|
|
.eth_l5_txc(eth_l5_txc),
|
|
.eth_l5_rxd(eth_l5_rxd),
|
|
.eth_l5_rxc(eth_l5_rxc),
|
|
.eth_l6_txd(eth_l6_txd),
|
|
.eth_l6_txc(eth_l6_txc),
|
|
.eth_l6_rxd(eth_l6_rxd),
|
|
.eth_l6_rxc(eth_l6_rxc),
|
|
.eth_l7_txd(eth_l7_txd),
|
|
.eth_l7_txc(eth_l7_txc),
|
|
.eth_l7_rxd(eth_l7_rxd),
|
|
.eth_l7_rxc(eth_l7_rxc),
|
|
.eth_l8_txd(eth_l8_txd),
|
|
.eth_l8_txc(eth_l8_txc),
|
|
.eth_l8_rxd(eth_l8_rxd),
|
|
.eth_l8_rxc(eth_l8_rxc),
|
|
.eth_l9_txd(eth_l9_txd),
|
|
.eth_l9_txc(eth_l9_txc),
|
|
.eth_l9_rxd(eth_l9_rxd),
|
|
.eth_l9_rxc(eth_l9_rxc),
|
|
.eth_l10_txd(eth_l10_txd),
|
|
.eth_l10_txc(eth_l10_txc),
|
|
.eth_l10_rxd(eth_l10_rxd),
|
|
.eth_l10_rxc(eth_l10_rxc),
|
|
.eth_l11_txd(eth_l11_txd),
|
|
.eth_l11_txc(eth_l11_txc),
|
|
.eth_l11_rxd(eth_l11_rxd),
|
|
.eth_l11_rxc(eth_l11_rxc)
|
|
);
|
|
|
|
endmodule
|
|
|
|
`resetall
|