Alex Forencich 5b859b08a0 Use false path constraints for status signals that change infrequently ...

Signed-off-by: Alex Forencich <alex@alexforencich.com>

2023-01-17 14:25:30 -08:00

..

cmac_gty_ch_wrapper.tcl

fpga/mqnic/common: Clean up TCL timing constraints and update to handle clocks from OOC IP that are not constrained during synthesis

2022-12-08 18:50:30 -08:00

cmac_gty_wrapper.tcl

fpga/mqnic/common: Clean up TCL timing constraints and update to handle clocks from OOC IP that are not constrained during synthesis

2022-12-08 18:50:30 -08:00

eth_xcvr_phy_10g_gty_wrapper.tcl

fpga/mqnic/common: Clean up TCL timing constraints and update to handle clocks from OOC IP that are not constrained during synthesis

2022-12-08 18:50:30 -08:00

mqnic_port.tcl

Use false path constraints for status signals that change infrequently

2023-01-17 14:25:30 -08:00

mqnic_ptp_clock.tcl

fpga/mqnic/common: Clean up TCL timing constraints and update to handle clocks from OOC IP that are not constrained during synthesis

2022-12-08 18:50:30 -08:00

mqnic_rb_clk_info.tcl

fpga/mqnic/common: Clean up TCL timing constraints and update to handle clocks from OOC IP that are not constrained during synthesis

2022-12-08 18:50:30 -08:00

rb_drp.tcl

fpga/mqnic/common: Clean up TCL timing constraints and update to handle clocks from OOC IP that are not constrained during synthesis

2022-12-08 18:50:30 -08:00

tdma_ber_ch.tcl

fpga/mqnic/common: Clean up TCL timing constraints and update to handle clocks from OOC IP that are not constrained during synthesis

2022-12-08 18:50:30 -08:00