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730 lines
30 KiB
Verilog
730 lines
30 KiB
Verilog
/*
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Copyright (c) 2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* AXI4 Central DMA
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*/
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module axi_cdma #
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(
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parameter AXI_DATA_WIDTH = 32, // width of data bus in bits
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parameter AXI_ADDR_WIDTH = 16, // width of address bus in bits
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parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8),
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parameter AXI_ID_WIDTH = 8,
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parameter AXI_MAX_BURST_LEN = 16,
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parameter LEN_WIDTH = 20,
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parameter TAG_WIDTH = 8,
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parameter ENABLE_UNALIGNED = 0
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI descriptor input
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*/
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input wire [AXI_ADDR_WIDTH-1:0] s_axis_desc_read_addr,
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input wire [AXI_ADDR_WIDTH-1:0] s_axis_desc_write_addr,
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input wire [LEN_WIDTH-1:0] s_axis_desc_len,
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input wire [TAG_WIDTH-1:0] s_axis_desc_tag,
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input wire s_axis_desc_valid,
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output wire s_axis_desc_ready,
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/*
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* AXI descriptor status output
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*/
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output wire [TAG_WIDTH-1:0] m_axis_desc_status_tag,
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output wire m_axis_desc_status_valid,
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/*
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* AXI write master interface
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*/
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output wire [AXI_ID_WIDTH-1:0] m_axi_awid,
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output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
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output wire [7:0] m_axi_awlen,
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output wire [2:0] m_axi_awsize,
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output wire [1:0] m_axi_awburst,
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output wire m_axi_awlock,
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output wire [3:0] m_axi_awcache,
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output wire [2:0] m_axi_awprot,
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output wire m_axi_awvalid,
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input wire m_axi_awready,
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output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata,
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output wire [AXI_STRB_WIDTH-1:0] m_axi_wstrb,
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output wire m_axi_wlast,
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output wire m_axi_wvalid,
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input wire m_axi_wready,
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input wire [AXI_ID_WIDTH-1:0] m_axi_bid,
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input wire [1:0] m_axi_bresp,
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input wire m_axi_bvalid,
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output wire m_axi_bready,
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/*
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* AXI read master interface
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*/
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output wire [AXI_ID_WIDTH-1:0] m_axi_arid,
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output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr,
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output wire [7:0] m_axi_arlen,
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output wire [2:0] m_axi_arsize,
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output wire [1:0] m_axi_arburst,
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output wire m_axi_arlock,
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output wire [3:0] m_axi_arcache,
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output wire [2:0] m_axi_arprot,
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output wire m_axi_arvalid,
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input wire m_axi_arready,
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input wire [AXI_ID_WIDTH-1:0] m_axi_rid,
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input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata,
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input wire [1:0] m_axi_rresp,
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input wire m_axi_rlast,
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input wire m_axi_rvalid,
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output wire m_axi_rready,
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/*
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* Configuration
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*/
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input wire enable
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);
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parameter AXI_WORD_WIDTH = AXI_STRB_WIDTH;
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parameter AXI_WORD_SIZE = AXI_DATA_WIDTH/AXI_WORD_WIDTH;
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parameter AXI_BURST_SIZE = $clog2(AXI_STRB_WIDTH);
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parameter AXI_MAX_BURST_SIZE = AXI_MAX_BURST_LEN << AXI_BURST_SIZE;
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parameter OFFSET_WIDTH = AXI_STRB_WIDTH > 1 ? $clog2(AXI_STRB_WIDTH) : 1;
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parameter OFFSET_MASK = AXI_STRB_WIDTH > 1 ? {OFFSET_WIDTH{1'b1}} : 0;
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parameter ADDR_MASK = {AXI_ADDR_WIDTH{1'b1}} << $clog2(AXI_STRB_WIDTH);
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parameter CYCLE_COUNT_WIDTH = LEN_WIDTH - AXI_BURST_SIZE + 1;
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parameter STATUS_FIFO_ADDR_WIDTH = 5;
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// bus width assertions
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initial begin
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if (AXI_WORD_SIZE * AXI_STRB_WIDTH != AXI_DATA_WIDTH) begin
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$error("Error: AXI data width not evenly divisble");
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$finish;
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end
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if (2**$clog2(AXI_WORD_WIDTH) != AXI_WORD_WIDTH) begin
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$error("Error: AXI word width must be even power of two");
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$finish;
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end
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if (AXI_MAX_BURST_LEN < 1 || AXI_MAX_BURST_LEN > 256) begin
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$error("Error: AXI_MAX_BURST_LEN must be between 1 and 256");
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$finish;
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end
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end
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localparam [1:0]
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READ_STATE_IDLE = 2'd0,
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READ_STATE_START = 2'd1,
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READ_STATE_REQ = 2'd2;
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reg [1:0] read_state_reg = READ_STATE_IDLE, read_state_next;
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localparam [0:0]
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AXI_STATE_IDLE = 1'd0,
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AXI_STATE_WRITE = 1'd1;
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reg [0:0] axi_state_reg = AXI_STATE_IDLE, axi_state_next;
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// datapath control signals
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reg transfer_in_save;
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reg axi_cmd_ready;
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reg status_fifo_we;
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reg [AXI_ADDR_WIDTH-1:0] read_addr_reg = {AXI_ADDR_WIDTH{1'b0}}, read_addr_next;
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reg [AXI_ADDR_WIDTH-1:0] write_addr_reg = {AXI_ADDR_WIDTH{1'b0}}, write_addr_next;
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reg [LEN_WIDTH-1:0] op_word_count_reg = {LEN_WIDTH{1'b0}}, op_word_count_next;
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reg [LEN_WIDTH-1:0] tr_word_count_reg = {LEN_WIDTH{1'b0}}, tr_word_count_next;
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reg [LEN_WIDTH-1:0] axi_word_count_reg = {LEN_WIDTH{1'b0}}, axi_word_count_next;
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reg [AXI_ADDR_WIDTH-1:0] axi_cmd_addr_reg = {AXI_ADDR_WIDTH{1'b0}}, axi_cmd_addr_next;
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reg [OFFSET_WIDTH-1:0] axi_cmd_offset_reg = {OFFSET_WIDTH{1'b0}}, axi_cmd_offset_next;
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reg [OFFSET_WIDTH-1:0] axi_cmd_first_cycle_offset_reg = {OFFSET_WIDTH{1'b0}}, axi_cmd_first_cycle_offset_next;
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reg [OFFSET_WIDTH-1:0] axi_cmd_last_cycle_offset_reg = {OFFSET_WIDTH{1'b0}}, axi_cmd_last_cycle_offset_next;
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reg [CYCLE_COUNT_WIDTH-1:0] axi_cmd_input_cycle_count_reg = {CYCLE_COUNT_WIDTH{1'b0}}, axi_cmd_input_cycle_count_next;
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reg [CYCLE_COUNT_WIDTH-1:0] axi_cmd_output_cycle_count_reg = {CYCLE_COUNT_WIDTH{1'b0}}, axi_cmd_output_cycle_count_next;
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reg axi_cmd_bubble_cycle_reg = 1'b0, axi_cmd_bubble_cycle_next;
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reg axi_cmd_last_transfer_reg = 1'b0, axi_cmd_last_transfer_next;
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reg [TAG_WIDTH-1:0] axi_cmd_tag_reg = {TAG_WIDTH{1'b0}}, axi_cmd_tag_next;
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reg axi_cmd_valid_reg = 1'b0, axi_cmd_valid_next;
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reg [OFFSET_WIDTH-1:0] offset_reg = {OFFSET_WIDTH{1'b0}}, offset_next;
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reg [OFFSET_WIDTH-1:0] first_cycle_offset_reg = {OFFSET_WIDTH{1'b0}}, first_cycle_offset_next;
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reg [OFFSET_WIDTH-1:0] last_cycle_offset_reg = {OFFSET_WIDTH{1'b0}}, last_cycle_offset_next;
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reg [CYCLE_COUNT_WIDTH-1:0] input_cycle_count_reg = {CYCLE_COUNT_WIDTH{1'b0}}, input_cycle_count_next;
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reg [CYCLE_COUNT_WIDTH-1:0] output_cycle_count_reg = {CYCLE_COUNT_WIDTH{1'b0}}, output_cycle_count_next;
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reg input_active_reg = 1'b0, input_active_next;
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reg output_active_reg = 1'b0, output_active_next;
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reg bubble_cycle_reg = 1'b0, bubble_cycle_next;
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reg first_input_cycle_reg = 1'b0, first_input_cycle_next;
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reg first_output_cycle_reg = 1'b0, first_output_cycle_next;
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reg output_last_cycle_reg = 1'b0, output_last_cycle_next;
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reg last_transfer_reg = 1'b0, last_transfer_next;
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reg [TAG_WIDTH-1:0] tag_reg = {TAG_WIDTH{1'b0}}, tag_next;
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reg [STATUS_FIFO_ADDR_WIDTH+1-1:0] status_fifo_wr_ptr_reg = 0, status_fifo_wr_ptr_next;
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reg [STATUS_FIFO_ADDR_WIDTH+1-1:0] status_fifo_rd_ptr_reg = 0, status_fifo_rd_ptr_next;
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reg [TAG_WIDTH-1:0] status_fifo_tag[(2**STATUS_FIFO_ADDR_WIDTH)-1:0];
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reg status_fifo_last[(2**STATUS_FIFO_ADDR_WIDTH)-1:0];
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reg [TAG_WIDTH-1:0] status_fifo_wr_tag;
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reg status_fifo_wr_last;
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reg s_axis_desc_ready_reg = 1'b0, s_axis_desc_ready_next;
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reg [TAG_WIDTH-1:0] m_axis_desc_status_tag_reg = {TAG_WIDTH{1'b0}}, m_axis_desc_status_tag_next;
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reg m_axis_desc_status_valid_reg = 1'b0, m_axis_desc_status_valid_next;
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reg [AXI_ADDR_WIDTH-1:0] m_axi_araddr_reg = {AXI_ADDR_WIDTH{1'b0}}, m_axi_araddr_next;
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reg [7:0] m_axi_arlen_reg = 8'd0, m_axi_arlen_next;
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reg m_axi_arvalid_reg = 1'b0, m_axi_arvalid_next;
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reg m_axi_rready_reg = 1'b0, m_axi_rready_next;
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reg [AXI_ADDR_WIDTH-1:0] m_axi_awaddr_reg = {AXI_ADDR_WIDTH{1'b0}}, m_axi_awaddr_next;
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reg [7:0] m_axi_awlen_reg = 8'd0, m_axi_awlen_next;
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reg m_axi_awvalid_reg = 1'b0, m_axi_awvalid_next;
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reg m_axi_bready_reg = 1'b0, m_axi_bready_next;
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reg [AXI_DATA_WIDTH-1:0] save_axi_rdata_reg = {AXI_DATA_WIDTH{1'b0}};
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wire [AXI_DATA_WIDTH-1:0] shift_axi_rdata = {m_axi_rdata, save_axi_rdata_reg} >> ((AXI_STRB_WIDTH-offset_reg)*AXI_WORD_SIZE);
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// internal datapath
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reg [AXI_DATA_WIDTH-1:0] m_axi_wdata_int;
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reg [AXI_STRB_WIDTH-1:0] m_axi_wstrb_int;
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reg m_axi_wlast_int;
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reg m_axi_wvalid_int;
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reg m_axi_wready_int_reg = 1'b0;
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wire m_axi_wready_int_early;
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assign s_axis_desc_ready = s_axis_desc_ready_reg;
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assign m_axis_desc_status_tag = m_axis_desc_status_tag_reg;
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assign m_axis_desc_status_valid = m_axis_desc_status_valid_reg;
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assign m_axi_arid = {AXI_ID_WIDTH{1'b0}};
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assign m_axi_araddr = m_axi_araddr_reg;
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assign m_axi_arlen = m_axi_arlen_reg;
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assign m_axi_arsize = AXI_BURST_SIZE;
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assign m_axi_arburst = 2'b01;
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assign m_axi_arlock = 1'b0;
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assign m_axi_arcache = 4'b0011;
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assign m_axi_arprot = 3'b010;
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assign m_axi_arvalid = m_axi_arvalid_reg;
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assign m_axi_rready = m_axi_rready_reg;
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assign m_axi_awid = {AXI_ID_WIDTH{1'b0}};
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assign m_axi_awaddr = m_axi_awaddr_reg;
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assign m_axi_awlen = m_axi_awlen_reg;
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assign m_axi_awsize = AXI_BURST_SIZE;
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assign m_axi_awburst = 2'b01;
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assign m_axi_awlock = 1'b0;
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assign m_axi_awcache = 4'b0011;
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assign m_axi_awprot = 3'b010;
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assign m_axi_awvalid = m_axi_awvalid_reg;
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assign m_axi_bready = m_axi_bready_reg;
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wire [AXI_ADDR_WIDTH-1:0] read_addr_plus_max_burst = read_addr_reg + AXI_MAX_BURST_SIZE;
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wire [AXI_ADDR_WIDTH-1:0] read_addr_plus_op_count = read_addr_reg + op_word_count_reg;
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wire [AXI_ADDR_WIDTH-1:0] read_addr_plus_axi_count = read_addr_reg + axi_word_count_reg;
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wire [AXI_ADDR_WIDTH-1:0] write_addr_plus_max_burst = write_addr_reg + AXI_MAX_BURST_SIZE;
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wire [AXI_ADDR_WIDTH-1:0] write_addr_plus_op_count = write_addr_reg + op_word_count_reg;
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wire [AXI_ADDR_WIDTH-1:0] write_addr_plus_axi_count = write_addr_reg + axi_word_count_reg;
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always @* begin
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read_state_next = READ_STATE_IDLE;
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s_axis_desc_ready_next = 1'b0;
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m_axi_araddr_next = m_axi_araddr_reg;
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m_axi_arlen_next = m_axi_arlen_reg;
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m_axi_arvalid_next = m_axi_arvalid_reg && !m_axi_arready;
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read_addr_next = read_addr_reg;
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write_addr_next = write_addr_reg;
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op_word_count_next = op_word_count_reg;
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tr_word_count_next = tr_word_count_reg;
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axi_word_count_next = axi_word_count_reg;
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axi_cmd_addr_next = axi_cmd_addr_reg;
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axi_cmd_offset_next = axi_cmd_offset_reg;
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axi_cmd_first_cycle_offset_next = axi_cmd_first_cycle_offset_reg;
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axi_cmd_last_cycle_offset_next = axi_cmd_last_cycle_offset_reg;
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axi_cmd_input_cycle_count_next = axi_cmd_input_cycle_count_reg;
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axi_cmd_output_cycle_count_next = axi_cmd_output_cycle_count_reg;
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axi_cmd_bubble_cycle_next = axi_cmd_bubble_cycle_reg;
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axi_cmd_last_transfer_next = axi_cmd_last_transfer_reg;
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axi_cmd_tag_next = axi_cmd_tag_reg;
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axi_cmd_valid_next = axi_cmd_valid_reg && !axi_cmd_ready;
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case (read_state_reg)
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READ_STATE_IDLE: begin
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// idle state - load new descriptor to start operation
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s_axis_desc_ready_next = !axi_cmd_valid_reg && enable;
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if (s_axis_desc_ready && s_axis_desc_valid) begin
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if (ENABLE_UNALIGNED) begin
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read_addr_next = s_axis_desc_read_addr;
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write_addr_next = s_axis_desc_write_addr;
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end else begin
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read_addr_next = s_axis_desc_read_addr & ADDR_MASK;
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write_addr_next = s_axis_desc_write_addr & ADDR_MASK;
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end
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axi_cmd_tag_next = s_axis_desc_tag;
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op_word_count_next = s_axis_desc_len;
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s_axis_desc_ready_next = 1'b0;
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read_state_next = READ_STATE_START;
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end else begin
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read_state_next = READ_STATE_IDLE;
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end
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end
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READ_STATE_START: begin
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// start state - compute write length
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if (!axi_cmd_valid_reg) begin
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if (op_word_count_reg <= AXI_MAX_BURST_SIZE - (write_addr_reg & OFFSET_MASK)) begin
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// packet smaller than max burst size
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if (write_addr_reg[12] != write_addr_plus_op_count[12]) begin
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// crosses 4k boundary
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axi_word_count_next = 13'h1000 - write_addr_reg[11:0];
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end else begin
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// does not cross 4k boundary
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axi_word_count_next = op_word_count_reg;
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end
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end else begin
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// packet larger than max burst size
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if (write_addr_reg[12] != write_addr_plus_max_burst[12]) begin
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// crosses 4k boundary
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axi_word_count_next = 13'h1000 - write_addr_reg[11:0];
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end else begin
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// does not cross 4k boundary
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axi_word_count_next = AXI_MAX_BURST_SIZE - (write_addr_reg & OFFSET_MASK);
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end
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end
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write_addr_next = write_addr_reg + axi_word_count_next;
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op_word_count_next = op_word_count_reg - axi_word_count_next;
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axi_cmd_addr_next = write_addr_reg;
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if (ENABLE_UNALIGNED) begin
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axi_cmd_input_cycle_count_next = (axi_word_count_next + (read_addr_reg & OFFSET_MASK) - 1) >> AXI_BURST_SIZE;
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axi_cmd_output_cycle_count_next = (axi_word_count_next + (write_addr_reg & OFFSET_MASK) - 1) >> AXI_BURST_SIZE;
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axi_cmd_offset_next = (write_addr_reg & OFFSET_MASK) - (read_addr_reg & OFFSET_MASK);
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axi_cmd_bubble_cycle_next = (read_addr_reg & OFFSET_MASK) > (write_addr_reg & OFFSET_MASK);
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axi_cmd_first_cycle_offset_next = write_addr_reg & OFFSET_MASK;
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axi_cmd_last_cycle_offset_next = axi_cmd_first_cycle_offset_next + axi_word_count_next & OFFSET_MASK;
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end else begin
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axi_cmd_input_cycle_count_next = (axi_word_count_next - 1) >> AXI_BURST_SIZE;
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axi_cmd_output_cycle_count_next = (axi_word_count_next - 1) >> AXI_BURST_SIZE;
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axi_cmd_offset_next = 0;
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axi_cmd_bubble_cycle_next = 0;
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axi_cmd_first_cycle_offset_next = 0;
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axi_cmd_last_cycle_offset_next = axi_word_count_next & OFFSET_MASK;
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end
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axi_cmd_last_transfer_next = op_word_count_next == 0;
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axi_cmd_valid_next = 1'b1;
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read_state_next = READ_STATE_REQ;
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end else begin
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read_state_next = READ_STATE_START;
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end
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end
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READ_STATE_REQ: begin
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// request state - issue AXI read requests
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if (!m_axi_arvalid) begin
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if (axi_word_count_reg <= AXI_MAX_BURST_SIZE - (read_addr_reg & OFFSET_MASK)) begin
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// packet smaller than max burst size
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if (read_addr_reg[12] != read_addr_plus_axi_count[12]) begin
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// crosses 4k boundary
|
|
tr_word_count_next = 13'h1000 - read_addr_reg[11:0];
|
|
end else begin
|
|
// does not cross 4k boundary
|
|
tr_word_count_next = axi_word_count_reg;
|
|
end
|
|
end else begin
|
|
// packet larger than max burst size
|
|
if (read_addr_reg[12] != read_addr_plus_max_burst[12]) begin
|
|
// crosses 4k boundary
|
|
tr_word_count_next = 13'h1000 - read_addr_reg[11:0];
|
|
end else begin
|
|
// does not cross 4k boundary
|
|
tr_word_count_next = AXI_MAX_BURST_SIZE - (read_addr_reg & OFFSET_MASK);
|
|
end
|
|
end
|
|
|
|
m_axi_araddr_next = read_addr_reg;
|
|
if (ENABLE_UNALIGNED) begin
|
|
m_axi_arlen_next = (tr_word_count_next + (read_addr_reg & OFFSET_MASK) - 1) >> AXI_BURST_SIZE;
|
|
end else begin
|
|
m_axi_arlen_next = (tr_word_count_next - 1) >> AXI_BURST_SIZE;
|
|
end
|
|
m_axi_arvalid_next = 1'b1;
|
|
|
|
read_addr_next = read_addr_reg + tr_word_count_next;
|
|
axi_word_count_next = axi_word_count_reg - tr_word_count_next;
|
|
|
|
if (axi_word_count_next > 0) begin
|
|
read_state_next = READ_STATE_REQ;
|
|
end else if (op_word_count_next > 0) begin
|
|
read_state_next = READ_STATE_START;
|
|
end else begin
|
|
s_axis_desc_ready_next = !axi_cmd_valid_reg && enable;
|
|
read_state_next = READ_STATE_IDLE;
|
|
end
|
|
end else begin
|
|
read_state_next = READ_STATE_REQ;
|
|
end
|
|
end
|
|
endcase
|
|
end
|
|
|
|
always @* begin
|
|
axi_state_next = AXI_STATE_IDLE;
|
|
|
|
m_axis_desc_status_tag_next = m_axis_desc_status_tag_reg;
|
|
m_axis_desc_status_valid_next = 1'b0;
|
|
|
|
m_axi_awaddr_next = m_axi_awaddr_reg;
|
|
m_axi_awlen_next = m_axi_awlen_reg;
|
|
m_axi_awvalid_next = m_axi_awvalid_reg && !m_axi_awready;
|
|
m_axi_wdata_int = shift_axi_rdata;
|
|
m_axi_wstrb_int = {AXI_STRB_WIDTH{1'b0}};
|
|
m_axi_wlast_int = 1'b0;
|
|
m_axi_wvalid_int = 1'b0;
|
|
m_axi_bready_next = 1'b0;
|
|
|
|
m_axi_rready_next = 1'b0;
|
|
|
|
transfer_in_save = 1'b0;
|
|
axi_cmd_ready = 1'b0;
|
|
status_fifo_we = 1'b0;
|
|
|
|
offset_next = offset_reg;
|
|
first_cycle_offset_next = first_cycle_offset_reg;
|
|
last_cycle_offset_next = last_cycle_offset_reg;
|
|
input_cycle_count_next = input_cycle_count_reg;
|
|
output_cycle_count_next = output_cycle_count_reg;
|
|
input_active_next = input_active_reg;
|
|
output_active_next = output_active_reg;
|
|
bubble_cycle_next = bubble_cycle_reg;
|
|
first_input_cycle_next = first_input_cycle_reg;
|
|
first_output_cycle_next = first_output_cycle_reg;
|
|
output_last_cycle_next = output_last_cycle_reg;
|
|
last_transfer_next = last_transfer_reg;
|
|
|
|
tag_next = tag_reg;
|
|
|
|
status_fifo_rd_ptr_next = status_fifo_rd_ptr_reg;
|
|
|
|
status_fifo_wr_tag = tag_reg;
|
|
status_fifo_wr_last = 1'b0;
|
|
|
|
case (axi_state_reg)
|
|
AXI_STATE_IDLE: begin
|
|
// idle state - load new descriptor to start operation
|
|
m_axi_rready_next = 1'b0;
|
|
|
|
// store transfer parameters
|
|
if (ENABLE_UNALIGNED) begin
|
|
offset_next = axi_cmd_offset_reg;
|
|
first_cycle_offset_next = axi_cmd_first_cycle_offset_reg;
|
|
end else begin
|
|
offset_next = 0;
|
|
first_cycle_offset_next = 0;
|
|
end
|
|
last_cycle_offset_next = axi_cmd_last_cycle_offset_reg;
|
|
input_cycle_count_next = axi_cmd_input_cycle_count_reg;
|
|
output_cycle_count_next = axi_cmd_output_cycle_count_reg;
|
|
bubble_cycle_next = axi_cmd_bubble_cycle_reg;
|
|
last_transfer_next = axi_cmd_last_transfer_reg;
|
|
tag_next = axi_cmd_tag_reg;
|
|
|
|
output_last_cycle_next = output_cycle_count_next == 0;
|
|
input_active_next = 1'b1;
|
|
output_active_next = 1'b1;
|
|
first_input_cycle_next = 1'b1;
|
|
first_output_cycle_next = 1'b1;
|
|
|
|
if (!m_axi_awvalid && axi_cmd_valid_reg) begin
|
|
axi_cmd_ready = 1'b1;
|
|
|
|
m_axi_awaddr_next = axi_cmd_addr_reg;
|
|
m_axi_awlen_next = axi_cmd_output_cycle_count_reg;
|
|
m_axi_awvalid_next = 1'b1;
|
|
|
|
m_axi_rready_next = m_axi_wready_int_early;
|
|
axi_state_next = AXI_STATE_WRITE;
|
|
end
|
|
end
|
|
AXI_STATE_WRITE: begin
|
|
// handle AXI read data
|
|
m_axi_rready_next = m_axi_wready_int_early && input_active_reg;
|
|
|
|
if (m_axi_wready_int_reg && ((m_axi_rready && m_axi_rvalid) || !input_active_reg)) begin
|
|
// transfer in AXI read data
|
|
transfer_in_save = m_axi_rready && m_axi_rvalid;
|
|
|
|
if (ENABLE_UNALIGNED && first_input_cycle_reg && bubble_cycle_reg) begin
|
|
if (input_active_reg) begin
|
|
input_cycle_count_next = input_cycle_count_reg - 1;
|
|
input_active_next = input_cycle_count_reg > 0;
|
|
end
|
|
bubble_cycle_next = 1'b0;
|
|
first_input_cycle_next = 1'b0;
|
|
|
|
m_axi_rready_next = m_axi_wready_int_early && input_active_next;
|
|
axi_state_next = AXI_STATE_WRITE;
|
|
end else begin
|
|
// update counters
|
|
if (input_active_reg) begin
|
|
input_cycle_count_next = input_cycle_count_reg - 1;
|
|
input_active_next = input_cycle_count_reg > 0;
|
|
end
|
|
if (output_active_reg) begin
|
|
output_cycle_count_next = output_cycle_count_reg - 1;
|
|
output_active_next = output_cycle_count_reg > 0;
|
|
end
|
|
output_last_cycle_next = output_cycle_count_next == 0;
|
|
bubble_cycle_next = 1'b0;
|
|
first_input_cycle_next = 1'b0;
|
|
first_output_cycle_next = 1'b0;
|
|
|
|
// pass through read data
|
|
m_axi_wdata_int = shift_axi_rdata;
|
|
if (first_output_cycle_reg) begin
|
|
m_axi_wstrb_int = {AXI_STRB_WIDTH{1'b1}} << first_cycle_offset_reg;
|
|
end else begin
|
|
m_axi_wstrb_int = {AXI_STRB_WIDTH{1'b1}};
|
|
end
|
|
m_axi_wvalid_int = 1'b1;
|
|
|
|
if (output_last_cycle_reg) begin
|
|
// no more data to transfer, finish operation
|
|
if (last_cycle_offset_reg > 0) begin
|
|
m_axi_wstrb_int = m_axi_wstrb_int & {AXI_STRB_WIDTH{1'b1}} >> (AXI_STRB_WIDTH - last_cycle_offset_reg);
|
|
end
|
|
m_axi_wlast_int = 1'b1;
|
|
|
|
status_fifo_we = 1'b1;
|
|
status_fifo_wr_tag = tag_reg;
|
|
status_fifo_wr_last = last_transfer_reg;
|
|
|
|
m_axi_rready_next = 1'b0;
|
|
axi_state_next = AXI_STATE_IDLE;
|
|
end else begin
|
|
// more cycles in AXI transfer
|
|
axi_state_next = AXI_STATE_WRITE;
|
|
end
|
|
end
|
|
end else begin
|
|
axi_state_next = AXI_STATE_WRITE;
|
|
end
|
|
end
|
|
endcase
|
|
|
|
if (status_fifo_rd_ptr_reg != status_fifo_wr_ptr_reg) begin
|
|
// status FIFO not empty
|
|
if (m_axi_bready && m_axi_bvalid) begin
|
|
// got write completion, pop and return status
|
|
m_axis_desc_status_tag_next = status_fifo_tag[status_fifo_rd_ptr_reg[STATUS_FIFO_ADDR_WIDTH-1:0]];
|
|
m_axis_desc_status_valid_next = status_fifo_last[status_fifo_rd_ptr_reg[STATUS_FIFO_ADDR_WIDTH-1:0]];
|
|
status_fifo_rd_ptr_next = status_fifo_rd_ptr_reg + 1;
|
|
m_axi_bready_next = 1'b0;
|
|
end else begin
|
|
// wait for write completion
|
|
m_axi_bready_next = 1'b1;
|
|
end
|
|
end
|
|
end
|
|
|
|
always @(posedge clk) begin
|
|
if (rst) begin
|
|
read_state_reg <= READ_STATE_IDLE;
|
|
axi_state_reg <= AXI_STATE_IDLE;
|
|
axi_cmd_valid_reg <= 1'b0;
|
|
s_axis_desc_ready_reg <= 1'b0;
|
|
m_axis_desc_status_valid_reg <= 1'b0;
|
|
m_axi_awvalid_reg <= 1'b0;
|
|
m_axi_bready_reg <= 1'b0;
|
|
m_axi_arvalid_reg <= 1'b0;
|
|
m_axi_rready_reg <= 1'b0;
|
|
|
|
status_fifo_wr_ptr_reg <= 0;
|
|
status_fifo_rd_ptr_reg <= 0;
|
|
end else begin
|
|
read_state_reg <= read_state_next;
|
|
axi_state_reg <= axi_state_next;
|
|
axi_cmd_valid_reg <= axi_cmd_valid_next;
|
|
s_axis_desc_ready_reg <= s_axis_desc_ready_next;
|
|
m_axis_desc_status_valid_reg <= m_axis_desc_status_valid_next;
|
|
m_axi_awvalid_reg <= m_axi_awvalid_next;
|
|
m_axi_bready_reg <= m_axi_bready_next;
|
|
m_axi_arvalid_reg <= m_axi_arvalid_next;
|
|
m_axi_rready_reg <= m_axi_rready_next;
|
|
|
|
if (status_fifo_we) begin
|
|
status_fifo_wr_ptr_reg <= status_fifo_wr_ptr_reg + 1;
|
|
end
|
|
status_fifo_rd_ptr_reg <= status_fifo_rd_ptr_next;
|
|
end
|
|
|
|
m_axis_desc_status_tag_reg <= m_axis_desc_status_tag_next;
|
|
|
|
m_axi_awaddr_reg <= m_axi_awaddr_next;
|
|
m_axi_awlen_reg <= m_axi_awlen_next;
|
|
m_axi_araddr_reg <= m_axi_araddr_next;
|
|
m_axi_arlen_reg <= m_axi_arlen_next;
|
|
|
|
read_addr_reg <= read_addr_next;
|
|
write_addr_reg <= write_addr_next;
|
|
op_word_count_reg <= op_word_count_next;
|
|
tr_word_count_reg <= tr_word_count_next;
|
|
axi_word_count_reg <= axi_word_count_next;
|
|
|
|
axi_cmd_addr_reg <= axi_cmd_addr_next;
|
|
axi_cmd_offset_reg <= axi_cmd_offset_next;
|
|
axi_cmd_first_cycle_offset_reg <= axi_cmd_first_cycle_offset_next;
|
|
axi_cmd_last_cycle_offset_reg <= axi_cmd_last_cycle_offset_next;
|
|
axi_cmd_input_cycle_count_reg <= axi_cmd_input_cycle_count_next;
|
|
axi_cmd_output_cycle_count_reg <= axi_cmd_output_cycle_count_next;
|
|
axi_cmd_bubble_cycle_reg <= axi_cmd_bubble_cycle_next;
|
|
axi_cmd_last_transfer_reg <= axi_cmd_last_transfer_next;
|
|
axi_cmd_tag_reg <= axi_cmd_tag_next;
|
|
axi_cmd_valid_reg <= axi_cmd_valid_next;
|
|
|
|
offset_reg <= offset_next;
|
|
first_cycle_offset_reg <= first_cycle_offset_next;
|
|
last_cycle_offset_reg <= last_cycle_offset_next;
|
|
input_cycle_count_reg <= input_cycle_count_next;
|
|
output_cycle_count_reg <= output_cycle_count_next;
|
|
input_active_reg <= input_active_next;
|
|
output_active_reg <= output_active_next;
|
|
bubble_cycle_reg <= bubble_cycle_next;
|
|
first_input_cycle_reg <= first_input_cycle_next;
|
|
first_output_cycle_reg <= first_output_cycle_next;
|
|
output_last_cycle_reg <= output_last_cycle_next;
|
|
last_transfer_reg <= last_transfer_next;
|
|
|
|
tag_reg <= tag_next;
|
|
|
|
if (transfer_in_save) begin
|
|
save_axi_rdata_reg <= m_axi_rdata;
|
|
end
|
|
|
|
if (status_fifo_we) begin
|
|
status_fifo_tag[status_fifo_wr_ptr_reg[STATUS_FIFO_ADDR_WIDTH-1:0]] <= status_fifo_wr_tag;
|
|
status_fifo_last[status_fifo_wr_ptr_reg[STATUS_FIFO_ADDR_WIDTH-1:0]] <= status_fifo_wr_last;
|
|
status_fifo_wr_ptr_reg <= status_fifo_wr_ptr_reg + 1;
|
|
end
|
|
end
|
|
|
|
// output datapath logic
|
|
reg [AXI_DATA_WIDTH-1:0] m_axi_wdata_reg = {AXI_DATA_WIDTH{1'b0}};
|
|
reg [AXI_STRB_WIDTH-1:0] m_axi_wstrb_reg = {AXI_STRB_WIDTH{1'b0}};
|
|
reg m_axi_wlast_reg = 1'b0;
|
|
reg m_axi_wvalid_reg = 1'b0, m_axi_wvalid_next;
|
|
|
|
reg [AXI_DATA_WIDTH-1:0] temp_m_axi_wdata_reg = {AXI_DATA_WIDTH{1'b0}};
|
|
reg [AXI_STRB_WIDTH-1:0] temp_m_axi_wstrb_reg = {AXI_STRB_WIDTH{1'b0}};
|
|
reg temp_m_axi_wlast_reg = 1'b0;
|
|
reg temp_m_axi_wvalid_reg = 1'b0, temp_m_axi_wvalid_next;
|
|
|
|
// datapath control
|
|
reg store_axi_w_int_to_output;
|
|
reg store_axi_w_int_to_temp;
|
|
reg store_axi_w_temp_to_output;
|
|
|
|
assign m_axi_wdata = m_axi_wdata_reg;
|
|
assign m_axi_wstrb = m_axi_wstrb_reg;
|
|
assign m_axi_wvalid = m_axi_wvalid_reg;
|
|
assign m_axi_wlast = m_axi_wlast_reg;
|
|
|
|
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
|
assign m_axi_wready_int_early = m_axi_wready || (!temp_m_axi_wvalid_reg && (!m_axi_wvalid_reg || !m_axi_wvalid_int));
|
|
|
|
always @* begin
|
|
// transfer sink ready state to source
|
|
m_axi_wvalid_next = m_axi_wvalid_reg;
|
|
temp_m_axi_wvalid_next = temp_m_axi_wvalid_reg;
|
|
|
|
store_axi_w_int_to_output = 1'b0;
|
|
store_axi_w_int_to_temp = 1'b0;
|
|
store_axi_w_temp_to_output = 1'b0;
|
|
|
|
if (m_axi_wready_int_reg) begin
|
|
// input is ready
|
|
if (m_axi_wready || !m_axi_wvalid_reg) begin
|
|
// output is ready or currently not valid, transfer data to output
|
|
m_axi_wvalid_next = m_axi_wvalid_int;
|
|
store_axi_w_int_to_output = 1'b1;
|
|
end else begin
|
|
// output is not ready, store input in temp
|
|
temp_m_axi_wvalid_next = m_axi_wvalid_int;
|
|
store_axi_w_int_to_temp = 1'b1;
|
|
end
|
|
end else if (m_axi_wready) begin
|
|
// input is not ready, but output is ready
|
|
m_axi_wvalid_next = temp_m_axi_wvalid_reg;
|
|
temp_m_axi_wvalid_next = 1'b0;
|
|
store_axi_w_temp_to_output = 1'b1;
|
|
end
|
|
end
|
|
|
|
always @(posedge clk) begin
|
|
if (rst) begin
|
|
m_axi_wvalid_reg <= 1'b0;
|
|
m_axi_wready_int_reg <= 1'b0;
|
|
temp_m_axi_wvalid_reg <= 1'b0;
|
|
end else begin
|
|
m_axi_wvalid_reg <= m_axi_wvalid_next;
|
|
m_axi_wready_int_reg <= m_axi_wready_int_early;
|
|
temp_m_axi_wvalid_reg <= temp_m_axi_wvalid_next;
|
|
end
|
|
|
|
// datapath
|
|
if (store_axi_w_int_to_output) begin
|
|
m_axi_wdata_reg <= m_axi_wdata_int;
|
|
m_axi_wstrb_reg <= m_axi_wstrb_int;
|
|
m_axi_wlast_reg <= m_axi_wlast_int;
|
|
end else if (store_axi_w_temp_to_output) begin
|
|
m_axi_wdata_reg <= temp_m_axi_wdata_reg;
|
|
m_axi_wstrb_reg <= temp_m_axi_wstrb_reg;
|
|
m_axi_wlast_reg <= temp_m_axi_wlast_reg;
|
|
end
|
|
|
|
if (store_axi_w_int_to_temp) begin
|
|
temp_m_axi_wdata_reg <= m_axi_wdata_int;
|
|
temp_m_axi_wstrb_reg <= m_axi_wstrb_int;
|
|
temp_m_axi_wlast_reg <= m_axi_wlast_int;
|
|
end
|
|
end
|
|
|
|
endmodule
|