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563 lines
23 KiB
Verilog
563 lines
23 KiB
Verilog
/*
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Copyright (c) 2019 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* AXI stream source DMA client
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*/
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module dma_client_axis_source #
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(
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// RAM segment count
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parameter SEG_COUNT = 2,
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// RAM segment data width
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parameter SEG_DATA_WIDTH = 64,
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// RAM segment address width
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parameter SEG_ADDR_WIDTH = 8,
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// RAM segment byte enable width
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parameter SEG_BE_WIDTH = SEG_DATA_WIDTH/8,
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// RAM address width
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parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH),
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// Width of AXI stream interfaces in bits
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parameter AXIS_DATA_WIDTH = SEG_DATA_WIDTH*SEG_COUNT/2,
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// Use AXI stream tkeep signal
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parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8),
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// AXI stream tkeep signal width (words per cycle)
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parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8),
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// Use AXI stream tlast signal
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parameter AXIS_LAST_ENABLE = 1,
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// Propagate AXI stream tid signal
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parameter AXIS_ID_ENABLE = 0,
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// AXI stream tid signal width
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parameter AXIS_ID_WIDTH = 8,
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// Propagate AXI stream tdest signal
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parameter AXIS_DEST_ENABLE = 0,
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// AXI stream tdest signal width
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parameter AXIS_DEST_WIDTH = 8,
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// Propagate AXI stream tuser signal
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parameter AXIS_USER_ENABLE = 1,
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// AXI stream tuser signal width
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parameter AXIS_USER_WIDTH = 1,
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// Width of length field
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parameter LEN_WIDTH = 16,
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// Width of tag field
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parameter TAG_WIDTH = 8
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI read descriptor input
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*/
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input wire [RAM_ADDR_WIDTH-1:0] s_axis_read_desc_ram_addr,
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input wire [LEN_WIDTH-1:0] s_axis_read_desc_len,
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input wire [TAG_WIDTH-1:0] s_axis_read_desc_tag,
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input wire [AXIS_ID_WIDTH-1:0] s_axis_read_desc_id,
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input wire [AXIS_DEST_WIDTH-1:0] s_axis_read_desc_dest,
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input wire [AXIS_USER_WIDTH-1:0] s_axis_read_desc_user,
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input wire s_axis_read_desc_valid,
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output wire s_axis_read_desc_ready,
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/*
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* AXI read descriptor status output
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*/
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output wire [TAG_WIDTH-1:0] m_axis_read_desc_status_tag,
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output wire m_axis_read_desc_status_valid,
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/*
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* AXI stream read data output
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*/
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output wire [AXIS_DATA_WIDTH-1:0] m_axis_read_data_tdata,
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output wire [AXIS_KEEP_WIDTH-1:0] m_axis_read_data_tkeep,
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output wire m_axis_read_data_tvalid,
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input wire m_axis_read_data_tready,
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output wire m_axis_read_data_tlast,
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output wire [AXIS_ID_WIDTH-1:0] m_axis_read_data_tid,
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output wire [AXIS_DEST_WIDTH-1:0] m_axis_read_data_tdest,
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output wire [AXIS_USER_WIDTH-1:0] m_axis_read_data_tuser,
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/*
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* RAM interface
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*/
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output wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ram_rd_cmd_addr,
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output wire [SEG_COUNT-1:0] ram_rd_cmd_valid,
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input wire [SEG_COUNT-1:0] ram_rd_cmd_ready,
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input wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ram_rd_resp_data,
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input wire [SEG_COUNT-1:0] ram_rd_resp_valid,
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output wire [SEG_COUNT-1:0] ram_rd_resp_ready,
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/*
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* Configuration
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*/
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input wire enable
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);
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parameter RAM_WORD_WIDTH = SEG_BE_WIDTH;
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parameter RAM_WORD_SIZE = SEG_DATA_WIDTH/RAM_WORD_WIDTH;
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parameter AXIS_KEEP_WIDTH_INT = AXIS_KEEP_ENABLE ? AXIS_KEEP_WIDTH : 1;
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parameter AXIS_WORD_WIDTH = AXIS_KEEP_WIDTH_INT;
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parameter AXIS_WORD_SIZE = AXIS_DATA_WIDTH/AXIS_WORD_WIDTH;
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parameter PART_COUNT = SEG_COUNT*SEG_BE_WIDTH / AXIS_KEEP_WIDTH_INT;
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parameter PART_COUNT_WIDTH = PART_COUNT > 1 ? $clog2(PART_COUNT) : 1;
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parameter PART_OFFSET_WIDTH = AXIS_KEEP_WIDTH_INT > 1 ? $clog2(AXIS_KEEP_WIDTH_INT) : 1;
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parameter PARTS_PER_SEG = (SEG_BE_WIDTH + AXIS_KEEP_WIDTH_INT - 1) / AXIS_KEEP_WIDTH_INT;
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parameter SEGS_PER_PART = (AXIS_KEEP_WIDTH_INT + SEG_BE_WIDTH - 1) / SEG_BE_WIDTH;
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parameter OFFSET_WIDTH = AXIS_KEEP_WIDTH_INT > 1 ? $clog2(AXIS_KEEP_WIDTH_INT) : 1;
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parameter OFFSET_MASK = AXIS_KEEP_WIDTH_INT > 1 ? {OFFSET_WIDTH{1'b1}} : 0;
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parameter ADDR_MASK = {RAM_ADDR_WIDTH{1'b1}} << $clog2(AXIS_KEEP_WIDTH_INT);
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parameter CYCLE_COUNT_WIDTH = LEN_WIDTH - $clog2(AXIS_KEEP_WIDTH_INT) + 1;
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parameter OUTPUT_FIFO_ADDR_WIDTH = 5;
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// bus width assertions
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initial begin
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if (RAM_WORD_SIZE * SEG_BE_WIDTH != SEG_DATA_WIDTH) begin
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$error("Error: RAM data width not evenly divisble (instance %m)");
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$finish;
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end
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if (AXIS_WORD_SIZE * AXIS_KEEP_WIDTH_INT != AXIS_DATA_WIDTH) begin
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$error("Error: AXI stream data width not evenly divisble (instance %m)");
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$finish;
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end
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if (RAM_WORD_SIZE != AXIS_WORD_SIZE) begin
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$error("Error: word size mismatch (instance %m)");
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$finish;
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end
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if (2**$clog2(RAM_WORD_WIDTH) != RAM_WORD_WIDTH) begin
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$error("Error: RAM word width must be even power of two (instance %m)");
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$finish;
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end
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if (RAM_ADDR_WIDTH != SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH)) begin
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$error("Error: RAM_ADDR_WIDTH does not match RAM configuration (instance %m)");
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$finish;
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end
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if (AXIS_DATA_WIDTH > SEG_COUNT*SEG_DATA_WIDTH) begin
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$error("Error: AXI stream interface width must not be wider than RAM interface width (instance %m)");
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$finish;
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end
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if (AXIS_DATA_WIDTH*2**$clog2(PART_COUNT) != SEG_COUNT*SEG_DATA_WIDTH) begin
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$error("Error: AXI stream interface width must be a power of two fraction of RAM interface width (instance %m)");
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$finish;
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end
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end
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localparam [0:0]
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READ_STATE_IDLE = 1'd0,
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READ_STATE_READ = 1'd1;
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reg [0:0] read_state_reg = READ_STATE_IDLE, read_state_next;
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localparam [0:0]
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AXIS_STATE_IDLE = 1'd0,
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AXIS_STATE_READ = 1'd1;
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reg [0:0] axis_state_reg = AXIS_STATE_IDLE, axis_state_next;
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// datapath control signals
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reg axis_cmd_ready;
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integer i;
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reg [RAM_ADDR_WIDTH-1:0] read_addr_reg = {RAM_ADDR_WIDTH{1'b0}}, read_addr_next;
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reg [SEG_COUNT-1:0] read_ram_mask_reg = 0, read_ram_mask_next;
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reg [CYCLE_COUNT_WIDTH-1:0] read_cycle_count_reg = {CYCLE_COUNT_WIDTH{1'b0}}, read_cycle_count_next;
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reg [RAM_ADDR_WIDTH-1:0] axis_cmd_addr_reg = {RAM_ADDR_WIDTH{1'b0}}, axis_cmd_addr_next;
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reg [OFFSET_WIDTH-1:0] axis_cmd_last_cycle_offset_reg = {OFFSET_WIDTH{1'b0}}, axis_cmd_last_cycle_offset_next;
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reg [CYCLE_COUNT_WIDTH-1:0] axis_cmd_cycle_count_reg = {CYCLE_COUNT_WIDTH{1'b0}}, axis_cmd_cycle_count_next;
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reg [TAG_WIDTH-1:0] axis_cmd_tag_reg = {TAG_WIDTH{1'b0}}, axis_cmd_tag_next;
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reg [AXIS_ID_WIDTH-1:0] axis_cmd_axis_id_reg = {AXIS_ID_WIDTH{1'b0}}, axis_cmd_axis_id_next;
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reg [AXIS_DEST_WIDTH-1:0] axis_cmd_axis_dest_reg = {AXIS_DEST_WIDTH{1'b0}}, axis_cmd_axis_dest_next;
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reg [AXIS_USER_WIDTH-1:0] axis_cmd_axis_user_reg = {AXIS_USER_WIDTH{1'b0}}, axis_cmd_axis_user_next;
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reg axis_cmd_valid_reg = 1'b0, axis_cmd_valid_next;
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reg [RAM_ADDR_WIDTH-1:0] addr_reg = {RAM_ADDR_WIDTH{1'b0}}, addr_next;
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reg [SEG_COUNT-1:0] ram_mask_reg = 0, ram_mask_next;
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reg [OFFSET_WIDTH-1:0] last_cycle_offset_reg = {OFFSET_WIDTH{1'b0}}, last_cycle_offset_next;
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reg [CYCLE_COUNT_WIDTH-1:0] cycle_count_reg = {CYCLE_COUNT_WIDTH{1'b0}}, cycle_count_next;
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reg last_cycle_reg = 1'b0, last_cycle_next;
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reg [AXIS_ID_WIDTH-1:0] axis_id_reg = {AXIS_ID_WIDTH{1'b0}}, axis_id_next;
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reg [AXIS_DEST_WIDTH-1:0] axis_dest_reg = {AXIS_DEST_WIDTH{1'b0}}, axis_dest_next;
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reg [AXIS_USER_WIDTH-1:0] axis_user_reg = {AXIS_USER_WIDTH{1'b0}}, axis_user_next;
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reg s_axis_read_desc_ready_reg = 1'b0, s_axis_read_desc_ready_next;
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reg [TAG_WIDTH-1:0] m_axis_read_desc_status_tag_reg = {TAG_WIDTH{1'b0}}, m_axis_read_desc_status_tag_next;
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reg m_axis_read_desc_status_valid_reg = 1'b0, m_axis_read_desc_status_valid_next;
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reg [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ram_rd_cmd_addr_reg = 0, ram_rd_cmd_addr_next;
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reg [SEG_COUNT-1:0] ram_rd_cmd_valid_reg = 0, ram_rd_cmd_valid_next;
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reg [SEG_COUNT-1:0] ram_rd_resp_ready_cmb;
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// internal datapath
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reg [AXIS_DATA_WIDTH-1:0] m_axis_read_data_tdata_int;
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reg [AXIS_KEEP_WIDTH-1:0] m_axis_read_data_tkeep_int;
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reg m_axis_read_data_tvalid_int;
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wire m_axis_read_data_tready_int;
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reg m_axis_read_data_tlast_int;
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reg [AXIS_ID_WIDTH-1:0] m_axis_read_data_tid_int;
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reg [AXIS_DEST_WIDTH-1:0] m_axis_read_data_tdest_int;
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reg [AXIS_USER_WIDTH-1:0] m_axis_read_data_tuser_int;
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assign s_axis_read_desc_ready = s_axis_read_desc_ready_reg;
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assign m_axis_read_desc_status_tag = m_axis_read_desc_status_tag_reg;
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assign m_axis_read_desc_status_valid = m_axis_read_desc_status_valid_reg;
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assign ram_rd_cmd_addr = ram_rd_cmd_addr_reg;
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assign ram_rd_cmd_valid = ram_rd_cmd_valid_reg;
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assign ram_rd_resp_ready = ram_rd_resp_ready_cmb;
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always @* begin
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read_state_next = READ_STATE_IDLE;
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s_axis_read_desc_ready_next = 1'b0;
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ram_rd_cmd_addr_next = ram_rd_cmd_addr_reg;
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ram_rd_cmd_valid_next = ram_rd_cmd_valid_reg & ~ram_rd_cmd_ready;
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read_addr_next = read_addr_reg;
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read_ram_mask_next = read_ram_mask_reg;
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read_cycle_count_next = read_cycle_count_reg;
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axis_cmd_addr_next = axis_cmd_addr_reg;
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axis_cmd_last_cycle_offset_next = axis_cmd_last_cycle_offset_reg;
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axis_cmd_cycle_count_next = axis_cmd_cycle_count_reg;
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axis_cmd_tag_next = axis_cmd_tag_reg;
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axis_cmd_axis_id_next = axis_cmd_axis_id_reg;
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axis_cmd_axis_dest_next = axis_cmd_axis_dest_reg;
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axis_cmd_axis_user_next = axis_cmd_axis_user_reg;
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axis_cmd_valid_next = axis_cmd_valid_reg && !axis_cmd_ready;
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case (read_state_reg)
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READ_STATE_IDLE: begin
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// idle state - load new descriptor to start operation
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s_axis_read_desc_ready_next = !axis_cmd_valid_reg && enable;
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if (s_axis_read_desc_ready && s_axis_read_desc_valid) begin
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read_addr_next = s_axis_read_desc_ram_addr & ADDR_MASK;
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if (PART_COUNT > 1) begin
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read_ram_mask_next = {SEGS_PER_PART{1'b1}} << ((((read_addr_next >> PART_OFFSET_WIDTH) & ({PART_COUNT_WIDTH{1'b1}})) / PARTS_PER_SEG) * SEGS_PER_PART);
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end else begin
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read_ram_mask_next = {SEG_COUNT{1'b1}};
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end
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axis_cmd_addr_next = s_axis_read_desc_ram_addr & ADDR_MASK;
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axis_cmd_last_cycle_offset_next = s_axis_read_desc_len & OFFSET_MASK;
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axis_cmd_tag_next = s_axis_read_desc_tag;
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axis_cmd_axis_id_next = s_axis_read_desc_id;
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axis_cmd_axis_dest_next = s_axis_read_desc_dest;
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axis_cmd_axis_user_next = s_axis_read_desc_user;
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axis_cmd_cycle_count_next = (s_axis_read_desc_len - 1) >> $clog2(AXIS_KEEP_WIDTH_INT);
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read_cycle_count_next = (s_axis_read_desc_len - 1) >> $clog2(AXIS_KEEP_WIDTH_INT);
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axis_cmd_valid_next = 1'b1;
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s_axis_read_desc_ready_next = 1'b0;
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read_state_next = READ_STATE_READ;
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end else begin
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read_state_next = READ_STATE_IDLE;
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end
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end
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READ_STATE_READ: begin
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// read state - start new read operations
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if (!(ram_rd_cmd_valid & ~ram_rd_cmd_ready & read_ram_mask_reg)) begin
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// update counters
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read_addr_next = read_addr_reg + AXIS_KEEP_WIDTH_INT;
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read_cycle_count_next = read_cycle_count_reg - 1;
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if (PART_COUNT > 1) begin
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read_ram_mask_next = {SEGS_PER_PART{1'b1}} << ((((read_addr_next >> PART_OFFSET_WIDTH) & ({PART_COUNT_WIDTH{1'b1}})) / PARTS_PER_SEG) * SEGS_PER_PART);
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end else begin
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read_ram_mask_next = {SEG_COUNT{1'b1}};
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end
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for (i = 0; i < SEG_COUNT; i = i + 1) begin
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if (read_ram_mask_reg[i]) begin
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ram_rd_cmd_addr_next[i*SEG_ADDR_WIDTH +: SEG_ADDR_WIDTH] = read_addr_reg[RAM_ADDR_WIDTH-1:RAM_ADDR_WIDTH-SEG_ADDR_WIDTH];
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ram_rd_cmd_valid_next[i] = 1'b1;
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end
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end
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if (read_cycle_count_reg == 0) begin
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s_axis_read_desc_ready_next = !axis_cmd_valid_reg && enable;
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read_state_next = READ_STATE_IDLE;
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end else begin
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read_state_next = READ_STATE_READ;
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end
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end else begin
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read_state_next = READ_STATE_READ;
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end
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end
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endcase
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end
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always @* begin
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axis_state_next = AXIS_STATE_IDLE;
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m_axis_read_desc_status_tag_next = m_axis_read_desc_status_tag_reg;
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m_axis_read_desc_status_valid_next = 1'b0;
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if (PART_COUNT > 1) begin
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m_axis_read_data_tdata_int = ram_rd_resp_data >> (((addr_reg >> PART_OFFSET_WIDTH) & {PART_COUNT_WIDTH{1'b1}}) * AXIS_DATA_WIDTH);
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end else begin
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m_axis_read_data_tdata_int = ram_rd_resp_data;
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end
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m_axis_read_data_tkeep_int = {AXIS_KEEP_WIDTH{1'b1}};
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m_axis_read_data_tlast_int = 1'b0;
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m_axis_read_data_tvalid_int = 1'b0;
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m_axis_read_data_tid_int = axis_id_reg;
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m_axis_read_data_tdest_int = axis_dest_reg;
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m_axis_read_data_tuser_int = axis_user_reg;
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ram_rd_resp_ready_cmb = {SEG_COUNT{1'b0}};
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axis_cmd_ready = 1'b0;
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addr_next = addr_reg;
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ram_mask_next = ram_mask_reg;
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last_cycle_offset_next = last_cycle_offset_reg;
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cycle_count_next = cycle_count_reg;
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last_cycle_next = last_cycle_reg;
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axis_id_next = axis_id_reg;
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axis_dest_next = axis_dest_reg;
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axis_user_next = axis_user_reg;
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case (axis_state_reg)
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AXIS_STATE_IDLE: begin
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// idle state - load new descriptor to start operation
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// store transfer parameters
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addr_next = axis_cmd_addr_reg;
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last_cycle_offset_next = axis_cmd_last_cycle_offset_reg;
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cycle_count_next = axis_cmd_cycle_count_reg;
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last_cycle_next = axis_cmd_cycle_count_reg == 0;
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if (PART_COUNT > 1) begin
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ram_mask_next = {SEGS_PER_PART{1'b1}} << ((((addr_next >> PART_OFFSET_WIDTH) & ({PART_COUNT_WIDTH{1'b1}})) / PARTS_PER_SEG) * SEGS_PER_PART);
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end else begin
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ram_mask_next = {SEG_COUNT{1'b1}};
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end
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m_axis_read_desc_status_tag_next = axis_cmd_tag_reg;
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axis_id_next = axis_cmd_axis_id_reg;
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axis_dest_next = axis_cmd_axis_dest_reg;
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axis_user_next = axis_cmd_axis_user_reg;
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if (axis_cmd_valid_reg) begin
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axis_cmd_ready = 1'b1;
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axis_state_next = AXIS_STATE_READ;
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end
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end
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AXIS_STATE_READ: begin
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// handle read data
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ram_rd_resp_ready_cmb = {SEG_COUNT{1'b0}};
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if (!(ram_mask_reg & ~ram_rd_resp_valid) && m_axis_read_data_tready_int) begin
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// transfer in read data
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ram_rd_resp_ready_cmb = ram_mask_reg;
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// update counters
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addr_next = addr_reg + AXIS_KEEP_WIDTH_INT;
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cycle_count_next = cycle_count_reg - 1;
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last_cycle_next = cycle_count_next == 0;
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|
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if (PART_COUNT > 1) begin
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ram_mask_next = {SEGS_PER_PART{1'b1}} << ((((addr_next >> PART_OFFSET_WIDTH) & ({PART_COUNT_WIDTH{1'b1}})) / PARTS_PER_SEG) * SEGS_PER_PART);
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end else begin
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ram_mask_next = {SEG_COUNT{1'b1}};
|
|
end
|
|
|
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if (PART_COUNT > 1) begin
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m_axis_read_data_tdata_int = ram_rd_resp_data >> (((addr_reg >> PART_OFFSET_WIDTH) & {PART_COUNT_WIDTH{1'b1}}) * AXIS_DATA_WIDTH);
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end else begin
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m_axis_read_data_tdata_int = ram_rd_resp_data;
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end
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m_axis_read_data_tkeep_int = {AXIS_KEEP_WIDTH_INT{1'b1}};
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m_axis_read_data_tvalid_int = 1'b1;
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|
|
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if (last_cycle_reg) begin
|
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// no more data to transfer, finish operation
|
|
if (last_cycle_offset_reg > 0) begin
|
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m_axis_read_data_tkeep_int = {AXIS_KEEP_WIDTH_INT{1'b1}} >> (AXIS_KEEP_WIDTH_INT - last_cycle_offset_reg);
|
|
end
|
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m_axis_read_data_tlast_int = 1'b1;
|
|
|
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m_axis_read_desc_status_valid_next = 1'b1;
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|
|
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axis_state_next = AXIS_STATE_IDLE;
|
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end else begin
|
|
// more cycles in AXI transfer
|
|
axis_state_next = AXIS_STATE_READ;
|
|
end
|
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end else begin
|
|
axis_state_next = AXIS_STATE_READ;
|
|
end
|
|
end
|
|
endcase
|
|
end
|
|
|
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always @(posedge clk) begin
|
|
read_state_reg <= read_state_next;
|
|
axis_state_reg <= axis_state_next;
|
|
|
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s_axis_read_desc_ready_reg <= s_axis_read_desc_ready_next;
|
|
|
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m_axis_read_desc_status_tag_reg <= m_axis_read_desc_status_tag_next;
|
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m_axis_read_desc_status_valid_reg <= m_axis_read_desc_status_valid_next;
|
|
|
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ram_rd_cmd_addr_reg <= ram_rd_cmd_addr_next;
|
|
ram_rd_cmd_valid_reg <= ram_rd_cmd_valid_next;
|
|
|
|
read_addr_reg <= read_addr_next;
|
|
read_ram_mask_reg <= read_ram_mask_next;
|
|
read_cycle_count_reg <= read_cycle_count_next;
|
|
|
|
axis_cmd_addr_reg <= axis_cmd_addr_next;
|
|
axis_cmd_last_cycle_offset_reg <= axis_cmd_last_cycle_offset_next;
|
|
axis_cmd_cycle_count_reg <= axis_cmd_cycle_count_next;
|
|
axis_cmd_tag_reg <= axis_cmd_tag_next;
|
|
axis_cmd_axis_id_reg <= axis_cmd_axis_id_next;
|
|
axis_cmd_axis_dest_reg <= axis_cmd_axis_dest_next;
|
|
axis_cmd_axis_user_reg <= axis_cmd_axis_user_next;
|
|
axis_cmd_valid_reg <= axis_cmd_valid_next;
|
|
|
|
addr_reg <= addr_next;
|
|
ram_mask_reg <= ram_mask_next;
|
|
last_cycle_offset_reg <= last_cycle_offset_next;
|
|
cycle_count_reg <= cycle_count_next;
|
|
last_cycle_reg <= last_cycle_next;
|
|
|
|
axis_id_reg <= axis_id_next;
|
|
axis_dest_reg <= axis_dest_next;
|
|
axis_user_reg <= axis_user_next;
|
|
|
|
if (rst) begin
|
|
read_state_reg <= READ_STATE_IDLE;
|
|
axis_state_reg <= AXIS_STATE_IDLE;
|
|
|
|
axis_cmd_valid_reg <= 1'b0;
|
|
|
|
s_axis_read_desc_ready_reg <= 1'b0;
|
|
m_axis_read_desc_status_valid_reg <= 1'b0;
|
|
|
|
ram_rd_cmd_valid_reg <= {SEG_COUNT{1'b0}};
|
|
end
|
|
end
|
|
|
|
// output datapath logic
|
|
reg [AXIS_DATA_WIDTH-1:0] m_axis_read_data_tdata_reg = {AXIS_DATA_WIDTH{1'b0}};
|
|
reg [AXIS_KEEP_WIDTH-1:0] m_axis_read_data_tkeep_reg = {AXIS_KEEP_WIDTH{1'b0}};
|
|
reg m_axis_read_data_tvalid_reg = 1'b0;
|
|
reg m_axis_read_data_tlast_reg = 1'b0;
|
|
reg [AXIS_ID_WIDTH-1:0] m_axis_read_data_tid_reg = {AXIS_ID_WIDTH{1'b0}};
|
|
reg [AXIS_DEST_WIDTH-1:0] m_axis_read_data_tdest_reg = {AXIS_DEST_WIDTH{1'b0}};
|
|
reg [AXIS_USER_WIDTH-1:0] m_axis_read_data_tuser_reg = {AXIS_USER_WIDTH{1'b0}};
|
|
|
|
reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_fifo_wr_ptr_reg = 0;
|
|
reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_fifo_rd_ptr_reg = 0;
|
|
reg out_fifo_half_full_reg = 1'b0;
|
|
|
|
wire out_fifo_full = out_fifo_wr_ptr_reg == (out_fifo_rd_ptr_reg ^ {1'b1, {OUTPUT_FIFO_ADDR_WIDTH{1'b0}}});
|
|
wire out_fifo_empty = out_fifo_wr_ptr_reg == out_fifo_rd_ptr_reg;
|
|
|
|
(* ram_style = "distributed" *)
|
|
reg [AXIS_DATA_WIDTH-1:0] out_fifo_tdata[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
|
|
(* ram_style = "distributed" *)
|
|
reg [AXIS_KEEP_WIDTH-1:0] out_fifo_tkeep[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
|
|
(* ram_style = "distributed" *)
|
|
reg out_fifo_tlast[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
|
|
(* ram_style = "distributed" *)
|
|
reg [AXIS_ID_WIDTH-1:0] out_fifo_tid[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
|
|
(* ram_style = "distributed" *)
|
|
reg [AXIS_DEST_WIDTH-1:0] out_fifo_tdest[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
|
|
(* ram_style = "distributed" *)
|
|
reg [AXIS_USER_WIDTH-1:0] out_fifo_tuser[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
|
|
|
|
assign m_axis_read_data_tready_int = !out_fifo_half_full_reg;
|
|
|
|
assign m_axis_read_data_tdata = m_axis_read_data_tdata_reg;
|
|
assign m_axis_read_data_tkeep = AXIS_KEEP_ENABLE ? m_axis_read_data_tkeep_reg : {AXIS_KEEP_WIDTH{1'b1}};
|
|
assign m_axis_read_data_tvalid = m_axis_read_data_tvalid_reg;
|
|
assign m_axis_read_data_tlast = AXIS_LAST_ENABLE ? m_axis_read_data_tlast_reg : 1'b1;
|
|
assign m_axis_read_data_tid = AXIS_ID_ENABLE ? m_axis_read_data_tid_reg : {AXIS_ID_WIDTH{1'b0}};
|
|
assign m_axis_read_data_tdest = AXIS_DEST_ENABLE ? m_axis_read_data_tdest_reg : {AXIS_DEST_WIDTH{1'b0}};
|
|
assign m_axis_read_data_tuser = AXIS_USER_ENABLE ? m_axis_read_data_tuser_reg : {AXIS_USER_WIDTH{1'b0}};
|
|
|
|
always @(posedge clk) begin
|
|
m_axis_read_data_tvalid_reg <= m_axis_read_data_tvalid_reg && !m_axis_read_data_tready;
|
|
|
|
out_fifo_half_full_reg <= $unsigned(out_fifo_wr_ptr_reg - out_fifo_rd_ptr_reg) >= 2**(OUTPUT_FIFO_ADDR_WIDTH-1);
|
|
|
|
if (!out_fifo_full && m_axis_read_data_tvalid_int) begin
|
|
out_fifo_tdata[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_read_data_tdata_int;
|
|
out_fifo_tkeep[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_read_data_tkeep_int;
|
|
out_fifo_tlast[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_read_data_tlast_int;
|
|
out_fifo_tid[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_read_data_tid_int;
|
|
out_fifo_tdest[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_read_data_tdest_int;
|
|
out_fifo_tuser[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_read_data_tuser_int;
|
|
out_fifo_wr_ptr_reg <= out_fifo_wr_ptr_reg + 1;
|
|
end
|
|
|
|
if (!out_fifo_empty && (!m_axis_read_data_tvalid_reg || m_axis_read_data_tready)) begin
|
|
m_axis_read_data_tdata_reg <= out_fifo_tdata[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
|
|
m_axis_read_data_tkeep_reg <= out_fifo_tkeep[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
|
|
m_axis_read_data_tvalid_reg <= 1'b1;
|
|
m_axis_read_data_tlast_reg <= out_fifo_tlast[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
|
|
m_axis_read_data_tid_reg <= out_fifo_tid[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
|
|
m_axis_read_data_tdest_reg <= out_fifo_tdest[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
|
|
m_axis_read_data_tuser_reg <= out_fifo_tuser[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
|
|
out_fifo_rd_ptr_reg <= out_fifo_rd_ptr_reg + 1;
|
|
end
|
|
|
|
if (rst) begin
|
|
out_fifo_wr_ptr_reg <= 0;
|
|
out_fifo_rd_ptr_reg <= 0;
|
|
m_axis_read_data_tvalid_reg <= 1'b0;
|
|
end
|
|
end
|
|
|
|
endmodule
|