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559 lines
22 KiB
Verilog
559 lines
22 KiB
Verilog
// SPDX-License-Identifier: BSD-2-Clause-Views
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/*
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* Copyright (c) 2022-2023 The Regents of the University of California
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* NIC port
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*/
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module mqnic_port #
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(
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// PTP configuration
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parameter PTP_TS_WIDTH = 96,
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// Interface configuration
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parameter PTP_TS_ENABLE = 1,
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parameter TX_CPL_ENABLE = 1,
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parameter TX_CPL_FIFO_DEPTH = 32,
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parameter TX_TAG_WIDTH = 16,
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parameter MAX_TX_SIZE = 9214,
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parameter MAX_RX_SIZE = 9214,
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// Application block configuration
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parameter APP_AXIS_DIRECT_ENABLE = 1,
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parameter APP_AXIS_SYNC_ENABLE = 1,
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// Register interface configuration
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parameter REG_ADDR_WIDTH = 7,
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parameter REG_DATA_WIDTH = 32,
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parameter REG_STRB_WIDTH = (REG_DATA_WIDTH/8),
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parameter RB_BASE_ADDR = 0,
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parameter RB_NEXT_PTR = 0,
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// Streaming interface configuration
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parameter AXIS_DATA_WIDTH = 256,
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parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8,
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parameter AXIS_TX_USER_WIDTH = TX_TAG_WIDTH + 1,
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parameter AXIS_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1,
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parameter AXIS_RX_USE_READY = 0,
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parameter AXIS_TX_PIPELINE = 0,
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parameter AXIS_TX_FIFO_PIPELINE = 2,
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parameter AXIS_TX_TS_PIPELINE = 0,
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parameter AXIS_RX_PIPELINE = 0,
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parameter AXIS_RX_FIFO_PIPELINE = 2,
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parameter AXIS_SYNC_DATA_WIDTH = AXIS_DATA_WIDTH,
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parameter AXIS_SYNC_KEEP_WIDTH = AXIS_SYNC_DATA_WIDTH/8,
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parameter AXIS_SYNC_TX_USER_WIDTH = AXIS_TX_USER_WIDTH,
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parameter AXIS_SYNC_RX_USER_WIDTH = AXIS_RX_USER_WIDTH
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)
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(
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input wire clk,
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input wire rst,
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/*
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* Control register interface
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*/
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input wire [REG_ADDR_WIDTH-1:0] ctrl_reg_wr_addr,
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input wire [REG_DATA_WIDTH-1:0] ctrl_reg_wr_data,
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input wire [REG_STRB_WIDTH-1:0] ctrl_reg_wr_strb,
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input wire ctrl_reg_wr_en,
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output wire ctrl_reg_wr_wait,
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output wire ctrl_reg_wr_ack,
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input wire [REG_ADDR_WIDTH-1:0] ctrl_reg_rd_addr,
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input wire ctrl_reg_rd_en,
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output wire [REG_DATA_WIDTH-1:0] ctrl_reg_rd_data,
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output wire ctrl_reg_rd_wait,
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output wire ctrl_reg_rd_ack,
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/*
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* Transmit data from interface FIFO
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*/
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input wire [AXIS_SYNC_DATA_WIDTH-1:0] s_axis_if_tx_tdata,
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input wire [AXIS_SYNC_KEEP_WIDTH-1:0] s_axis_if_tx_tkeep,
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input wire s_axis_if_tx_tvalid,
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output wire s_axis_if_tx_tready,
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input wire s_axis_if_tx_tlast,
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input wire [AXIS_SYNC_TX_USER_WIDTH-1:0] s_axis_if_tx_tuser,
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output wire [PTP_TS_WIDTH-1:0] m_axis_if_tx_cpl_ts,
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output wire [TX_TAG_WIDTH-1:0] m_axis_if_tx_cpl_tag,
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output wire m_axis_if_tx_cpl_valid,
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input wire m_axis_if_tx_cpl_ready,
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/*
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* Receive data to interface FIFO
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*/
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output wire [AXIS_SYNC_DATA_WIDTH-1:0] m_axis_if_rx_tdata,
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output wire [AXIS_SYNC_KEEP_WIDTH-1:0] m_axis_if_rx_tkeep,
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output wire m_axis_if_rx_tvalid,
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input wire m_axis_if_rx_tready,
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output wire m_axis_if_rx_tlast,
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output wire [AXIS_SYNC_RX_USER_WIDTH-1:0] m_axis_if_rx_tuser,
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/*
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* Application section datapath interface (synchronous MAC interface)
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*/
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output wire [AXIS_SYNC_DATA_WIDTH-1:0] m_axis_app_sync_tx_tdata,
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output wire [AXIS_SYNC_KEEP_WIDTH-1:0] m_axis_app_sync_tx_tkeep,
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output wire m_axis_app_sync_tx_tvalid,
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input wire m_axis_app_sync_tx_tready,
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output wire m_axis_app_sync_tx_tlast,
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output wire [AXIS_SYNC_TX_USER_WIDTH-1:0] m_axis_app_sync_tx_tuser,
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input wire [AXIS_SYNC_DATA_WIDTH-1:0] s_axis_app_sync_tx_tdata,
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input wire [AXIS_SYNC_KEEP_WIDTH-1:0] s_axis_app_sync_tx_tkeep,
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input wire s_axis_app_sync_tx_tvalid,
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output wire s_axis_app_sync_tx_tready,
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input wire s_axis_app_sync_tx_tlast,
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input wire [AXIS_SYNC_TX_USER_WIDTH-1:0] s_axis_app_sync_tx_tuser,
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output wire [PTP_TS_WIDTH-1:0] m_axis_app_sync_tx_cpl_ts,
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output wire [TX_TAG_WIDTH-1:0] m_axis_app_sync_tx_cpl_tag,
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output wire m_axis_app_sync_tx_cpl_valid,
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input wire m_axis_app_sync_tx_cpl_ready,
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input wire [PTP_TS_WIDTH-1:0] s_axis_app_sync_tx_cpl_ts,
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input wire [TX_TAG_WIDTH-1:0] s_axis_app_sync_tx_cpl_tag,
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input wire s_axis_app_sync_tx_cpl_valid,
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output wire s_axis_app_sync_tx_cpl_ready,
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output wire [AXIS_SYNC_DATA_WIDTH-1:0] m_axis_app_sync_rx_tdata,
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output wire [AXIS_SYNC_KEEP_WIDTH-1:0] m_axis_app_sync_rx_tkeep,
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output wire m_axis_app_sync_rx_tvalid,
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input wire m_axis_app_sync_rx_tready,
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output wire m_axis_app_sync_rx_tlast,
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output wire [AXIS_SYNC_RX_USER_WIDTH-1:0] m_axis_app_sync_rx_tuser,
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input wire [AXIS_SYNC_DATA_WIDTH-1:0] s_axis_app_sync_rx_tdata,
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input wire [AXIS_SYNC_KEEP_WIDTH-1:0] s_axis_app_sync_rx_tkeep,
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input wire s_axis_app_sync_rx_tvalid,
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output wire s_axis_app_sync_rx_tready,
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input wire s_axis_app_sync_rx_tlast,
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input wire [AXIS_SYNC_RX_USER_WIDTH-1:0] s_axis_app_sync_rx_tuser,
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/*
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* Application section datapath interface (direct MAC interface)
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*/
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output wire [AXIS_DATA_WIDTH-1:0] m_axis_app_direct_tx_tdata,
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output wire [AXIS_KEEP_WIDTH-1:0] m_axis_app_direct_tx_tkeep,
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output wire m_axis_app_direct_tx_tvalid,
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input wire m_axis_app_direct_tx_tready,
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output wire m_axis_app_direct_tx_tlast,
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output wire [AXIS_TX_USER_WIDTH-1:0] m_axis_app_direct_tx_tuser,
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input wire [AXIS_DATA_WIDTH-1:0] s_axis_app_direct_tx_tdata,
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input wire [AXIS_KEEP_WIDTH-1:0] s_axis_app_direct_tx_tkeep,
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input wire s_axis_app_direct_tx_tvalid,
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output wire s_axis_app_direct_tx_tready,
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input wire s_axis_app_direct_tx_tlast,
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input wire [AXIS_TX_USER_WIDTH-1:0] s_axis_app_direct_tx_tuser,
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output wire [PTP_TS_WIDTH-1:0] m_axis_app_direct_tx_cpl_ts,
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output wire [TX_TAG_WIDTH-1:0] m_axis_app_direct_tx_cpl_tag,
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output wire m_axis_app_direct_tx_cpl_valid,
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input wire m_axis_app_direct_tx_cpl_ready,
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input wire [PTP_TS_WIDTH-1:0] s_axis_app_direct_tx_cpl_ts,
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input wire [TX_TAG_WIDTH-1:0] s_axis_app_direct_tx_cpl_tag,
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input wire s_axis_app_direct_tx_cpl_valid,
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output wire s_axis_app_direct_tx_cpl_ready,
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output wire [AXIS_DATA_WIDTH-1:0] m_axis_app_direct_rx_tdata,
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output wire [AXIS_KEEP_WIDTH-1:0] m_axis_app_direct_rx_tkeep,
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output wire m_axis_app_direct_rx_tvalid,
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input wire m_axis_app_direct_rx_tready,
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output wire m_axis_app_direct_rx_tlast,
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output wire [AXIS_RX_USER_WIDTH-1:0] m_axis_app_direct_rx_tuser,
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input wire [AXIS_DATA_WIDTH-1:0] s_axis_app_direct_rx_tdata,
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input wire [AXIS_KEEP_WIDTH-1:0] s_axis_app_direct_rx_tkeep,
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input wire s_axis_app_direct_rx_tvalid,
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output wire s_axis_app_direct_rx_tready,
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input wire s_axis_app_direct_rx_tlast,
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input wire [AXIS_RX_USER_WIDTH-1:0] s_axis_app_direct_rx_tuser,
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/*
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* Transmit data output
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*/
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input wire tx_clk,
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input wire tx_rst,
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output wire [AXIS_DATA_WIDTH-1:0] m_axis_tx_tdata,
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output wire [AXIS_KEEP_WIDTH-1:0] m_axis_tx_tkeep,
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output wire m_axis_tx_tvalid,
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input wire m_axis_tx_tready,
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output wire m_axis_tx_tlast,
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output wire [AXIS_TX_USER_WIDTH-1:0] m_axis_tx_tuser,
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input wire [PTP_TS_WIDTH-1:0] s_axis_tx_cpl_ts,
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input wire [TX_TAG_WIDTH-1:0] s_axis_tx_cpl_tag,
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input wire s_axis_tx_cpl_valid,
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output wire s_axis_tx_cpl_ready,
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input wire tx_status,
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/*
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* Receive data input
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*/
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input wire rx_clk,
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input wire rx_rst,
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input wire [AXIS_DATA_WIDTH-1:0] s_axis_rx_tdata,
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input wire [AXIS_KEEP_WIDTH-1:0] s_axis_rx_tkeep,
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input wire s_axis_rx_tvalid,
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output wire s_axis_rx_tready,
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input wire s_axis_rx_tlast,
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input wire [AXIS_RX_USER_WIDTH-1:0] s_axis_rx_tuser,
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input wire rx_status
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);
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localparam RBB = RB_BASE_ADDR & {REG_ADDR_WIDTH{1'b1}};
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// check configuration
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initial begin
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if (REG_DATA_WIDTH != 32) begin
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$error("Error: Register interface width must be 32 (instance %m)");
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$finish;
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end
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if (REG_STRB_WIDTH * 8 != REG_DATA_WIDTH) begin
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$error("Error: Register interface requires byte (8-bit) granularity (instance %m)");
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$finish;
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end
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if (REG_ADDR_WIDTH < $clog2(64)) begin
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$error("Error: Register address width too narrow (instance %m)");
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$finish;
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end
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if (RB_NEXT_PTR >= RB_BASE_ADDR && RB_NEXT_PTR < RB_BASE_ADDR + 64) begin
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$error("Error: RB_NEXT_PTR overlaps block (instance %m)");
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$finish;
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end
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end
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// TX status
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reg tx_rst_sync_1_reg = 1'b0;
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reg tx_rst_sync_2_reg = 1'b0;
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reg tx_rst_sync_3_reg = 1'b0;
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reg tx_status_sync_1_reg = 1'b0;
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reg tx_status_sync_2_reg = 1'b0;
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reg tx_status_sync_3_reg = 1'b0;
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always @(posedge tx_clk or posedge tx_rst) begin
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if (tx_rst) begin
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tx_rst_sync_1_reg <= 1'b1;
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tx_status_sync_1_reg <= 1'b0;
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end else begin
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tx_rst_sync_1_reg <= 1'b0;
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tx_status_sync_1_reg <= tx_status;
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end
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end
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always @(posedge clk) begin
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tx_rst_sync_2_reg <= tx_rst_sync_1_reg;
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tx_rst_sync_3_reg <= tx_rst_sync_2_reg;
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tx_status_sync_2_reg <= tx_status_sync_1_reg;
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tx_status_sync_3_reg <= tx_status_sync_2_reg;
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end
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// RX status
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reg rx_rst_sync_1_reg = 1'b0;
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reg rx_rst_sync_2_reg = 1'b0;
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reg rx_rst_sync_3_reg = 1'b0;
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reg rx_status_sync_1_reg = 1'b0;
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reg rx_status_sync_2_reg = 1'b0;
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reg rx_status_sync_3_reg = 1'b0;
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always @(posedge rx_clk or posedge rx_rst) begin
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if (rx_rst) begin
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rx_rst_sync_1_reg <= 1'b1;
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rx_status_sync_1_reg <= 1'b0;
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end else begin
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rx_rst_sync_1_reg <= 1'b0;
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rx_status_sync_1_reg <= rx_status;
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end
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end
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always @(posedge clk) begin
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rx_rst_sync_2_reg <= rx_rst_sync_1_reg;
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rx_rst_sync_3_reg <= rx_rst_sync_2_reg;
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rx_status_sync_2_reg <= rx_status_sync_1_reg;
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rx_status_sync_3_reg <= rx_status_sync_2_reg;
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end
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// control registers
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reg ctrl_reg_wr_ack_reg = 1'b0;
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reg [REG_DATA_WIDTH-1:0] ctrl_reg_rd_data_reg = {REG_DATA_WIDTH{1'b0}};
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reg ctrl_reg_rd_ack_reg = 1'b0;
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assign ctrl_reg_wr_wait = 1'b0;
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assign ctrl_reg_wr_ack = ctrl_reg_wr_ack_reg;
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assign ctrl_reg_rd_data = ctrl_reg_rd_data_reg;
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assign ctrl_reg_rd_wait = 1'b0;
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assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_reg;
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always @(posedge clk) begin
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ctrl_reg_wr_ack_reg <= 1'b0;
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ctrl_reg_rd_data_reg <= {REG_DATA_WIDTH{1'b0}};
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ctrl_reg_rd_ack_reg <= 1'b0;
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if (ctrl_reg_wr_en && !ctrl_reg_wr_ack_reg) begin
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// write operation
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ctrl_reg_wr_ack_reg <= 1'b1;
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case ({ctrl_reg_wr_addr >> 2, 2'b00})
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// Port control
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default: ctrl_reg_wr_ack_reg <= 1'b0;
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endcase
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end
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if (ctrl_reg_rd_en && !ctrl_reg_rd_ack_reg) begin
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// read operation
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ctrl_reg_rd_ack_reg <= 1'b1;
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case ({ctrl_reg_rd_addr >> 2, 2'b00})
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// Port
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RBB+8'h00: ctrl_reg_rd_data_reg <= 32'h0000C002; // Port: Type
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RBB+8'h04: ctrl_reg_rd_data_reg <= 32'h00000200; // Port: Version
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RBB+8'h08: ctrl_reg_rd_data_reg <= RB_NEXT_PTR; // Port: Next header
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RBB+8'h0C: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h10; // Port: Offset
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// Port control
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RBB+8'h10: ctrl_reg_rd_data_reg <= 32'h0000C003; // Port ctrl: Type
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RBB+8'h14: ctrl_reg_rd_data_reg <= 32'h00000200; // Port ctrl: Version
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RBB+8'h18: ctrl_reg_rd_data_reg <= 0; // Port ctrl: Next header
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RBB+8'h1C: begin
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// Port ctrl: features
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end
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RBB+8'h20: begin
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// Port ctrl: TX status
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ctrl_reg_rd_data_reg[0] <= tx_status_sync_3_reg;
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ctrl_reg_rd_data_reg[1] <= tx_rst_sync_3_reg;
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end
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RBB+8'h24: begin
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// Port ctrl: RX status
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ctrl_reg_rd_data_reg[0] <= rx_status_sync_3_reg;
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ctrl_reg_rd_data_reg[1] <= rx_rst_sync_3_reg;
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end
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default: ctrl_reg_rd_ack_reg <= 1'b0;
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endcase
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end
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if (rst) begin
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ctrl_reg_wr_ack_reg <= 1'b0;
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ctrl_reg_rd_ack_reg <= 1'b0;
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end
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end
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mqnic_port_tx #(
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// PTP configuration
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.PTP_TS_WIDTH(PTP_TS_WIDTH),
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// Interface configuration
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.PTP_TS_ENABLE(PTP_TS_ENABLE),
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.TX_CPL_ENABLE(TX_CPL_ENABLE),
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.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
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.TX_TAG_WIDTH(TX_TAG_WIDTH),
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.MAX_TX_SIZE(MAX_TX_SIZE),
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// Application block configuration
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.APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE),
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.APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE),
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// Streaming interface configuration
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.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
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.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
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.AXIS_TX_USER_WIDTH(AXIS_TX_USER_WIDTH),
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.AXIS_TX_PIPELINE(AXIS_TX_PIPELINE),
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.AXIS_TX_FIFO_PIPELINE(AXIS_TX_FIFO_PIPELINE),
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.AXIS_TX_TS_PIPELINE(AXIS_TX_TS_PIPELINE),
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.AXIS_SYNC_DATA_WIDTH(AXIS_SYNC_DATA_WIDTH),
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.AXIS_SYNC_KEEP_WIDTH(AXIS_SYNC_KEEP_WIDTH),
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.AXIS_SYNC_TX_USER_WIDTH(AXIS_SYNC_TX_USER_WIDTH)
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)
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port_tx_inst (
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.clk(clk),
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.rst(rst),
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/*
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* Transmit data from interface FIFO
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*/
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.s_axis_if_tx_tdata(s_axis_if_tx_tdata),
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.s_axis_if_tx_tkeep(s_axis_if_tx_tkeep),
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.s_axis_if_tx_tvalid(s_axis_if_tx_tvalid),
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.s_axis_if_tx_tready(s_axis_if_tx_tready),
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.s_axis_if_tx_tlast(s_axis_if_tx_tlast),
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.s_axis_if_tx_tuser(s_axis_if_tx_tuser),
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.m_axis_if_tx_cpl_ts(m_axis_if_tx_cpl_ts),
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.m_axis_if_tx_cpl_tag(m_axis_if_tx_cpl_tag),
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.m_axis_if_tx_cpl_valid(m_axis_if_tx_cpl_valid),
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.m_axis_if_tx_cpl_ready(m_axis_if_tx_cpl_ready),
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/*
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* Application section datapath interface (synchronous MAC interface)
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*/
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.m_axis_app_sync_tx_tdata(m_axis_app_sync_tx_tdata),
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.m_axis_app_sync_tx_tkeep(m_axis_app_sync_tx_tkeep),
|
|
.m_axis_app_sync_tx_tvalid(m_axis_app_sync_tx_tvalid),
|
|
.m_axis_app_sync_tx_tready(m_axis_app_sync_tx_tready),
|
|
.m_axis_app_sync_tx_tlast(m_axis_app_sync_tx_tlast),
|
|
.m_axis_app_sync_tx_tuser(m_axis_app_sync_tx_tuser),
|
|
|
|
.s_axis_app_sync_tx_tdata(s_axis_app_sync_tx_tdata),
|
|
.s_axis_app_sync_tx_tkeep(s_axis_app_sync_tx_tkeep),
|
|
.s_axis_app_sync_tx_tvalid(s_axis_app_sync_tx_tvalid),
|
|
.s_axis_app_sync_tx_tready(s_axis_app_sync_tx_tready),
|
|
.s_axis_app_sync_tx_tlast(s_axis_app_sync_tx_tlast),
|
|
.s_axis_app_sync_tx_tuser(s_axis_app_sync_tx_tuser),
|
|
|
|
.m_axis_app_sync_tx_cpl_ts(m_axis_app_sync_tx_cpl_ts),
|
|
.m_axis_app_sync_tx_cpl_tag(m_axis_app_sync_tx_cpl_tag),
|
|
.m_axis_app_sync_tx_cpl_valid(m_axis_app_sync_tx_cpl_valid),
|
|
.m_axis_app_sync_tx_cpl_ready(m_axis_app_sync_tx_cpl_ready),
|
|
|
|
.s_axis_app_sync_tx_cpl_ts(s_axis_app_sync_tx_cpl_ts),
|
|
.s_axis_app_sync_tx_cpl_tag(s_axis_app_sync_tx_cpl_tag),
|
|
.s_axis_app_sync_tx_cpl_valid(s_axis_app_sync_tx_cpl_valid),
|
|
.s_axis_app_sync_tx_cpl_ready(s_axis_app_sync_tx_cpl_ready),
|
|
|
|
/*
|
|
* Application section datapath interface (direct MAC interface)
|
|
*/
|
|
.m_axis_app_direct_tx_tdata(m_axis_app_direct_tx_tdata),
|
|
.m_axis_app_direct_tx_tkeep(m_axis_app_direct_tx_tkeep),
|
|
.m_axis_app_direct_tx_tvalid(m_axis_app_direct_tx_tvalid),
|
|
.m_axis_app_direct_tx_tready(m_axis_app_direct_tx_tready),
|
|
.m_axis_app_direct_tx_tlast(m_axis_app_direct_tx_tlast),
|
|
.m_axis_app_direct_tx_tuser(m_axis_app_direct_tx_tuser),
|
|
|
|
.s_axis_app_direct_tx_tdata(s_axis_app_direct_tx_tdata),
|
|
.s_axis_app_direct_tx_tkeep(s_axis_app_direct_tx_tkeep),
|
|
.s_axis_app_direct_tx_tvalid(s_axis_app_direct_tx_tvalid),
|
|
.s_axis_app_direct_tx_tready(s_axis_app_direct_tx_tready),
|
|
.s_axis_app_direct_tx_tlast(s_axis_app_direct_tx_tlast),
|
|
.s_axis_app_direct_tx_tuser(s_axis_app_direct_tx_tuser),
|
|
|
|
.m_axis_app_direct_tx_cpl_ts(m_axis_app_direct_tx_cpl_ts),
|
|
.m_axis_app_direct_tx_cpl_tag(m_axis_app_direct_tx_cpl_tag),
|
|
.m_axis_app_direct_tx_cpl_valid(m_axis_app_direct_tx_cpl_valid),
|
|
.m_axis_app_direct_tx_cpl_ready(m_axis_app_direct_tx_cpl_ready),
|
|
|
|
.s_axis_app_direct_tx_cpl_ts(s_axis_app_direct_tx_cpl_ts),
|
|
.s_axis_app_direct_tx_cpl_tag(s_axis_app_direct_tx_cpl_tag),
|
|
.s_axis_app_direct_tx_cpl_valid(s_axis_app_direct_tx_cpl_valid),
|
|
.s_axis_app_direct_tx_cpl_ready(s_axis_app_direct_tx_cpl_ready),
|
|
|
|
/*
|
|
* Transmit data output
|
|
*/
|
|
.tx_clk(tx_clk),
|
|
.tx_rst(tx_rst),
|
|
|
|
.m_axis_tx_tdata(m_axis_tx_tdata),
|
|
.m_axis_tx_tkeep(m_axis_tx_tkeep),
|
|
.m_axis_tx_tvalid(m_axis_tx_tvalid),
|
|
.m_axis_tx_tready(m_axis_tx_tready),
|
|
.m_axis_tx_tlast(m_axis_tx_tlast),
|
|
.m_axis_tx_tuser(m_axis_tx_tuser),
|
|
|
|
.s_axis_tx_cpl_ts(s_axis_tx_cpl_ts),
|
|
.s_axis_tx_cpl_tag(s_axis_tx_cpl_tag),
|
|
.s_axis_tx_cpl_valid(s_axis_tx_cpl_valid),
|
|
.s_axis_tx_cpl_ready(s_axis_tx_cpl_ready)
|
|
);
|
|
|
|
mqnic_port_rx #(
|
|
// PTP configuration
|
|
.PTP_TS_WIDTH(PTP_TS_WIDTH),
|
|
|
|
// Interface configuration
|
|
.PTP_TS_ENABLE(PTP_TS_ENABLE),
|
|
.MAX_RX_SIZE(MAX_RX_SIZE),
|
|
|
|
// Application block configuration
|
|
.APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE),
|
|
.APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE),
|
|
|
|
// Streaming interface configuration
|
|
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
|
|
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
|
|
.AXIS_RX_USER_WIDTH(AXIS_RX_USER_WIDTH),
|
|
.AXIS_RX_USE_READY(AXIS_RX_USE_READY),
|
|
.AXIS_RX_PIPELINE(AXIS_RX_PIPELINE),
|
|
.AXIS_RX_FIFO_PIPELINE(AXIS_RX_FIFO_PIPELINE),
|
|
.AXIS_SYNC_DATA_WIDTH(AXIS_SYNC_DATA_WIDTH),
|
|
.AXIS_SYNC_KEEP_WIDTH(AXIS_SYNC_KEEP_WIDTH),
|
|
.AXIS_SYNC_RX_USER_WIDTH(AXIS_SYNC_RX_USER_WIDTH)
|
|
)
|
|
port_rx_inst (
|
|
.clk(clk),
|
|
.rst(rst),
|
|
|
|
/*
|
|
* Receive data to interface FIFO
|
|
*/
|
|
.m_axis_if_rx_tdata(m_axis_if_rx_tdata),
|
|
.m_axis_if_rx_tkeep(m_axis_if_rx_tkeep),
|
|
.m_axis_if_rx_tvalid(m_axis_if_rx_tvalid),
|
|
.m_axis_if_rx_tready(m_axis_if_rx_tready),
|
|
.m_axis_if_rx_tlast(m_axis_if_rx_tlast),
|
|
.m_axis_if_rx_tuser(m_axis_if_rx_tuser),
|
|
|
|
/*
|
|
* Application section datapath interface (synchronous MAC interface)
|
|
*/
|
|
.m_axis_app_sync_rx_tdata(m_axis_app_sync_rx_tdata),
|
|
.m_axis_app_sync_rx_tkeep(m_axis_app_sync_rx_tkeep),
|
|
.m_axis_app_sync_rx_tvalid(m_axis_app_sync_rx_tvalid),
|
|
.m_axis_app_sync_rx_tready(m_axis_app_sync_rx_tready),
|
|
.m_axis_app_sync_rx_tlast(m_axis_app_sync_rx_tlast),
|
|
.m_axis_app_sync_rx_tuser(m_axis_app_sync_rx_tuser),
|
|
|
|
.s_axis_app_sync_rx_tdata(s_axis_app_sync_rx_tdata),
|
|
.s_axis_app_sync_rx_tkeep(s_axis_app_sync_rx_tkeep),
|
|
.s_axis_app_sync_rx_tvalid(s_axis_app_sync_rx_tvalid),
|
|
.s_axis_app_sync_rx_tready(s_axis_app_sync_rx_tready),
|
|
.s_axis_app_sync_rx_tlast(s_axis_app_sync_rx_tlast),
|
|
.s_axis_app_sync_rx_tuser(s_axis_app_sync_rx_tuser),
|
|
|
|
/*
|
|
* Application section datapath interface (direct MAC interface)
|
|
*/
|
|
.m_axis_app_direct_rx_tdata(m_axis_app_direct_rx_tdata),
|
|
.m_axis_app_direct_rx_tkeep(m_axis_app_direct_rx_tkeep),
|
|
.m_axis_app_direct_rx_tvalid(m_axis_app_direct_rx_tvalid),
|
|
.m_axis_app_direct_rx_tready(m_axis_app_direct_rx_tready),
|
|
.m_axis_app_direct_rx_tlast(m_axis_app_direct_rx_tlast),
|
|
.m_axis_app_direct_rx_tuser(m_axis_app_direct_rx_tuser),
|
|
|
|
.s_axis_app_direct_rx_tdata(s_axis_app_direct_rx_tdata),
|
|
.s_axis_app_direct_rx_tkeep(s_axis_app_direct_rx_tkeep),
|
|
.s_axis_app_direct_rx_tvalid(s_axis_app_direct_rx_tvalid),
|
|
.s_axis_app_direct_rx_tready(s_axis_app_direct_rx_tready),
|
|
.s_axis_app_direct_rx_tlast(s_axis_app_direct_rx_tlast),
|
|
.s_axis_app_direct_rx_tuser(s_axis_app_direct_rx_tuser),
|
|
|
|
/*
|
|
* Receive data input
|
|
*/
|
|
.rx_clk(rx_clk),
|
|
.rx_rst(rx_rst),
|
|
|
|
.s_axis_rx_tdata(s_axis_rx_tdata),
|
|
.s_axis_rx_tkeep(s_axis_rx_tkeep),
|
|
.s_axis_rx_tvalid(s_axis_rx_tvalid),
|
|
.s_axis_rx_tready(s_axis_rx_tready),
|
|
.s_axis_rx_tlast(s_axis_rx_tlast),
|
|
.s_axis_rx_tuser(s_axis_rx_tuser)
|
|
);
|
|
|
|
endmodule
|
|
|
|
`resetall
|