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575 lines
20 KiB
Verilog
575 lines
20 KiB
Verilog
// SPDX-License-Identifier: BSD-2-Clause-Views
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/*
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* Copyright (c) 2019-2023 The Regents of the University of California
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* TDMA BER module
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*/
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module tdma_ber_ch #
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(
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// Timeslot index width
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parameter INDEX_WIDTH = 6,
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// Slice index width
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parameter SLICE_WIDTH = 5,
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// Width of AXI lite data bus in bits
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parameter AXIL_DATA_WIDTH = 32,
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// Width of AXI lite address bus in bits
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parameter AXIL_ADDR_WIDTH = INDEX_WIDTH+4,
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// Width of AXI lite wstrb (width of data bus in words)
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parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8),
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// pipeline stages on PHY interface ports
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parameter PHY_PIPELINE = 0
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)
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(
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input wire clk,
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input wire rst,
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/*
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* PHY connections
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*/
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input wire phy_tx_clk,
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input wire phy_rx_clk,
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input wire [6:0] phy_rx_error_count,
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output wire phy_tx_prbs31_enable,
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output wire phy_rx_prbs31_enable,
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/*
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* AXI-Lite slave interface
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*/
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input wire [AXIL_ADDR_WIDTH-1:0] s_axil_awaddr,
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input wire [2:0] s_axil_awprot,
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input wire s_axil_awvalid,
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output wire s_axil_awready,
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input wire [AXIL_DATA_WIDTH-1:0] s_axil_wdata,
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input wire [AXIL_STRB_WIDTH-1:0] s_axil_wstrb,
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input wire s_axil_wvalid,
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output wire s_axil_wready,
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output wire [1:0] s_axil_bresp,
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output wire s_axil_bvalid,
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input wire s_axil_bready,
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input wire [AXIL_ADDR_WIDTH-1:0] s_axil_araddr,
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input wire [2:0] s_axil_arprot,
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input wire s_axil_arvalid,
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output wire s_axil_arready,
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output wire [AXIL_DATA_WIDTH-1:0] s_axil_rdata,
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output wire [1:0] s_axil_rresp,
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output wire s_axil_rvalid,
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input wire s_axil_rready,
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/*
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* TDMA schedule
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*/
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input wire [INDEX_WIDTH-1:0] tdma_timeslot_index,
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input wire tdma_timeslot_start,
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input wire tdma_timeslot_active
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);
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parameter VALID_ADDR_WIDTH = AXIL_ADDR_WIDTH - $clog2(AXIL_STRB_WIDTH);
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parameter WORD_WIDTH = AXIL_STRB_WIDTH;
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parameter WORD_SIZE = AXIL_DATA_WIDTH/WORD_WIDTH;
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// check configuration
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initial begin
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if (AXIL_ADDR_WIDTH < INDEX_WIDTH+4) begin
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$error("Error: AXI address width too narrow (instance %m)");
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$finish;
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end
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if (AXIL_DATA_WIDTH != 32) begin
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$error("Error: AXI data width must be 32 (instance %m)");
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$finish;
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end
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if (AXIL_STRB_WIDTH * 8 != AXIL_DATA_WIDTH) begin
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$error("Error: Interface requires byte (8-bit) granularity (instance %m)");
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$finish;
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end
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end
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reg tx_prbs31_enable_reg = 1'b0, tx_prbs31_enable_next;
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reg rx_prbs31_enable_reg = 1'b0, rx_prbs31_enable_next;
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// PHY TX BER interface
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reg phy_tx_prbs31_enable_reg = 1'b0;
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reg [PHY_PIPELINE-1:0] phy_tx_prbs31_enable_pipe_reg = 0;
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always @(posedge phy_tx_clk) begin
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phy_tx_prbs31_enable_reg <= tx_prbs31_enable_reg;
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phy_tx_prbs31_enable_pipe_reg <= {phy_tx_prbs31_enable_pipe_reg, phy_tx_prbs31_enable_reg};
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end
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assign phy_tx_prbs31_enable = PHY_PIPELINE ? phy_tx_prbs31_enable_pipe_reg[PHY_PIPELINE-1] : phy_tx_prbs31_enable_reg;
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// PHY RX BER interface
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reg phy_rx_prbs31_enable_reg = 1'b0;
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reg [PHY_PIPELINE-1:0] phy_rx_prbs31_enable_pipe_reg = 0;
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reg [PHY_PIPELINE*7-1:0] phy_rx_error_count_pipe_reg = 0;
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// accumulate errors, dump every 16 cycles
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reg [10:0] phy_rx_error_count_reg = 0;
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reg [10:0] phy_rx_error_count_acc_reg = 0;
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reg [3:0] phy_rx_count_reg = 4'd0;
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reg phy_rx_flag_reg = 1'b0;
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always @(posedge phy_rx_clk) begin
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phy_rx_prbs31_enable_reg <= rx_prbs31_enable_reg;
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phy_rx_prbs31_enable_pipe_reg <= {phy_rx_prbs31_enable_pipe_reg, phy_rx_prbs31_enable_reg};
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phy_rx_error_count_pipe_reg <= {phy_rx_error_count_pipe_reg, phy_rx_error_count};
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phy_rx_count_reg <= phy_rx_count_reg + 1;
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if (phy_rx_count_reg == 0) begin
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phy_rx_error_count_reg <= phy_rx_error_count_acc_reg;
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phy_rx_error_count_acc_reg <= PHY_PIPELINE ? phy_rx_error_count_pipe_reg[(PHY_PIPELINE-1)*7 +: 7] : phy_rx_error_count;
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phy_rx_flag_reg <= !phy_rx_flag_reg;
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end else begin
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phy_rx_error_count_acc_reg <= phy_rx_error_count_acc_reg + (PHY_PIPELINE ? phy_rx_error_count_pipe_reg[(PHY_PIPELINE-1)*7 +: 7] : phy_rx_error_count);
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end
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end
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assign phy_rx_prbs31_enable = PHY_PIPELINE ? phy_rx_prbs31_enable_pipe_reg[PHY_PIPELINE-1] : phy_rx_prbs31_enable_reg;
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// synchronize dumped counts to control clock domain
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reg rx_flag_sync_reg_1 = 1'b0;
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reg rx_flag_sync_reg_2 = 1'b0;
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reg rx_flag_sync_reg_3 = 1'b0;
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always @(posedge clk) begin
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rx_flag_sync_reg_1 <= phy_rx_flag_reg;
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rx_flag_sync_reg_2 <= rx_flag_sync_reg_1;
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rx_flag_sync_reg_3 <= rx_flag_sync_reg_2;
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end
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reg [31:0] cycle_count_reg = 32'd0, cycle_count_next;
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reg [31:0] update_count_reg = 32'd0, update_count_next;
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reg [31:0] rx_error_count_reg = 32'd0, rx_error_count_next;
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reg [31:0] atomic_cycle_count_reg = 32'd0, atomic_cycle_count_next;
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reg [31:0] atomic_update_count_reg = 32'd0, atomic_update_count_next;
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reg [31:0] atomic_rx_error_count_reg = 32'd0, atomic_rx_error_count_next;
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reg accumulate_enable_reg = 1'b0, accumulate_enable_next;
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reg slice_enable_reg = 1'b0, slice_enable_next;
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reg [31:0] slice_time_reg = 0, slice_time_next;
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reg [31:0] slice_offset_reg = 0, slice_offset_next;
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reg [SLICE_WIDTH-1:0] slice_select_reg = 0, slice_select_next;
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reg error_count_mem_read_reg = 0;
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reg [31:0] error_count_mem_read_data_reg = 0;
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reg update_count_mem_read_reg = 0;
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reg [31:0] update_count_mem_read_data_reg = 0;
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reg [31:0] error_count_mem[(2**(INDEX_WIDTH+SLICE_WIDTH))-1:0];
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reg [31:0] update_count_mem[(2**(INDEX_WIDTH+SLICE_WIDTH))-1:0];
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integer i;
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initial begin
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for (i = 0; i < 2**(INDEX_WIDTH+SLICE_WIDTH); i = i + 1) begin
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error_count_mem[i] = 0;
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update_count_mem[i] = 0;
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end
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end
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reg [10:0] phy_rx_error_count_sync_reg = 0;
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reg phy_rx_error_count_sync_valid_reg = 1'b0;
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always @(posedge clk) begin
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phy_rx_error_count_sync_valid_reg <= 1'b0;
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if (rx_flag_sync_reg_2 ^ rx_flag_sync_reg_3) begin
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phy_rx_error_count_sync_reg <= phy_rx_error_count_reg;
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phy_rx_error_count_sync_valid_reg <= 1'b1;
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end
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end
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reg slice_running_reg = 1'b0;
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reg slice_active_reg = 1'b0;
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reg [31:0] slice_count_reg = 0;
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reg [SLICE_WIDTH-1:0] cur_slice_reg = 0;
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reg [1:0] accumulate_state_reg = 0;
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reg [31:0] rx_ts_update_count_read_reg = 0;
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reg [31:0] rx_ts_error_count_read_reg = 0;
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reg [31:0] rx_ts_update_count_reg = 0;
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reg [31:0] rx_ts_error_count_reg = 0;
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reg [INDEX_WIDTH+SLICE_WIDTH-1:0] index_reg = 0;
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always @(posedge clk) begin
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if (tdma_timeslot_start) begin
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slice_running_reg <= 1'b1;
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if (slice_offset_reg) begin
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slice_active_reg <= 1'b0;
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slice_count_reg <= slice_offset_reg;
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end else begin
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slice_active_reg <= 1'b1;
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slice_count_reg <= slice_time_reg;
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end
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cur_slice_reg <= 0;
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end else if (slice_count_reg > 0) begin
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slice_count_reg <= slice_count_reg - 1;
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end else begin
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slice_count_reg <= slice_time_reg;
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slice_active_reg <= slice_running_reg;
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if (slice_active_reg && slice_running_reg) begin
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cur_slice_reg <= cur_slice_reg + 1;
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slice_running_reg <= cur_slice_reg < {SLICE_WIDTH{1'b1}};
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slice_active_reg <= cur_slice_reg < {SLICE_WIDTH{1'b1}};
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end
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end
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case (accumulate_state_reg)
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2'd0: begin
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if (accumulate_enable_reg && tdma_timeslot_active && phy_rx_error_count_sync_valid_reg) begin
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if (slice_enable_reg) begin
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index_reg <= (tdma_timeslot_index << SLICE_WIDTH) + cur_slice_reg;
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if (slice_active_reg) begin
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accumulate_state_reg <= 2'd1;
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end
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end else begin
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index_reg <= (tdma_timeslot_index << SLICE_WIDTH);
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accumulate_state_reg <= 2'd1;
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end
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end
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end
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2'd1: begin
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rx_ts_update_count_read_reg <= update_count_mem[index_reg];
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rx_ts_error_count_read_reg <= error_count_mem[index_reg];
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accumulate_state_reg <= 2'd2;
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end
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2'd2: begin
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rx_ts_error_count_reg <= rx_ts_error_count_read_reg + phy_rx_error_count_sync_reg;
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rx_ts_update_count_reg <= rx_ts_update_count_read_reg + 1;
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// if ((rx_ts_error_count_reg + inc_reg) >> 32) begin
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// rx_ts_error_count_reg <= 32'hffffffff;
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// end else begin
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// rx_ts_error_count_reg <= rx_ts_error_count_reg + inc_reg;
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// end
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// if ((rx_ts_update_count_reg + 1) >> 32) begin
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// rx_ts_update_count_reg <= 32'hffffffff;
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// end else begin
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// rx_ts_update_count_reg <= rx_ts_update_count_reg + 1;
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// end
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accumulate_state_reg <= 2'd3;
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end
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2'd3: begin
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update_count_mem[index_reg] <= rx_ts_update_count_reg;
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error_count_mem[index_reg] <= rx_ts_error_count_reg;
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accumulate_state_reg <= 2'd0;
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end
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default: begin
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accumulate_state_reg <= 2'd0;
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end
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endcase
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end
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// control registers
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reg read_eligible;
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reg write_eligible;
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reg mem_wr_en;
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reg mem_rd_en;
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reg last_read_reg = 1'b0, last_read_next;
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reg s_axil_awready_reg = 1'b0, s_axil_awready_next;
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reg s_axil_wready_reg = 1'b0, s_axil_wready_next;
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reg s_axil_bvalid_reg = 1'b0, s_axil_bvalid_next;
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reg s_axil_arready_reg = 1'b0, s_axil_arready_next;
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reg [AXIL_DATA_WIDTH-1:0] s_axil_rdata_reg = {AXIL_DATA_WIDTH{1'b0}}, s_axil_rdata_next;
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reg s_axil_rvalid_reg = 1'b0, s_axil_rvalid_next;
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assign s_axil_awready = s_axil_awready_reg;
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assign s_axil_wready = s_axil_wready_reg;
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assign s_axil_bresp = 2'b00;
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assign s_axil_bvalid = s_axil_bvalid_reg;
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assign s_axil_arready = s_axil_arready_reg;
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assign s_axil_rdata = error_count_mem_read_reg ? error_count_mem_read_data_reg : (update_count_mem_read_reg ? update_count_mem_read_data_reg : s_axil_rdata_reg);
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assign s_axil_rresp = 2'b00;
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assign s_axil_rvalid = s_axil_rvalid_reg;
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wire [INDEX_WIDTH+SLICE_WIDTH-1:0] axil_ram_addr = ((mem_rd_en ? s_axil_araddr[INDEX_WIDTH+1+2-1:1+2] : s_axil_awaddr[INDEX_WIDTH+1+2-1:1+2]) << SLICE_WIDTH) | slice_select_reg;
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always @* begin
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mem_wr_en = 1'b0;
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mem_rd_en = 1'b0;
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last_read_next = last_read_reg;
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s_axil_awready_next = 1'b0;
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s_axil_wready_next = 1'b0;
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s_axil_bvalid_next = s_axil_bvalid_reg && !s_axil_bready;
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s_axil_arready_next = 1'b0;
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s_axil_rdata_next = s_axil_rdata_reg;
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s_axil_rvalid_next = s_axil_rvalid_reg && !s_axil_rready;
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cycle_count_next = cycle_count_reg + 1;
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update_count_next = update_count_reg;
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rx_error_count_next = rx_error_count_reg;
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if (phy_rx_error_count_sync_valid_reg) begin
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update_count_next = update_count_reg + 1;
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rx_error_count_next = phy_rx_error_count_sync_reg + rx_error_count_reg;
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end
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atomic_cycle_count_next = atomic_cycle_count_reg + 1;
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if (atomic_cycle_count_reg[31] && ~atomic_cycle_count_next[31]) begin
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atomic_cycle_count_next = 32'hffffffff;
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end
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atomic_update_count_next = atomic_update_count_reg;
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atomic_rx_error_count_next = atomic_rx_error_count_reg;
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if (phy_rx_error_count_sync_valid_reg) begin
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atomic_update_count_next = atomic_update_count_reg + 1;
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atomic_rx_error_count_next = phy_rx_error_count_sync_reg + atomic_rx_error_count_reg;
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// saturate
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if (atomic_update_count_reg[31] && ~atomic_update_count_next[31]) begin
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atomic_update_count_next = 32'hffffffff;
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end
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if (atomic_rx_error_count_reg[31] && ~atomic_rx_error_count_next[31]) begin
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atomic_rx_error_count_next = 32'hffffffff;
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end
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end
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accumulate_enable_next = accumulate_enable_reg;
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slice_enable_next = slice_enable_reg;
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slice_time_next = slice_time_reg;
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slice_offset_next = slice_offset_reg;
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slice_select_next = slice_select_reg;
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tx_prbs31_enable_next = tx_prbs31_enable_reg;
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rx_prbs31_enable_next = rx_prbs31_enable_reg;
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write_eligible = s_axil_awvalid && s_axil_wvalid && (!s_axil_bvalid || s_axil_bready) && (!s_axil_awready && !s_axil_wready);
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read_eligible = s_axil_arvalid && (!s_axil_rvalid || s_axil_rready) && (!s_axil_arready);
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if (write_eligible && (!read_eligible || last_read_reg)) begin
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last_read_next = 1'b0;
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s_axil_awready_next = 1'b1;
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s_axil_wready_next = 1'b1;
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s_axil_bvalid_next = 1'b1;
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if (s_axil_awaddr[INDEX_WIDTH+2+1+1-1]) begin
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mem_wr_en = 1'b1;
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end else begin
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case (s_axil_awaddr & ({AXIL_ADDR_WIDTH{1'b1}} << 2))
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16'h0000: begin
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// control
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tx_prbs31_enable_next = s_axil_wdata[0];
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rx_prbs31_enable_next = s_axil_wdata[1];
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end
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16'h0004: begin
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// cycle count
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cycle_count_next = 1;
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end
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16'h0008: begin
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// update count
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update_count_next = 0;
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end
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16'h000C: begin
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// error count
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rx_error_count_next = 0;
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end
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16'h0014: begin
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// cycle count
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atomic_cycle_count_next = 1;
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end
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16'h0018: begin
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// update count
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atomic_update_count_next = 0;
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end
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16'h001C: begin
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// error count
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atomic_rx_error_count_next = 0;
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end
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16'h0020: begin
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// control
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accumulate_enable_next = s_axil_wdata[0];
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slice_enable_next = s_axil_wdata[1];
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end
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16'h0024: begin
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// slice time
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slice_time_next = s_axil_wdata;
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end
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16'h0028: begin
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// slice offset
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slice_offset_next = s_axil_wdata;
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end
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16'h0030: begin
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// slice select
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slice_select_next = s_axil_wdata;
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end
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endcase
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end
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end else if (read_eligible) begin
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last_read_next = 1'b1;
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s_axil_arready_next = 1'b1;
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s_axil_rvalid_next = 1'b1;
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s_axil_rdata_next = {AXIL_DATA_WIDTH{1'b0}};
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if (s_axil_araddr[INDEX_WIDTH+2+1+1-1]) begin
|
|
mem_rd_en = 1'b1;
|
|
end else begin
|
|
case (s_axil_araddr & ({AXIL_ADDR_WIDTH{1'b1}} << 2))
|
|
16'h0000: begin
|
|
// control
|
|
s_axil_rdata_next[0] = tx_prbs31_enable_reg;
|
|
s_axil_rdata_next[1] = rx_prbs31_enable_reg;
|
|
end
|
|
16'h0004: begin
|
|
// cycle count
|
|
s_axil_rdata_next = cycle_count_reg;
|
|
end
|
|
16'h0008: begin
|
|
// update count
|
|
s_axil_rdata_next = update_count_reg;
|
|
end
|
|
16'h000C: begin
|
|
// error count
|
|
s_axil_rdata_next = rx_error_count_reg;
|
|
end
|
|
16'h0014: begin
|
|
// cycle count
|
|
s_axil_rdata_next = atomic_cycle_count_reg;
|
|
atomic_cycle_count_next = 1;
|
|
end
|
|
16'h0018: begin
|
|
// update count
|
|
s_axil_rdata_next = atomic_update_count_reg;
|
|
atomic_update_count_next = 0;
|
|
end
|
|
16'h001C: begin
|
|
// error count
|
|
s_axil_rdata_next = atomic_rx_error_count_reg;
|
|
atomic_rx_error_count_next = 0;
|
|
end
|
|
16'h0020: begin
|
|
// control
|
|
s_axil_rdata_next[0] = accumulate_enable_reg;
|
|
s_axil_rdata_next[1] = slice_enable_reg;
|
|
end
|
|
16'h0024: begin
|
|
// slice time
|
|
s_axil_rdata_next = slice_time_reg;
|
|
end
|
|
16'h0028: begin
|
|
// slice offset
|
|
s_axil_rdata_next = slice_offset_reg;
|
|
end
|
|
16'h0030: begin
|
|
// slice select
|
|
s_axil_rdata_next = slice_select_reg;
|
|
end
|
|
endcase
|
|
end
|
|
end
|
|
end
|
|
|
|
always @(posedge clk) begin
|
|
if (rst) begin
|
|
last_read_reg <= 1'b0;
|
|
|
|
s_axil_awready_reg <= 1'b0;
|
|
s_axil_wready_reg <= 1'b0;
|
|
s_axil_bvalid_reg <= 1'b0;
|
|
|
|
s_axil_arready_reg <= 1'b0;
|
|
s_axil_rvalid_reg <= 1'b0;
|
|
|
|
cycle_count_reg <= 32'd0;
|
|
update_count_reg <= 32'd0;
|
|
rx_error_count_reg <= 32'd0;
|
|
|
|
atomic_cycle_count_reg <= 32'd0;
|
|
atomic_update_count_reg <= 32'd0;
|
|
atomic_rx_error_count_reg <= 32'd0;
|
|
|
|
accumulate_enable_reg <= 1'b0;
|
|
slice_enable_reg <= 1'b0;
|
|
|
|
slice_time_reg <= 32'd0;
|
|
slice_offset_reg <= 32'd0;
|
|
|
|
slice_select_reg <= 0;
|
|
|
|
tx_prbs31_enable_reg <= 1'b0;
|
|
rx_prbs31_enable_reg <= 1'b0;
|
|
end else begin
|
|
last_read_reg <= last_read_next;
|
|
|
|
s_axil_awready_reg <= s_axil_awready_next;
|
|
s_axil_wready_reg <= s_axil_wready_next;
|
|
s_axil_bvalid_reg <= s_axil_bvalid_next;
|
|
|
|
s_axil_arready_reg <= s_axil_arready_next;
|
|
s_axil_rvalid_reg <= s_axil_rvalid_next;
|
|
|
|
cycle_count_reg <= cycle_count_next;
|
|
update_count_reg <= update_count_next;
|
|
rx_error_count_reg <= rx_error_count_next;
|
|
|
|
atomic_cycle_count_reg <= atomic_cycle_count_next;
|
|
atomic_update_count_reg <= atomic_update_count_next;
|
|
atomic_rx_error_count_reg <= atomic_rx_error_count_next;
|
|
|
|
accumulate_enable_reg <= accumulate_enable_next;
|
|
slice_enable_reg <= slice_enable_next;
|
|
|
|
slice_time_reg <= slice_time_next;
|
|
slice_offset_reg <= slice_offset_next;
|
|
|
|
slice_select_reg <= slice_select_next;
|
|
|
|
tx_prbs31_enable_reg <= tx_prbs31_enable_next;
|
|
rx_prbs31_enable_reg <= rx_prbs31_enable_next;
|
|
end
|
|
|
|
s_axil_rdata_reg <= s_axil_rdata_next;
|
|
|
|
error_count_mem_read_reg <= 1'b0;
|
|
update_count_mem_read_reg <= 1'b0;
|
|
|
|
if (mem_rd_en) begin
|
|
if (s_axil_araddr[2]) begin
|
|
error_count_mem_read_data_reg <= error_count_mem[axil_ram_addr];
|
|
error_count_mem_read_reg <= 1'b1;
|
|
end else begin
|
|
update_count_mem_read_data_reg <= update_count_mem[axil_ram_addr];
|
|
update_count_mem_read_reg <= 1'b1;
|
|
end
|
|
end else begin
|
|
for (i = 0; i < WORD_WIDTH; i = i + 1) begin
|
|
if (mem_wr_en && s_axil_wstrb[i]) begin
|
|
if (s_axil_awaddr[2]) begin
|
|
error_count_mem[axil_ram_addr][WORD_SIZE*i +: WORD_SIZE] <= s_axil_wdata[WORD_SIZE*i +: WORD_SIZE];
|
|
end else begin
|
|
update_count_mem[axil_ram_addr][WORD_SIZE*i +: WORD_SIZE] <= s_axil_wdata[WORD_SIZE*i +: WORD_SIZE];
|
|
end
|
|
end
|
|
end
|
|
end
|
|
end
|
|
|
|
endmodule
|
|
|
|
`resetall
|