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110 lines
2.8 KiB
Verilog
Executable File
110 lines
2.8 KiB
Verilog
Executable File
/*
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Copyright (c) 2014-2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* Testbench for arp_cache
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*/
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module test_arp_cache;
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// Inputs
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reg clk = 0;
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reg rst = 0;
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reg [7:0] current_test = 0;
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reg query_request_valid = 0;
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reg [31:0] query_request_ip = 0;
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reg query_response_ready = 0;
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reg write_request_valid = 0;
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reg [31:0] write_request_ip = 0;
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reg [47:0] write_request_mac = 0;
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reg clear_cache = 0;
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// Outputs
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wire query_request_ready;
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wire query_response_valid;
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wire query_response_error;
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wire [47:0] query_response_mac;
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wire write_request_ready;
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initial begin
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// myhdl integration
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$from_myhdl(
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clk,
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rst,
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current_test,
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query_request_valid,
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query_request_ip,
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query_response_ready,
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write_request_valid,
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write_request_ip,
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write_request_mac,
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clear_cache
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);
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$to_myhdl(
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query_request_ready,
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query_response_valid,
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query_response_error,
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query_response_mac,
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write_request_ready
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);
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// dump file
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$dumpfile("test_arp_cache.lxt");
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$dumpvars(0, test_arp_cache);
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end
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arp_cache #(
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.CACHE_ADDR_WIDTH(2)
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)
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UUT (
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.clk(clk),
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.rst(rst),
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// Query cache
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.query_request_valid(query_request_valid),
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.query_request_ready(query_request_ready),
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.query_request_ip(query_request_ip),
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.query_response_valid(query_response_valid),
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.query_response_ready(query_response_ready),
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.query_response_error(query_response_error),
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.query_response_mac(query_response_mac),
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// Write cache
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.write_request_valid(write_request_valid),
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.write_request_ready(write_request_ready),
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.write_request_ip(write_request_ip),
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.write_request_mac(write_request_mac),
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// Configuration
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.clear_cache(clear_cache)
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);
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endmodule
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