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544 lines
22 KiB
Verilog
544 lines
22 KiB
Verilog
/*
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Copyright (c) 2021 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* PCIe AXI Master (write)
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*/
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module pcie_axi_master_wr #
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(
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// TLP data width
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parameter TLP_DATA_WIDTH = 256,
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// TLP header width
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parameter TLP_HDR_WIDTH = 128,
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// TLP segment count
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parameter TLP_SEG_COUNT = 1,
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// Width of AXI data bus in bits
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parameter AXI_DATA_WIDTH = TLP_DATA_WIDTH,
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// Width of AXI address bus in bits
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parameter AXI_ADDR_WIDTH = 64,
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// Width of AXI wstrb (width of data bus in words)
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parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8),
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// Width of AXI ID signal
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parameter AXI_ID_WIDTH = 8,
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// Maximum AXI burst length to generate
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parameter AXI_MAX_BURST_LEN = 256,
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// Force 64 bit address
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parameter TLP_FORCE_64_BIT_ADDR = 0
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)
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(
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input wire clk,
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input wire rst,
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/*
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* TLP input (request)
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*/
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input wire [TLP_DATA_WIDTH-1:0] rx_req_tlp_data,
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input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_req_tlp_hdr,
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input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_valid,
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input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_sop,
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input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_eop,
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output wire rx_req_tlp_ready,
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/*
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* AXI Master output
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*/
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output wire [AXI_ID_WIDTH-1:0] m_axi_awid,
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output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
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output wire [7:0] m_axi_awlen,
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output wire [2:0] m_axi_awsize,
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output wire [1:0] m_axi_awburst,
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output wire m_axi_awlock,
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output wire [3:0] m_axi_awcache,
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output wire [2:0] m_axi_awprot,
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output wire m_axi_awvalid,
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input wire m_axi_awready,
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output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata,
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output wire [AXI_STRB_WIDTH-1:0] m_axi_wstrb,
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output wire m_axi_wlast,
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output wire m_axi_wvalid,
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input wire m_axi_wready,
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input wire [AXI_ID_WIDTH-1:0] m_axi_bid,
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input wire [1:0] m_axi_bresp,
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input wire m_axi_bvalid,
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output wire m_axi_bready,
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/*
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* Status
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*/
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output wire status_error_uncor
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);
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parameter AXI_WORD_WIDTH = AXI_STRB_WIDTH;
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parameter AXI_WORD_SIZE = AXI_DATA_WIDTH/AXI_WORD_WIDTH;
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parameter AXI_BURST_SIZE = $clog2(AXI_STRB_WIDTH);
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parameter AXI_MAX_BURST_SIZE = AXI_MAX_BURST_LEN*AXI_WORD_WIDTH;
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parameter TLP_DATA_WIDTH_BYTES = TLP_DATA_WIDTH/8;
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parameter TLP_DATA_WIDTH_DWORDS = TLP_DATA_WIDTH/32;
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parameter OFFSET_WIDTH = $clog2(TLP_DATA_WIDTH_DWORDS);
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parameter OUTPUT_FIFO_ADDR_WIDTH = 5;
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// bus width assertions
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initial begin
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if (TLP_SEG_COUNT != 1) begin
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$error("Error: TLP segment count must be 1 (instance %m)");
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$finish;
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end
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if (TLP_HDR_WIDTH != 128) begin
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$error("Error: TLP segment header width must be 128 (instance %m)");
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$finish;
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end
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if (AXI_DATA_WIDTH != TLP_DATA_WIDTH) begin
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$error("Error: AXI interface width must match PCIe interface width (instance %m)");
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$finish;
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end
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if (AXI_STRB_WIDTH * 8 != AXI_DATA_WIDTH) begin
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$error("Error: AXI interface requires byte (8-bit) granularity (instance %m)");
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$finish;
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end
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if (AXI_MAX_BURST_LEN < 1 || AXI_MAX_BURST_LEN > 256) begin
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$error("Error: AXI_MAX_BURST_LEN must be between 1 and 256 (instance %m)");
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$finish;
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end
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end
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localparam [2:0]
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TLP_FMT_3DW = 3'b000,
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TLP_FMT_4DW = 3'b001,
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TLP_FMT_3DW_DATA = 3'b010,
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TLP_FMT_4DW_DATA = 3'b011,
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TLP_FMT_PREFIX = 3'b100;
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localparam [1:0]
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STATE_IDLE = 2'd0,
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STATE_TRANSFER = 2'd1,
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STATE_WAIT_END = 2'd2;
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reg [1:0] state_reg = STATE_IDLE, state_next;
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reg [AXI_ADDR_WIDTH-1:0] axi_addr_reg = {AXI_ADDR_WIDTH{1'b0}}, axi_addr_next;
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reg [10:0] op_dword_count_reg = 11'd0, op_dword_count_next;
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reg [10:0] tr_dword_count_reg = 11'd0, tr_dword_count_next;
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reg [12:0] input_cycle_count_reg = 13'd0, input_cycle_count_next;
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reg [12:0] output_cycle_count_reg = 13'd0, output_cycle_count_next;
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reg input_active_reg = 1'b0, input_active_next;
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reg first_cycle_reg = 1'b0, first_cycle_next;
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reg last_cycle_reg = 1'b0, last_cycle_next;
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reg [3:0] type_reg = 4'd0, type_next;
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reg [3:0] first_be_reg = 4'd0, first_be_next;
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reg [3:0] last_be_reg = 4'd0, last_be_next;
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reg [OFFSET_WIDTH-1:0] offset_reg = {OFFSET_WIDTH{1'b0}}, offset_next;
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reg [OFFSET_WIDTH-1:0] last_cycle_offset_reg = {OFFSET_WIDTH{1'b0}}, last_cycle_offset_next;
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reg [2:0] rx_req_tlp_hdr_fmt;
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reg [4:0] rx_req_tlp_hdr_type;
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reg [2:0] rx_req_tlp_hdr_tc;
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reg rx_req_tlp_hdr_ln;
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reg rx_req_tlp_hdr_th;
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reg rx_req_tlp_hdr_td;
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reg rx_req_tlp_hdr_ep;
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reg [2:0] rx_req_tlp_hdr_attr;
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reg [1:0] rx_req_tlp_hdr_at;
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reg [10:0] rx_req_tlp_hdr_length;
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reg [15:0] rx_req_tlp_hdr_requester_id;
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reg [9:0] rx_req_tlp_hdr_tag;
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reg [7:0] rx_req_tlp_hdr_last_be;
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reg [7:0] rx_req_tlp_hdr_first_be;
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reg [63:0] rx_req_tlp_hdr_addr;
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reg [1:0] rx_req_tlp_hdr_ph;
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reg rx_req_tlp_ready_reg = 1'b0, rx_req_tlp_ready_next;
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reg [AXI_ADDR_WIDTH-1:0] m_axi_awaddr_reg = {AXI_ADDR_WIDTH{1'b0}}, m_axi_awaddr_next;
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reg [7:0] m_axi_awlen_reg = 8'd0, m_axi_awlen_next;
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reg m_axi_awvalid_reg = 1'b0, m_axi_awvalid_next;
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reg [TLP_DATA_WIDTH-1:0] save_tlp_data_reg = {TLP_DATA_WIDTH{1'b0}};
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wire [TLP_DATA_WIDTH-1:0] shift_tlp_data = {rx_req_tlp_data, save_tlp_data_reg} >> ((TLP_DATA_WIDTH_DWORDS-offset_reg)*32);
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reg status_error_uncor_reg = 1'b0, status_error_uncor_next;
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// internal datapath
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reg [AXI_DATA_WIDTH-1:0] m_axi_wdata_int;
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reg [AXI_STRB_WIDTH-1:0] m_axi_wstrb_int;
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reg m_axi_wvalid_int;
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reg m_axi_wlast_int;
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wire m_axi_wready_int;
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assign rx_req_tlp_ready = rx_req_tlp_ready_reg;
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assign m_axi_awid = {AXI_ID_WIDTH{1'b0}};
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assign m_axi_awaddr = m_axi_awaddr_reg;
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assign m_axi_awlen = m_axi_awlen_reg;
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assign m_axi_awsize = $clog2(AXI_STRB_WIDTH);
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assign m_axi_awburst = 2'b01;
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assign m_axi_awlock = 1'b0;
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assign m_axi_awcache = 4'b0011;
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assign m_axi_awprot = 3'b010;
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assign m_axi_awvalid = m_axi_awvalid_reg;
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assign m_axi_bready = 1'b1;
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assign status_error_uncor = status_error_uncor_reg;
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always @* begin
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state_next = STATE_IDLE;
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type_next = type_reg;
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axi_addr_next = axi_addr_reg;
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op_dword_count_next = op_dword_count_reg;
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tr_dword_count_next = tr_dword_count_reg;
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input_cycle_count_next = input_cycle_count_reg;
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output_cycle_count_next = output_cycle_count_reg;
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input_active_next = input_active_reg;
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first_cycle_next = first_cycle_reg;
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last_cycle_next = last_cycle_reg;
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first_be_next = first_be_reg;
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last_be_next = last_be_reg;
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offset_next = offset_reg;
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last_cycle_offset_next = last_cycle_offset_reg;
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rx_req_tlp_ready_next = 1'b0;
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m_axi_awaddr_next = m_axi_awaddr_reg;
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m_axi_awlen_next = m_axi_awlen_reg;
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m_axi_awvalid_next = m_axi_awvalid_reg && !m_axi_awready;
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m_axi_wdata_int = shift_tlp_data;
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m_axi_wstrb_int = {AXI_STRB_WIDTH{1'b1}};
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m_axi_wvalid_int = 1'b0;
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m_axi_wlast_int = 1'b0;
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status_error_uncor_next = 1'b0;
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// TLP header parsing
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// DW 0
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rx_req_tlp_hdr_fmt = rx_req_tlp_hdr[127:125]; // fmt
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rx_req_tlp_hdr_type = rx_req_tlp_hdr[124:120]; // type
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rx_req_tlp_hdr_tag[9] = rx_req_tlp_hdr[119]; // T9
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rx_req_tlp_hdr_tc = rx_req_tlp_hdr[118:116]; // TC
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rx_req_tlp_hdr_tag[8] = rx_req_tlp_hdr[115]; // T8
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rx_req_tlp_hdr_attr[2] = rx_req_tlp_hdr[114]; // attr
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rx_req_tlp_hdr_ln = rx_req_tlp_hdr[113]; // LN
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rx_req_tlp_hdr_th = rx_req_tlp_hdr[112]; // TH
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rx_req_tlp_hdr_td = rx_req_tlp_hdr[111]; // TD
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rx_req_tlp_hdr_ep = rx_req_tlp_hdr[110]; // EP
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rx_req_tlp_hdr_attr[1:0] = rx_req_tlp_hdr[109:108]; // attr
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rx_req_tlp_hdr_at = rx_req_tlp_hdr[107:106]; // AT
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rx_req_tlp_hdr_length = {rx_req_tlp_hdr[105:96] == 0, rx_req_tlp_hdr[105:96]}; // length
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// DW 1
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rx_req_tlp_hdr_requester_id = rx_req_tlp_hdr[95:80]; // requester ID
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rx_req_tlp_hdr_tag[7:0] = rx_req_tlp_hdr[79:72]; // tag
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rx_req_tlp_hdr_last_be = rx_req_tlp_hdr[71:68]; // last BE
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rx_req_tlp_hdr_first_be = rx_req_tlp_hdr[67:64]; // first BE
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if (rx_req_tlp_hdr_fmt[0] || TLP_FORCE_64_BIT_ADDR) begin
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// 4 DW (64-bit address)
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// DW 2+3
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rx_req_tlp_hdr_addr = {rx_req_tlp_hdr[63:2], 2'b00}; // addr
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rx_req_tlp_hdr_ph = rx_req_tlp_hdr[1:0]; // PH
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end else begin
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// 3 DW (32-bit address)
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// DW 2
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rx_req_tlp_hdr_addr = {rx_req_tlp_hdr[63:34], 2'b00}; // addr
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rx_req_tlp_hdr_ph = rx_req_tlp_hdr[33:32]; // PH
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end
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case (state_reg)
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STATE_IDLE: begin
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// idle state, wait for completion request
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rx_req_tlp_ready_next = (!m_axi_awvalid_reg || m_axi_awready) && m_axi_wready_int;
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axi_addr_next = rx_req_tlp_hdr_addr;
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op_dword_count_next = rx_req_tlp_hdr_length;
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first_be_next = rx_req_tlp_hdr_first_be;
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last_be_next = op_dword_count_next == 1 ? rx_req_tlp_hdr_first_be : rx_req_tlp_hdr_last_be;
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if (rx_req_tlp_ready && rx_req_tlp_valid && rx_req_tlp_sop) begin
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if (op_dword_count_next <= AXI_MAX_BURST_SIZE/4) begin
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// packet smaller than max burst size
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// assumed to not cross 4k boundary, send one request
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tr_dword_count_next = op_dword_count_next;
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m_axi_awlen_next = (tr_dword_count_next + axi_addr_next[OFFSET_WIDTH+2-1:2] - 1) >> (AXI_BURST_SIZE-2);
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end else begin
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// packet larger than max burst size
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// assumed to not cross 4k boundary, aligned split on burst size
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tr_dword_count_next = AXI_MAX_BURST_SIZE/4 - axi_addr_next[OFFSET_WIDTH+2-1:2];
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m_axi_awlen_next = (tr_dword_count_next - 1) >> (AXI_BURST_SIZE-2);
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end
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m_axi_awaddr_next = axi_addr_next;
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// required DWORD shift to place first DWORD from the TLP payload into proper position on AXI interface
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offset_next = axi_addr_next >> 2;
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first_cycle_next = 1'b1;
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// number of bus transfers in TLP, DOWRD count divided by bus width in DWORDS
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input_cycle_count_next = (tr_dword_count_next - 1) >> (AXI_BURST_SIZE-2);
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// number of bus transfers to AXI, DWORD count plus DWORD offset, divided by bus width in DWORDS
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output_cycle_count_next = m_axi_awlen_next;
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last_cycle_offset_next = offset_next + tr_dword_count_next;
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last_cycle_next = output_cycle_count_next == 0;
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input_active_next = input_cycle_count_next != 0;
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axi_addr_next = axi_addr_next + (tr_dword_count_next << 2);
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op_dword_count_next = op_dword_count_next - tr_dword_count_next;
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if (rx_req_tlp_hdr_fmt[1] && rx_req_tlp_hdr_type == 5'b00000 && !rx_req_tlp_hdr_ep) begin
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// write request
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m_axi_awvalid_next = 1'b1;
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rx_req_tlp_ready_next = 1'b0;
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state_next = STATE_TRANSFER;
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end else begin
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// other request
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status_error_uncor_next = 1'b1;
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if (rx_req_tlp_eop) begin
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state_next = STATE_IDLE;
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end else begin
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rx_req_tlp_ready_next = 1'b1;
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state_next = STATE_WAIT_END;
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end
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end
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end
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end
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STATE_TRANSFER: begin
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// transfer state, transfer data
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rx_req_tlp_ready_next = m_axi_wready_int && input_active_reg && !first_cycle_reg;
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if ((rx_req_tlp_ready && rx_req_tlp_valid) || !input_active_reg || first_cycle_reg) begin
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// transfer data
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if (first_cycle_reg) begin
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m_axi_wdata_int = {save_tlp_data_reg, {TLP_DATA_WIDTH{1'b0}}} >> ((TLP_DATA_WIDTH_DWORDS-offset_reg)*32);
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rx_req_tlp_ready_next = m_axi_wready_int && input_active_reg;
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end else begin
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m_axi_wdata_int = shift_tlp_data;
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end
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// generate strb signal
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if (first_cycle_reg) begin
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m_axi_wstrb_int = {{AXI_STRB_WIDTH-4{1'b1}}, first_be_reg} << (offset_reg*4);
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end else begin
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m_axi_wstrb_int = {AXI_STRB_WIDTH{1'b1}};
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end
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// update cycle counters
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if (input_active_reg && !first_cycle_reg) begin
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input_cycle_count_next = input_cycle_count_reg - 1;
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input_active_next = input_cycle_count_next != 0;
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end
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output_cycle_count_next = output_cycle_count_reg - 1;
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last_cycle_next = output_cycle_count_next == 0;
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// modify strb signal at end of transfer
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if (last_cycle_reg) begin
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if (op_dword_count_reg == 0) begin
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if (last_cycle_offset_reg > 0) begin
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m_axi_wstrb_int = m_axi_wstrb_int & {last_be_reg, {AXI_STRB_WIDTH-4{1'b1}}} >> (AXI_STRB_WIDTH-last_cycle_offset_reg*4);
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end else begin
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m_axi_wstrb_int = m_axi_wstrb_int & {last_be_reg, {AXI_STRB_WIDTH-4{1'b1}}};
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end
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end
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m_axi_wlast_int = 1'b1;
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end
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m_axi_wvalid_int = 1'b1;
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first_cycle_next = 1'b0;
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if (!last_cycle_reg) begin
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// more data to transfer
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rx_req_tlp_ready_next = m_axi_wready_int && input_active_next;
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state_next = STATE_TRANSFER;
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end else if (op_dword_count_reg > 0) begin
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// current transfer done, but operation not finished yet
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if (op_dword_count_reg <= AXI_MAX_BURST_SIZE/4) begin
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// packet smaller than max burst size
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// assumed to not cross 4k boundary, send one request
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tr_dword_count_next = op_dword_count_reg;
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m_axi_awlen_next = (tr_dword_count_next + axi_addr_reg[OFFSET_WIDTH+2-1:2] - 1) >> (AXI_BURST_SIZE-2);
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end else begin
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// packet larger than max burst size
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// assumed to not cross 4k boundary, aligned split on burst size
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tr_dword_count_next = AXI_MAX_BURST_SIZE/4 - axi_addr_reg[OFFSET_WIDTH+2-1:2];
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m_axi_awlen_next = (tr_dword_count_next - 1) >> (AXI_BURST_SIZE-2);
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end
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m_axi_awaddr_next = axi_addr_reg;
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|
|
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// number of bus transfers in TLP, DOWRD count minus payload start DWORD offset, divided by bus width in DWORDS
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input_cycle_count_next = (tr_dword_count_next - offset_reg - 1) >> (AXI_BURST_SIZE-2);
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// number of bus transfers to AXI, DWORD count plus DWORD offset, divided by bus width in DWORDS
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output_cycle_count_next = m_axi_awlen_next;
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last_cycle_offset_next = axi_addr_reg[OFFSET_WIDTH+2-1:2] + tr_dword_count_next;
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last_cycle_next = output_cycle_count_next == 0;
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input_active_next = input_cycle_count_next != 0;
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|
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axi_addr_next = axi_addr_reg + (tr_dword_count_next << 2);
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op_dword_count_next = op_dword_count_reg - tr_dword_count_next;
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|
|
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m_axi_awvalid_next = 1'b1;
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rx_req_tlp_ready_next = m_axi_wready_int && input_active_next;
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state_next = STATE_TRANSFER;
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end else begin
|
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rx_req_tlp_ready_next = (!m_axi_awvalid_reg || m_axi_awready) && m_axi_wready_int;
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state_next = STATE_IDLE;
|
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end
|
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end else begin
|
|
state_next = STATE_TRANSFER;
|
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end
|
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end
|
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STATE_WAIT_END: begin
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// wait end state, wait for end of TLP
|
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rx_req_tlp_ready_next = 1'b1;
|
|
|
|
if (rx_req_tlp_ready && rx_req_tlp_valid) begin
|
|
if (rx_req_tlp_eop) begin
|
|
|
|
rx_req_tlp_ready_next = (!m_axi_awvalid_reg || m_axi_awready) && m_axi_wready_int;
|
|
|
|
state_next = STATE_IDLE;
|
|
end else begin
|
|
state_next = STATE_WAIT_END;
|
|
end
|
|
end else begin
|
|
state_next = STATE_WAIT_END;
|
|
end
|
|
end
|
|
endcase
|
|
end
|
|
|
|
always @(posedge clk) begin
|
|
state_reg <= state_next;
|
|
|
|
axi_addr_reg <= axi_addr_next;
|
|
op_dword_count_reg <= op_dword_count_next;
|
|
tr_dword_count_reg <= tr_dword_count_next;
|
|
input_cycle_count_reg <= input_cycle_count_next;
|
|
output_cycle_count_reg <= output_cycle_count_next;
|
|
input_active_reg <= input_active_next;
|
|
first_cycle_reg <= first_cycle_next;
|
|
last_cycle_reg <= last_cycle_next;
|
|
|
|
type_reg <= type_next;
|
|
first_be_reg <= first_be_next;
|
|
last_be_reg <= last_be_next;
|
|
offset_reg <= offset_next;
|
|
last_cycle_offset_reg <= last_cycle_offset_next;
|
|
|
|
rx_req_tlp_ready_reg <= rx_req_tlp_ready_next;
|
|
|
|
m_axi_awaddr_reg <= m_axi_awaddr_next;
|
|
m_axi_awlen_reg <= m_axi_awlen_next;
|
|
m_axi_awvalid_reg <= m_axi_awvalid_next;
|
|
|
|
status_error_uncor_reg <= status_error_uncor_next;
|
|
|
|
if (rx_req_tlp_ready && rx_req_tlp_valid) begin
|
|
save_tlp_data_reg <= rx_req_tlp_data;
|
|
end
|
|
|
|
if (rst) begin
|
|
state_reg <= STATE_IDLE;
|
|
|
|
rx_req_tlp_ready_reg <= 1'b0;
|
|
|
|
m_axi_awvalid_reg <= 1'b0;
|
|
|
|
status_error_uncor_reg <= 1'b0;
|
|
end
|
|
end
|
|
|
|
// output datapath logic (AXI write data)
|
|
reg [AXI_DATA_WIDTH-1:0] m_axi_wdata_reg = {AXI_DATA_WIDTH{1'b0}};
|
|
reg [AXI_STRB_WIDTH-1:0] m_axi_wstrb_reg = {AXI_STRB_WIDTH{1'b0}};
|
|
reg m_axi_wlast_reg = 1'b0;
|
|
reg m_axi_wvalid_reg = 1'b0;
|
|
|
|
reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_fifo_wr_ptr_reg = 0;
|
|
reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_fifo_rd_ptr_reg = 0;
|
|
reg out_fifo_half_full_reg = 1'b0;
|
|
|
|
wire out_fifo_full = out_fifo_wr_ptr_reg == (out_fifo_rd_ptr_reg ^ {1'b1, {OUTPUT_FIFO_ADDR_WIDTH{1'b0}}});
|
|
wire out_fifo_empty = out_fifo_wr_ptr_reg == out_fifo_rd_ptr_reg;
|
|
|
|
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
|
|
reg [AXI_DATA_WIDTH-1:0] out_fifo_wdata[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
|
|
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
|
|
reg [AXI_STRB_WIDTH-1:0] out_fifo_wstrb[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
|
|
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
|
|
reg out_fifo_wlast[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
|
|
|
|
assign m_axi_wready_int = !out_fifo_half_full_reg;
|
|
|
|
assign m_axi_wdata = m_axi_wdata_reg;
|
|
assign m_axi_wstrb = m_axi_wstrb_reg;
|
|
assign m_axi_wvalid = m_axi_wvalid_reg;
|
|
assign m_axi_wlast = m_axi_wlast_reg;
|
|
|
|
always @(posedge clk) begin
|
|
m_axi_wvalid_reg <= m_axi_wvalid_reg && !m_axi_wready;
|
|
|
|
out_fifo_half_full_reg <= $unsigned(out_fifo_wr_ptr_reg - out_fifo_rd_ptr_reg) >= 2**(OUTPUT_FIFO_ADDR_WIDTH-1);
|
|
|
|
if (!out_fifo_full && m_axi_wvalid_int) begin
|
|
out_fifo_wdata[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axi_wdata_int;
|
|
out_fifo_wstrb[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axi_wstrb_int;
|
|
out_fifo_wlast[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axi_wlast_int;
|
|
out_fifo_wr_ptr_reg <= out_fifo_wr_ptr_reg + 1;
|
|
end
|
|
|
|
if (!out_fifo_empty && (!m_axi_wvalid_reg || m_axi_wready)) begin
|
|
m_axi_wdata_reg <= out_fifo_wdata[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
|
|
m_axi_wstrb_reg <= out_fifo_wstrb[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
|
|
m_axi_wlast_reg <= out_fifo_wlast[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
|
|
m_axi_wvalid_reg <= 1'b1;
|
|
out_fifo_rd_ptr_reg <= out_fifo_rd_ptr_reg + 1;
|
|
end
|
|
|
|
if (rst) begin
|
|
out_fifo_wr_ptr_reg <= 0;
|
|
out_fifo_rd_ptr_reg <= 0;
|
|
m_axi_wvalid_reg <= 1'b0;
|
|
end
|
|
end
|
|
|
|
endmodule
|
|
|
|
`resetall
|