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354 lines
10 KiB
Python
354 lines
10 KiB
Python
#!/usr/bin/env python
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"""
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Copyright (c) 2022 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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"""
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import itertools
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import logging
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import os
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import re
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import sys
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from contextlib import contextmanager
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import cocotb_test.simulator
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import pytest
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import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import RisingEdge
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from cocotb.regression import TestFactory
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from cocotbext.axi import AxiLiteBus, AxiLiteMaster
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from cocotbext.axi.stream import define_stream
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try:
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from pcie_if import PcieIfSink, PcieIfTxBus
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except ImportError:
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# attempt import from current directory
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sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
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try:
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from pcie_if import PcieIfSink, PcieIfTxBus
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finally:
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del sys.path[0]
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IrqBus, IrqTransaction, IrqSource, IrqSink, IrqMonitor = define_stream("Irq",
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signals=["index", "valid", "ready"]
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)
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@contextmanager
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def assert_raises(exc_type, pattern=None):
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try:
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yield
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except exc_type as e:
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if pattern:
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assert re.match(pattern, str(e)), \
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"Correct exception type caught, but message did not match pattern"
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pass
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else:
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raise AssertionError("{} was not raised".format(exc_type.__name__))
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class TB(object):
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def __init__(self, dut):
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self.dut = dut
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self.log = logging.getLogger("cocotb.tb")
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self.log.setLevel(logging.DEBUG)
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cocotb.start_soon(Clock(dut.clk, 4, units="ns").start())
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self.axil_master = AxiLiteMaster(AxiLiteBus.from_prefix(dut, "s_axil"), dut.clk, dut.rst)
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self.irq_source = IrqSource(IrqBus.from_prefix(dut, "irq"), dut.clk, dut.rst)
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self.tlp_sink = PcieIfSink(PcieIfTxBus.from_prefix(dut, "tx_wr_req_tlp"), dut.clk, dut.rst)
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dut.requester_id.setimmediatevalue(0)
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dut.msix_enable.setimmediatevalue(0)
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dut.msix_mask.setimmediatevalue(0)
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def set_idle_generator(self, generator=None):
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if generator:
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self.axil_master.write_if.aw_channel.set_pause_generator(generator())
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self.axil_master.write_if.w_channel.set_pause_generator(generator())
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self.axil_master.read_if.ar_channel.set_pause_generator(generator())
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def set_backpressure_generator(self, generator=None):
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if generator:
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self.axil_master.write_if.b_channel.set_pause_generator(generator())
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self.axil_master.read_if.r_channel.set_pause_generator(generator())
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self.tlp_sink.set_pause_generator(generator())
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async def cycle_reset(self):
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self.dut.rst.setimmediatevalue(0)
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst.value = 1
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst.value = 0
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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async def run_test_table_write(dut, data_in=None, idle_inserter=None, backpressure_inserter=None):
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tb = TB(dut)
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byte_lanes = tb.axil_master.write_if.byte_lanes
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await tb.cycle_reset()
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tb.set_idle_generator(idle_inserter)
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tb.set_backpressure_generator(backpressure_inserter)
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for length in range(1, byte_lanes*4):
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for offset in range(byte_lanes):
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tb.log.info("length %d, offset %d", length, offset)
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addr = offset+0x100
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test_data = bytearray([x % 256 for x in range(length)])
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await tb.axil_master.write(addr-4, b'\xaa'*(length+8))
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await tb.axil_master.write(addr, test_data)
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data = await tb.axil_master.read(addr-1, length+2)
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assert data.data == b'\xaa'+test_data+b'\xaa'
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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async def run_test_table_read(dut, data_in=None, idle_inserter=None, backpressure_inserter=None):
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tb = TB(dut)
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byte_lanes = tb.axil_master.write_if.byte_lanes
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await tb.cycle_reset()
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tb.set_idle_generator(idle_inserter)
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tb.set_backpressure_generator(backpressure_inserter)
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for length in range(1, byte_lanes*4):
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for offset in range(byte_lanes):
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tb.log.info("length %d, offset %d", length, offset)
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addr = offset+0x100
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test_data = bytearray([x % 256 for x in range(length)])
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await tb.axil_master.write(addr, test_data)
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data = await tb.axil_master.read(addr, length)
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assert data.data == test_data
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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async def run_test_msix(dut, idle_inserter=None, backpressure_inserter=None):
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tb = TB(dut)
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tbl_offset = 0
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pba_offset = 2**(tb.axil_master.write_if.address_width-1)
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await tb.cycle_reset()
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tb.set_idle_generator(idle_inserter)
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tb.set_backpressure_generator(backpressure_inserter)
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dut.msix_enable.value = 1
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tb.log.info("Init table")
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for k in range(2**len(dut.irq_index)):
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await tb.axil_master.write_qword(tbl_offset+k*16+0, 0x1234567800000000 + k*4)
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await tb.axil_master.write_dword(tbl_offset+k*16+8, k)
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await tb.axil_master.write_dword(tbl_offset+k*16+12, 0)
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tb.log.info("Test unmasked interrupts")
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for k in range(8):
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await tb.irq_source.send(IrqTransaction(index=k))
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for k in range(8):
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frame = await tb.tlp_sink.recv()
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tlp = frame.to_tlp()
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tb.log.info("TLP: %s", tlp)
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assert tlp.address == 0x1234567800000000 + k*4
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assert tlp.data == k.to_bytes(4, 'little')
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assert tlp.first_be == 0xf
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val = await tb.axil_master.read_dword(pba_offset+0)
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tb.log.info("PBA value: 0x%02x", val)
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assert val == 0x00
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tb.log.info("Test global mask")
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dut.msix_mask.value = 1
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for k in range(8):
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await tb.irq_source.send(IrqTransaction(index=k))
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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while dut.irq_valid.value.integer:
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await RisingEdge(dut.clk)
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for k in range(10):
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await RisingEdge(dut.clk)
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val = await tb.axil_master.read_dword(pba_offset+0)
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tb.log.info("PBA value: 0x%02x", val)
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assert val == 0xff
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dut.msix_mask.value = 0
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for k in range(8):
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frame = await tb.tlp_sink.recv()
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tlp = frame.to_tlp()
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tb.log.info("TLP: %s", tlp)
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assert tlp.address == 0x1234567800000000 + k*4
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assert tlp.data == k.to_bytes(4, 'little')
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assert tlp.first_be == 0xf
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val = await tb.axil_master.read_dword(pba_offset+0)
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tb.log.info("PBA value: 0x%02x", val)
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assert val == 0x00
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tb.log.info("Test vector masks")
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for k in range(8):
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await tb.axil_master.write_dword(tbl_offset+k*16+12, 1)
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for k in range(8):
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await tb.irq_source.send(IrqTransaction(index=k))
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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while dut.irq_valid.value.integer:
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await RisingEdge(dut.clk)
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for k in range(10):
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await RisingEdge(dut.clk)
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val = await tb.axil_master.read_dword(pba_offset+0)
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tb.log.info("PBA value: 0x%02x", val)
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assert val == 0xff
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for k in range(8):
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await tb.axil_master.write_dword(tbl_offset+k*16+12, 0)
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for k in range(8):
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frame = await tb.tlp_sink.recv()
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tlp = frame.to_tlp()
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tb.log.info("TLP: %s", tlp)
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assert tlp.address == 0x1234567800000000 + k*4
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assert tlp.data == k.to_bytes(4, 'little')
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assert tlp.first_be == 0xf
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val = await tb.axil_master.read_dword(pba_offset+0)
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tb.log.info("PBA value: 0x%02x", val)
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assert val == 0x00
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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def cycle_pause():
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return itertools.cycle([1, 1, 1, 0])
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if cocotb.SIM_NAME:
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for test in [
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run_test_table_write,
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run_test_table_read,
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run_test_msix
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]:
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factory = TestFactory(test)
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factory.add_option("idle_inserter", [None, cycle_pause])
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factory.add_option("backpressure_inserter", [None, cycle_pause])
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factory.generate_tests()
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# cocotb-test
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tests_dir = os.path.dirname(__file__)
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rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
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@pytest.mark.parametrize("axil_data_width", [32, 64])
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def test_pcie_msix(request, axil_data_width):
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dut = "pcie_msix"
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module = os.path.splitext(os.path.basename(__file__))[0]
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toplevel = dut
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verilog_sources = [
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os.path.join(rtl_dir, f"{dut}.v"),
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]
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parameters = {}
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parameters['IRQ_INDEX_WIDTH'] = 11
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parameters['AXIL_DATA_WIDTH'] = axil_data_width
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parameters['AXIL_ADDR_WIDTH'] = parameters['IRQ_INDEX_WIDTH']+5
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parameters['AXIL_STRB_WIDTH'] = (axil_data_width // 8)
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parameters['TLP_HDR_WIDTH'] = 128
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parameters['TLP_FORCE_64_BIT_ADDR'] = 0
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extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
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sim_build = os.path.join(tests_dir, "sim_build",
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request.node.name.replace('[', '-').replace(']', ''))
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cocotb_test.simulator.run(
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python_search=[tests_dir],
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verilog_sources=verilog_sources,
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toplevel=toplevel,
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module=module,
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parameters=parameters,
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sim_build=sim_build,
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extra_env=extra_env,
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)
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