Alex Forencich 48577f3a2d Add simple register as a per-channel option to AXI register modules

2018-08-16 13:25:07 -07:00

..

axi.py

Add prot and resp signal encoding constants

2018-08-15 23:02:57 -07:00

axil.py

Don't crash when omitting read or write port connections

2018-08-16 12:50:14 -07:00

test_axi_fifo_delay.py

Add AXI FIFOs and testbenches

2018-08-13 15:31:04 -07:00

test_axi_fifo_delay.v

Add AXI FIFOs and testbenches

2018-08-13 15:31:04 -07:00

test_axi_fifo_rd_delay.py

Add AXI FIFOs and testbenches

2018-08-13 15:31:04 -07:00

test_axi_fifo_rd_delay.v

Add AXI FIFOs and testbenches

2018-08-13 15:31:04 -07:00

test_axi_fifo_rd.py

Add AXI FIFOs and testbenches

2018-08-13 15:31:04 -07:00

test_axi_fifo_rd.v

Add AXI FIFOs and testbenches

2018-08-13 15:31:04 -07:00

test_axi_fifo_wr_delay.py

Add AXI FIFOs and testbenches

2018-08-13 15:31:04 -07:00

test_axi_fifo_wr_delay.v

Add AXI FIFOs and testbenches

2018-08-13 15:31:04 -07:00

test_axi_fifo_wr.py

Add AXI FIFOs and testbenches

2018-08-13 15:31:04 -07:00

test_axi_fifo_wr.v

Add AXI FIFOs and testbenches

2018-08-13 15:31:04 -07:00

test_axi_fifo.py

Add AXI FIFOs and testbenches

2018-08-13 15:31:04 -07:00

test_axi_fifo.v

Add AXI FIFOs and testbenches

2018-08-13 15:31:04 -07:00

test_axi_ram.py

Don't use narrow bursts for setup and checking in AXI RAM testbench

2018-08-14 23:44:15 -07:00

test_axi_ram.v

Initial commit

2018-07-29 19:04:30 -07:00

test_axi_register_rd.py

Add simple register as a per-channel option to AXI register modules

2018-08-16 13:25:07 -07:00

test_axi_register_rd.v

Add simple register as a per-channel option to AXI register modules

2018-08-16 13:25:07 -07:00

test_axi_register_wr.py

Add simple register as a per-channel option to AXI register modules

2018-08-16 13:25:07 -07:00

test_axi_register_wr.v

Add simple register as a per-channel option to AXI register modules

2018-08-16 13:25:07 -07:00

test_axi_register.py

Add simple register as a per-channel option to AXI register modules

2018-08-16 13:25:07 -07:00

test_axi_register.v

Add simple register as a per-channel option to AXI register modules

2018-08-16 13:25:07 -07:00

test_axi.py

Properly handle read bursts in AXI model

2018-08-13 15:12:56 -07:00

test_axil_ram.py

Add AXI lite RAM module and testbench

2018-08-14 23:49:40 -07:00

test_axil_ram.v

Add AXI lite RAM module and testbench

2018-08-14 23:49:40 -07:00

test_axil_register_rd.py

Add AXI lite registers and testbenches

2018-08-16 13:01:45 -07:00

test_axil_register_rd.v

Add AXI lite registers and testbenches

2018-08-16 13:01:45 -07:00

test_axil_register_wr.py

Add AXI lite registers and testbenches

2018-08-16 13:01:45 -07:00

test_axil_register_wr.v

Add AXI lite registers and testbenches

2018-08-16 13:01:45 -07:00

test_axil_register.py

Add AXI lite registers and testbenches

2018-08-16 13:01:45 -07:00

test_axil_register.v

Add AXI lite registers and testbenches

2018-08-16 13:01:45 -07:00

test_axil.py

Add MyHDL AXI4 Lite master model, RAM model, and testbench

2018-08-14 23:49:11 -07:00