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1715 lines
61 KiB
Verilog
1715 lines
61 KiB
Verilog
/*
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Copyright 2019, The Regents of the University of California.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
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IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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The views and conclusions contained in the software and documentation are those
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of the authors and should not be interpreted as representing official policies,
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either expressed or implied, of The Regents of the University of California.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* NIC Port
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*/
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module port #
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(
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// DMA address width
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parameter DMA_ADDR_WIDTH = 64,
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// DMA length field width
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parameter DMA_LEN_WIDTH = 16,
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// DMA tag field width
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parameter DMA_TAG_WIDTH = 8,
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// Request tag field width
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parameter REQ_TAG_WIDTH = 8,
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// Descriptor request tag field width
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parameter DESC_REQ_TAG_WIDTH = 8,
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// Queue request tag field width
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parameter QUEUE_REQ_TAG_WIDTH = 8,
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// Queue operation tag field width
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parameter QUEUE_OP_TAG_WIDTH = 8,
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// Transmit queue index width
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parameter TX_QUEUE_INDEX_WIDTH = 8,
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// Receive queue index width
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parameter RX_QUEUE_INDEX_WIDTH = 8,
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// Max queue index width
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parameter QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH,
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// Transmit completion queue index width
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parameter TX_CPL_QUEUE_INDEX_WIDTH = 8,
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// Receive completion queue index width
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parameter RX_CPL_QUEUE_INDEX_WIDTH = 8,
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// Max completion queue index width
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parameter CPL_QUEUE_INDEX_WIDTH = TX_CPL_QUEUE_INDEX_WIDTH > RX_CPL_QUEUE_INDEX_WIDTH ? TX_CPL_QUEUE_INDEX_WIDTH : RX_CPL_QUEUE_INDEX_WIDTH,
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// Transmit descriptor table size (number of in-flight operations)
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parameter TX_DESC_TABLE_SIZE = 16,
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// Transmit packet table size (number of in-progress packets)
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parameter TX_PKT_TABLE_SIZE = 8,
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// Receive descriptor table size (number of in-flight operations)
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parameter RX_DESC_TABLE_SIZE = 16,
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// Receive packet table size (number of in-progress packets)
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parameter RX_PKT_TABLE_SIZE = 8,
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// Transmit scheduler type
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parameter TX_SCHEDULER = "RR",
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// Scheduler operation table size
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parameter TX_SCHEDULER_OP_TABLE_SIZE = 32,
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// Scheduler TDMA index width
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parameter TDMA_INDEX_WIDTH = 8,
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// Queue element pointer width
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parameter QUEUE_PTR_WIDTH = 16,
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// Enable PTP timestamping
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parameter PTP_TS_ENABLE = 1,
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// PTP timestamp width
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parameter PTP_TS_WIDTH = 96,
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// Enable TX checksum offload
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parameter TX_CHECKSUM_ENABLE = 1,
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// Enable RX checksum offload
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parameter RX_CHECKSUM_ENABLE = 1,
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// Width of AXI lite data bus in bits
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parameter AXIL_DATA_WIDTH = 32,
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// Width of AXI lite address bus in bits
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parameter AXIL_ADDR_WIDTH = 16,
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// Width of AXI lite wstrb (width of data bus in words)
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parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8),
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// DMA RAM segment count
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parameter SEG_COUNT = 2,
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// DMA RAM segment data width
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parameter SEG_DATA_WIDTH = 64,
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// DMA RAM segment address width
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parameter SEG_ADDR_WIDTH = 8,
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// DMA RAM segment byte enable width
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parameter SEG_BE_WIDTH = SEG_DATA_WIDTH/8,
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// DMA RAM address width
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parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH),
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// DMA RAM pipeline stages
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parameter RAM_PIPELINE = 2,
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// Width of AXI stream interfaces in bits
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parameter AXIS_DATA_WIDTH = 256,
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// AXI stream tkeep signal width (words per cycle)
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parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8,
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// Max transmit packet size
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parameter MAX_TX_SIZE = 2048,
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// Max receive packet size
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parameter MAX_RX_SIZE = 2048,
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// Descriptor size (in bytes)
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parameter DESC_SIZE = 16,
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// Descriptor size (in bytes)
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parameter CPL_SIZE = 32,
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// Width of AXI stream descriptor interfaces in bits
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parameter AXIS_DESC_DATA_WIDTH = DESC_SIZE*8,
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// AXI stream descriptor tkeep signal width (words per cycle)
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parameter AXIS_DESC_KEEP_WIDTH = AXIS_DESC_DATA_WIDTH/8,
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// DMA TX RAM size
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parameter TX_RAM_SIZE = TX_PKT_TABLE_SIZE*MAX_TX_SIZE,
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// DMA RX RAM size
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parameter RX_RAM_SIZE = RX_PKT_TABLE_SIZE*MAX_RX_SIZE
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)
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(
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input wire clk,
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input wire rst,
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/*
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* Descriptor request output
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*/
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output wire [0:0] m_axis_desc_req_sel,
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output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_desc_req_queue,
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output wire [DESC_REQ_TAG_WIDTH-1:0] m_axis_desc_req_tag,
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output wire m_axis_desc_req_valid,
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input wire m_axis_desc_req_ready,
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/*
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* Descriptor request status input
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*/
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input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_queue,
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input wire [QUEUE_PTR_WIDTH-1:0] s_axis_desc_req_status_ptr,
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input wire [CPL_QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_cpl,
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input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_desc_req_status_tag,
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input wire s_axis_desc_req_status_empty,
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input wire s_axis_desc_req_status_error,
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input wire s_axis_desc_req_status_valid,
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/*
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* Descriptor data input
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*/
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input wire [AXIS_DESC_DATA_WIDTH-1:0] s_axis_desc_tdata,
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input wire [AXIS_DESC_KEEP_WIDTH-1:0] s_axis_desc_tkeep,
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input wire s_axis_desc_tvalid,
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output wire s_axis_desc_tready,
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input wire s_axis_desc_tlast,
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input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_desc_tid,
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input wire s_axis_desc_tuser,
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/*
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* Completion request output
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*/
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output wire [0:0] m_axis_cpl_req_sel,
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output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_cpl_req_queue,
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output wire [DESC_REQ_TAG_WIDTH-1:0] m_axis_cpl_req_tag,
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output wire [CPL_SIZE*8-1:0] m_axis_cpl_req_data,
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output wire m_axis_cpl_req_valid,
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input wire m_axis_cpl_req_ready,
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/*
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* Completion request status input
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*/
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input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_cpl_req_status_tag,
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input wire s_axis_cpl_req_status_full,
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input wire s_axis_cpl_req_status_error,
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input wire s_axis_cpl_req_status_valid,
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/*
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* TX doorbell input
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*/
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input wire [TX_QUEUE_INDEX_WIDTH-1:0] s_axis_tx_doorbell_queue,
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input wire s_axis_tx_doorbell_valid,
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/*
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* DMA read descriptor output
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*/
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output wire [DMA_ADDR_WIDTH-1:0] m_axis_dma_read_desc_dma_addr,
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output wire [RAM_ADDR_WIDTH-1:0] m_axis_dma_read_desc_ram_addr,
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output wire [DMA_LEN_WIDTH-1:0] m_axis_dma_read_desc_len,
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output wire [DMA_TAG_WIDTH-1:0] m_axis_dma_read_desc_tag,
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output wire m_axis_dma_read_desc_valid,
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input wire m_axis_dma_read_desc_ready,
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/*
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* DMA read descriptor status input
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*/
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input wire [DMA_TAG_WIDTH-1:0] s_axis_dma_read_desc_status_tag,
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input wire s_axis_dma_read_desc_status_valid,
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/*
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* DMA write descriptor output
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*/
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output wire [DMA_ADDR_WIDTH-1:0] m_axis_dma_write_desc_dma_addr,
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output wire [RAM_ADDR_WIDTH-1:0] m_axis_dma_write_desc_ram_addr,
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output wire [DMA_LEN_WIDTH-1:0] m_axis_dma_write_desc_len,
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output wire [DMA_TAG_WIDTH-1:0] m_axis_dma_write_desc_tag,
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output wire m_axis_dma_write_desc_valid,
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input wire m_axis_dma_write_desc_ready,
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/*
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* DMA write descriptor status input
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*/
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input wire [DMA_TAG_WIDTH-1:0] s_axis_dma_write_desc_status_tag,
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input wire s_axis_dma_write_desc_status_valid,
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/*
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* AXI-Lite slave interface
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*/
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input wire [AXIL_ADDR_WIDTH-1:0] s_axil_awaddr,
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input wire [2:0] s_axil_awprot,
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input wire s_axil_awvalid,
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output wire s_axil_awready,
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input wire [AXIL_DATA_WIDTH-1:0] s_axil_wdata,
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input wire [AXIL_STRB_WIDTH-1:0] s_axil_wstrb,
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input wire s_axil_wvalid,
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output wire s_axil_wready,
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output wire [1:0] s_axil_bresp,
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output wire s_axil_bvalid,
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input wire s_axil_bready,
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input wire [AXIL_ADDR_WIDTH-1:0] s_axil_araddr,
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input wire [2:0] s_axil_arprot,
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input wire s_axil_arvalid,
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output wire s_axil_arready,
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output wire [AXIL_DATA_WIDTH-1:0] s_axil_rdata,
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output wire [1:0] s_axil_rresp,
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output wire s_axil_rvalid,
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input wire s_axil_rready,
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/*
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* RAM interface
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*/
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input wire [SEG_COUNT*SEG_BE_WIDTH-1:0] dma_ram_wr_cmd_be,
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input wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_wr_cmd_addr,
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input wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_wr_cmd_data,
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input wire [SEG_COUNT-1:0] dma_ram_wr_cmd_valid,
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output wire [SEG_COUNT-1:0] dma_ram_wr_cmd_ready,
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input wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_rd_cmd_addr,
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input wire [SEG_COUNT-1:0] dma_ram_rd_cmd_valid,
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output wire [SEG_COUNT-1:0] dma_ram_rd_cmd_ready,
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output wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_rd_resp_data,
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output wire [SEG_COUNT-1:0] dma_ram_rd_resp_valid,
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input wire [SEG_COUNT-1:0] dma_ram_rd_resp_ready,
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/*
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* Transmit data output
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*/
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output wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata,
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output wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep,
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output wire tx_axis_tvalid,
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input wire tx_axis_tready,
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output wire tx_axis_tlast,
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output wire tx_axis_tuser,
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/*
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* Transmit PTP timestamp input
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*/
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input wire [PTP_TS_WIDTH-1:0] s_axis_tx_ptp_ts_96,
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input wire s_axis_tx_ptp_ts_valid,
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output wire s_axis_tx_ptp_ts_ready,
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/*
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* Receive data input
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*/
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input wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata,
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input wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep,
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input wire rx_axis_tvalid,
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output wire rx_axis_tready,
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input wire rx_axis_tlast,
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input wire rx_axis_tuser,
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/*
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* Receive PTP timestamp input
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*/
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input wire [PTP_TS_WIDTH-1:0] s_axis_rx_ptp_ts_96,
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input wire s_axis_rx_ptp_ts_valid,
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output wire s_axis_rx_ptp_ts_ready,
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/*
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* PTP clock
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*/
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input wire [PTP_TS_WIDTH-1:0] ptp_ts_96,
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input wire ptp_ts_step
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);
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parameter DMA_CLIENT_TAG_WIDTH = $clog2(TX_DESC_TABLE_SIZE > RX_DESC_TABLE_SIZE ? TX_DESC_TABLE_SIZE : RX_DESC_TABLE_SIZE);
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parameter DMA_CLIENT_LEN_WIDTH = DMA_LEN_WIDTH;
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parameter DESC_REQ_TAG_WIDTH_INT = DESC_REQ_TAG_WIDTH - $clog2(2);
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parameter SCHED_COUNT = (TX_SCHEDULER == "TDMA_RR") ? 2 : 1;
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parameter AXIL_SCHED_ADDR_WIDTH = AXIL_ADDR_WIDTH-$clog2(SCHED_COUNT+1);
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// parameter sizing helpers
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function [31:0] w_32(input [31:0] val);
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w_32 = val;
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endfunction
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// AXI lite connections
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wire [AXIL_ADDR_WIDTH-1:0] axil_ctrl_awaddr;
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wire [2:0] axil_ctrl_awprot;
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wire axil_ctrl_awvalid;
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wire axil_ctrl_awready;
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wire [AXIL_DATA_WIDTH-1:0] axil_ctrl_wdata;
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wire [AXIL_STRB_WIDTH-1:0] axil_ctrl_wstrb;
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wire axil_ctrl_wvalid;
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wire axil_ctrl_wready;
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wire [1:0] axil_ctrl_bresp;
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wire axil_ctrl_bvalid;
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wire axil_ctrl_bready;
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wire [AXIL_ADDR_WIDTH-1:0] axil_ctrl_araddr;
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wire [2:0] axil_ctrl_arprot;
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wire axil_ctrl_arvalid;
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wire axil_ctrl_arready;
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wire [AXIL_DATA_WIDTH-1:0] axil_ctrl_rdata;
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wire [1:0] axil_ctrl_rresp;
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wire axil_ctrl_rvalid;
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wire axil_ctrl_rready;
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wire [SCHED_COUNT*AXIL_ADDR_WIDTH-1:0] axil_sched_awaddr;
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wire [SCHED_COUNT*3-1:0] axil_sched_awprot;
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wire [SCHED_COUNT-1:0] axil_sched_awvalid;
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wire [SCHED_COUNT-1:0] axil_sched_awready;
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wire [SCHED_COUNT*AXIL_DATA_WIDTH-1:0] axil_sched_wdata;
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wire [SCHED_COUNT*AXIL_STRB_WIDTH-1:0] axil_sched_wstrb;
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wire [SCHED_COUNT-1:0] axil_sched_wvalid;
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wire [SCHED_COUNT-1:0] axil_sched_wready;
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wire [SCHED_COUNT*2-1:0] axil_sched_bresp;
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wire [SCHED_COUNT-1:0] axil_sched_bvalid;
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wire [SCHED_COUNT-1:0] axil_sched_bready;
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wire [SCHED_COUNT*AXIL_ADDR_WIDTH-1:0] axil_sched_araddr;
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wire [SCHED_COUNT*3-1:0] axil_sched_arprot;
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wire [SCHED_COUNT-1:0] axil_sched_arvalid;
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wire [SCHED_COUNT-1:0] axil_sched_arready;
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wire [SCHED_COUNT*AXIL_DATA_WIDTH-1:0] axil_sched_rdata;
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wire [SCHED_COUNT*2-1:0] axil_sched_rresp;
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wire [SCHED_COUNT-1:0] axil_sched_rvalid;
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wire [SCHED_COUNT-1:0] axil_sched_rready;
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// Checksumming
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wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata_int;
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wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep_int;
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wire tx_axis_tvalid_int;
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wire tx_axis_tready_int;
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wire tx_axis_tlast_int;
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wire tx_axis_tuser_int;
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// Descriptor and completion
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wire [0:0] rx_desc_req_sel = 1'b1;
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wire [QUEUE_INDEX_WIDTH-1:0] rx_desc_req_queue;
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wire [DESC_REQ_TAG_WIDTH_INT-1:0] rx_desc_req_tag;
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wire rx_desc_req_valid;
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wire rx_desc_req_ready;
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wire [QUEUE_INDEX_WIDTH-1:0] rx_desc_req_status_queue;
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wire [QUEUE_PTR_WIDTH-1:0] rx_desc_req_status_ptr;
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wire [CPL_QUEUE_INDEX_WIDTH-1:0] rx_desc_req_status_cpl;
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wire [DESC_REQ_TAG_WIDTH_INT-1:0] rx_desc_req_status_tag;
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wire rx_desc_req_status_empty;
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wire rx_desc_req_status_error;
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wire rx_desc_req_status_valid;
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wire [AXIS_DESC_DATA_WIDTH-1:0] rx_desc_tdata;
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wire [AXIS_DESC_KEEP_WIDTH-1:0] rx_desc_tkeep;
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wire rx_desc_tvalid;
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wire rx_desc_tready;
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wire rx_desc_tlast;
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wire [DESC_REQ_TAG_WIDTH_INT-1:0] rx_desc_tid;
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wire rx_desc_tuser;
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wire [0:0] tx_desc_req_sel = 1'b0;
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wire [QUEUE_INDEX_WIDTH-1:0] tx_desc_req_queue;
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wire [DESC_REQ_TAG_WIDTH_INT-1:0] tx_desc_req_tag;
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wire tx_desc_req_valid;
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wire tx_desc_req_ready;
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wire [QUEUE_INDEX_WIDTH-1:0] tx_desc_req_status_queue;
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wire [QUEUE_PTR_WIDTH-1:0] tx_desc_req_status_ptr;
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wire [CPL_QUEUE_INDEX_WIDTH-1:0] tx_desc_req_status_cpl;
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wire [DESC_REQ_TAG_WIDTH_INT-1:0] tx_desc_req_status_tag;
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wire tx_desc_req_status_empty;
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wire tx_desc_req_status_error;
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wire tx_desc_req_status_valid;
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wire [AXIS_DESC_DATA_WIDTH-1:0] tx_desc_tdata;
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wire [AXIS_DESC_KEEP_WIDTH-1:0] tx_desc_tkeep;
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wire tx_desc_tvalid;
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wire tx_desc_tready;
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wire tx_desc_tlast;
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wire [DESC_REQ_TAG_WIDTH_INT-1:0] tx_desc_tid;
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wire tx_desc_tuser;
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wire [0:0] rx_cpl_req_sel = 1'b1;
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wire [QUEUE_INDEX_WIDTH-1:0] rx_cpl_req_queue;
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wire [DESC_REQ_TAG_WIDTH_INT-1:0] rx_cpl_req_tag;
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wire [CPL_SIZE*8-1:0] rx_cpl_req_data;
|
|
wire rx_cpl_req_valid;
|
|
wire rx_cpl_req_ready;
|
|
|
|
wire [DESC_REQ_TAG_WIDTH_INT-1:0] rx_cpl_req_status_tag;
|
|
wire rx_cpl_req_status_full;
|
|
wire rx_cpl_req_status_error;
|
|
wire rx_cpl_req_status_valid;
|
|
|
|
wire [0:0] tx_cpl_req_sel = 1'b0;
|
|
wire [QUEUE_INDEX_WIDTH-1:0] tx_cpl_req_queue;
|
|
wire [DESC_REQ_TAG_WIDTH_INT-1:0] tx_cpl_req_tag;
|
|
wire [CPL_SIZE*8-1:0] tx_cpl_req_data;
|
|
wire tx_cpl_req_valid;
|
|
wire tx_cpl_req_ready;
|
|
|
|
wire [DESC_REQ_TAG_WIDTH_INT-1:0] tx_cpl_req_status_tag;
|
|
wire tx_cpl_req_status_full;
|
|
wire tx_cpl_req_status_error;
|
|
wire tx_cpl_req_status_valid;
|
|
|
|
// Scheduler
|
|
wire [TX_QUEUE_INDEX_WIDTH-1:0] tx_sched_ctrl_queue;
|
|
wire tx_sched_ctrl_enable;
|
|
wire tx_sched_ctrl_valid;
|
|
wire tx_sched_ctrl_ready;
|
|
|
|
// TX engine
|
|
wire [TX_QUEUE_INDEX_WIDTH-1:0] tx_req_queue;
|
|
wire [REQ_TAG_WIDTH-1:0] tx_req_tag;
|
|
wire tx_req_valid;
|
|
wire tx_req_ready;
|
|
|
|
wire [DMA_CLIENT_LEN_WIDTH-1:0] tx_req_status_len;
|
|
wire [REQ_TAG_WIDTH-1:0] tx_req_status_tag;
|
|
wire tx_req_status_valid;
|
|
|
|
// RX engine
|
|
reg rx_frame_reg = 0;
|
|
|
|
wire [RX_QUEUE_INDEX_WIDTH-1:0] rx_req_queue = 0; // TODO RSS of some form
|
|
wire [REQ_TAG_WIDTH-1:0] rx_req_tag = 0;
|
|
wire rx_req_valid = rx_axis_tvalid && !rx_frame_reg;
|
|
wire rx_req_ready;
|
|
|
|
wire [REQ_TAG_WIDTH-1:0] rx_req_status_tag;
|
|
wire rx_req_status_valid;
|
|
|
|
always @(posedge clk) begin
|
|
if (rx_axis_tready && rx_axis_tvalid) begin
|
|
rx_frame_reg <= !rx_axis_tlast;
|
|
end
|
|
|
|
if (rst) begin
|
|
rx_frame_reg <= 1'b0;
|
|
end
|
|
end
|
|
|
|
// Timestamps
|
|
wire [95:0] rx_ptp_ts_96;
|
|
wire rx_ptp_ts_valid;
|
|
wire rx_ptp_ts_ready;
|
|
|
|
wire [95:0] tx_ptp_ts_96;
|
|
wire tx_ptp_ts_valid;
|
|
wire tx_ptp_ts_ready;
|
|
|
|
// Checksums
|
|
wire [15:0] rx_csum;
|
|
wire rx_csum_valid;
|
|
|
|
wire [15:0] rx_fifo_csum;
|
|
wire rx_fifo_csum_valid;
|
|
wire rx_fifo_csum_ready;
|
|
|
|
wire tx_csum_cmd_csum_enable;
|
|
wire [7:0] tx_csum_cmd_csum_start;
|
|
wire [7:0] tx_csum_cmd_csum_offset;
|
|
wire tx_csum_cmd_valid;
|
|
wire tx_csum_cmd_ready;
|
|
|
|
wire tx_fifo_csum_cmd_csum_enable;
|
|
wire [7:0] tx_fifo_csum_cmd_csum_start;
|
|
wire [7:0] tx_fifo_csum_cmd_csum_offset;
|
|
wire tx_fifo_csum_cmd_valid;
|
|
wire tx_fifo_csum_cmd_ready;
|
|
|
|
// Interface DMA control
|
|
wire [RAM_ADDR_WIDTH-1:0] dma_tx_desc_addr;
|
|
wire [DMA_CLIENT_LEN_WIDTH-1:0] dma_tx_desc_len;
|
|
wire [DMA_CLIENT_TAG_WIDTH-1:0] dma_tx_desc_tag;
|
|
wire dma_tx_desc_user;
|
|
wire dma_tx_desc_valid;
|
|
wire dma_tx_desc_ready;
|
|
|
|
wire [DMA_CLIENT_TAG_WIDTH-1:0] dma_tx_desc_status_tag;
|
|
wire dma_tx_desc_status_valid;
|
|
|
|
wire [RAM_ADDR_WIDTH-1:0] dma_rx_desc_addr;
|
|
wire [DMA_CLIENT_LEN_WIDTH-1:0] dma_rx_desc_len;
|
|
wire [DMA_CLIENT_TAG_WIDTH-1:0] dma_rx_desc_tag;
|
|
wire dma_rx_desc_valid;
|
|
wire dma_rx_desc_ready;
|
|
|
|
wire [DMA_CLIENT_LEN_WIDTH-1:0] dma_rx_desc_status_len;
|
|
wire [DMA_CLIENT_TAG_WIDTH-1:0] dma_rx_desc_status_tag;
|
|
wire dma_rx_desc_status_user;
|
|
wire dma_rx_desc_status_valid;
|
|
|
|
wire dma_enable = 1;
|
|
|
|
// Port control registers
|
|
reg axil_ctrl_awready_reg = 1'b0;
|
|
reg axil_ctrl_wready_reg = 1'b0;
|
|
reg axil_ctrl_bvalid_reg = 1'b0;
|
|
reg axil_ctrl_arready_reg = 1'b0;
|
|
reg [AXIL_DATA_WIDTH-1:0] axil_ctrl_rdata_reg = {AXIL_DATA_WIDTH{1'b0}};
|
|
reg axil_ctrl_rvalid_reg = 1'b0;
|
|
|
|
reg sched_enable_reg = 1'b0;
|
|
|
|
reg tdma_enable_reg = 1'b0;
|
|
wire tdma_locked;
|
|
wire tdma_error;
|
|
|
|
reg [79:0] set_tdma_schedule_start_reg = 0;
|
|
reg set_tdma_schedule_start_valid_reg = 0;
|
|
reg [79:0] set_tdma_schedule_period_reg = 0;
|
|
reg set_tdma_schedule_period_valid_reg = 0;
|
|
reg [79:0] set_tdma_timeslot_period_reg = 0;
|
|
reg set_tdma_timeslot_period_valid_reg = 0;
|
|
reg [79:0] set_tdma_active_period_reg = 0;
|
|
reg set_tdma_active_period_valid_reg = 0;
|
|
|
|
wire tdma_schedule_start;
|
|
wire [TDMA_INDEX_WIDTH-1:0] tdma_timeslot_index;
|
|
wire tdma_timeslot_start;
|
|
wire tdma_timeslot_end;
|
|
wire tdma_timeslot_active;
|
|
|
|
assign axil_ctrl_awready = axil_ctrl_awready_reg;
|
|
assign axil_ctrl_wready = axil_ctrl_wready_reg;
|
|
assign axil_ctrl_bresp = 2'b00;
|
|
assign axil_ctrl_bvalid = axil_ctrl_bvalid_reg;
|
|
assign axil_ctrl_arready = axil_ctrl_arready_reg;
|
|
assign axil_ctrl_rdata = axil_ctrl_rdata_reg;
|
|
assign axil_ctrl_rresp = 2'b00;
|
|
assign axil_ctrl_rvalid = axil_ctrl_rvalid_reg;
|
|
|
|
always @(posedge clk) begin
|
|
axil_ctrl_awready_reg <= 1'b0;
|
|
axil_ctrl_wready_reg <= 1'b0;
|
|
axil_ctrl_bvalid_reg <= axil_ctrl_bvalid_reg && !axil_ctrl_bready;
|
|
axil_ctrl_arready_reg <= 1'b0;
|
|
axil_ctrl_rvalid_reg <= axil_ctrl_rvalid_reg && !axil_ctrl_rready;
|
|
|
|
set_tdma_schedule_start_valid_reg <= 1'b0;
|
|
set_tdma_schedule_period_valid_reg <= 1'b0;
|
|
set_tdma_timeslot_period_valid_reg <= 1'b0;
|
|
set_tdma_active_period_valid_reg <= 1'b0;
|
|
|
|
if (axil_ctrl_awvalid && axil_ctrl_wvalid && !axil_ctrl_bvalid) begin
|
|
// write operation
|
|
axil_ctrl_awready_reg <= 1'b1;
|
|
axil_ctrl_wready_reg <= 1'b1;
|
|
axil_ctrl_bvalid_reg <= 1'b1;
|
|
|
|
case ({axil_ctrl_awaddr[15:2], 2'b00})
|
|
16'h0040: begin
|
|
// Scheduler enable
|
|
if (axil_ctrl_wstrb[0]) begin
|
|
sched_enable_reg <= axil_ctrl_wdata[0];
|
|
end
|
|
end
|
|
16'h0100: begin
|
|
// TDMA control
|
|
if (axil_ctrl_wstrb[0]) begin
|
|
tdma_enable_reg <= axil_ctrl_wdata[0];
|
|
end
|
|
end
|
|
16'h0114: set_tdma_schedule_start_reg[29:0] <= axil_ctrl_wdata; // TDMA schedule start ns
|
|
16'h0118: set_tdma_schedule_start_reg[63:32] <= axil_ctrl_wdata; // TDMA schedule start sec l
|
|
16'h011C: begin
|
|
// TDMA schedule start sec h
|
|
set_tdma_schedule_start_reg[79:64] <= axil_ctrl_wdata;
|
|
set_tdma_schedule_start_valid_reg <= 1'b1;
|
|
end
|
|
16'h0124: set_tdma_schedule_period_reg[29:0] <= axil_ctrl_wdata; // TDMA schedule period ns
|
|
16'h0128: set_tdma_schedule_period_reg[63:32] <= axil_ctrl_wdata; // TDMA schedule period sec l
|
|
16'h012C: begin
|
|
// TDMA schedule period sec h
|
|
set_tdma_schedule_period_reg[79:64] <= axil_ctrl_wdata;
|
|
set_tdma_schedule_period_valid_reg <= 1'b1;
|
|
end
|
|
16'h0134: set_tdma_timeslot_period_reg[29:0] <= axil_ctrl_wdata; // TDMA timeslot period ns
|
|
16'h0138: set_tdma_timeslot_period_reg[63:32] <= axil_ctrl_wdata; // TDMA timeslot period sec l
|
|
16'h013C: begin
|
|
// TDMA timeslot period sec h
|
|
set_tdma_timeslot_period_reg[79:64] <= axil_ctrl_wdata;
|
|
set_tdma_timeslot_period_valid_reg <= 1'b1;
|
|
end
|
|
16'h0144: set_tdma_active_period_reg[29:0] <= axil_ctrl_wdata; // TDMA active period ns
|
|
16'h0148: set_tdma_active_period_reg[63:32] <= axil_ctrl_wdata; // TDMA active period sec l
|
|
16'h014C: begin
|
|
// TDMA active period sec h
|
|
set_tdma_active_period_reg[79:64] <= axil_ctrl_wdata;
|
|
set_tdma_active_period_valid_reg <= 1'b1;
|
|
end
|
|
endcase
|
|
end
|
|
|
|
if (axil_ctrl_arvalid && !axil_ctrl_rvalid) begin
|
|
// read operation
|
|
axil_ctrl_arready_reg <= 1'b1;
|
|
axil_ctrl_rvalid_reg <= 1'b1;
|
|
axil_ctrl_rdata_reg <= {AXIL_DATA_WIDTH{1'b0}};
|
|
|
|
case ({axil_ctrl_araddr[15:2], 2'b00})
|
|
16'h0000: axil_ctrl_rdata_reg <= 32'd0; // port_id
|
|
16'h0004: begin
|
|
// port_features
|
|
axil_ctrl_rdata_reg[4] <= PTP_TS_ENABLE;
|
|
axil_ctrl_rdata_reg[8] <= TX_CHECKSUM_ENABLE;
|
|
axil_ctrl_rdata_reg[9] <= RX_CHECKSUM_ENABLE;
|
|
end
|
|
16'h0010: axil_ctrl_rdata_reg <= SCHED_COUNT; // scheduler_count
|
|
16'h0014: axil_ctrl_rdata_reg <= 2**AXIL_SCHED_ADDR_WIDTH; // scheduler_offset
|
|
16'h0018: axil_ctrl_rdata_reg <= 2**AXIL_SCHED_ADDR_WIDTH; // scheduler_stride
|
|
16'h001C: axil_ctrl_rdata_reg <= 32'd0; // scheduler_type
|
|
16'h0040: begin
|
|
// Scheduler enable
|
|
axil_ctrl_rdata_reg[0] <= sched_enable_reg;
|
|
end
|
|
16'h0100: begin
|
|
// TDMA control
|
|
axil_ctrl_rdata_reg[0] <= tdma_enable_reg;
|
|
end
|
|
16'h0104: begin
|
|
// TDMA status
|
|
axil_ctrl_rdata_reg[0] <= tdma_locked;
|
|
axil_ctrl_rdata_reg[1] <= tdma_error;
|
|
end
|
|
16'h0108: axil_ctrl_rdata_reg <= 2**TDMA_INDEX_WIDTH; // TDMA timeslot count
|
|
16'h0114: axil_ctrl_rdata_reg <= set_tdma_schedule_start_reg[29:0]; // TDMA schedule start ns
|
|
16'h0118: axil_ctrl_rdata_reg <= set_tdma_schedule_start_reg[63:32]; // TDMA schedule start sec l
|
|
16'h011C: axil_ctrl_rdata_reg <= set_tdma_schedule_start_reg[79:64]; // TDMA schedule start sec h
|
|
16'h0124: axil_ctrl_rdata_reg <= set_tdma_schedule_period_reg[29:0]; // TDMA schedule period ns
|
|
16'h0128: axil_ctrl_rdata_reg <= set_tdma_schedule_period_reg[63:32]; // TDMA schedule period sec l
|
|
16'h012C: axil_ctrl_rdata_reg <= set_tdma_schedule_period_reg[79:64]; // TDMA schedule period sec h
|
|
16'h0134: axil_ctrl_rdata_reg <= set_tdma_timeslot_period_reg[29:0]; // TDMA timeslot period ns
|
|
16'h0138: axil_ctrl_rdata_reg <= set_tdma_timeslot_period_reg[63:32]; // TDMA timeslot period sec l
|
|
16'h013C: axil_ctrl_rdata_reg <= set_tdma_timeslot_period_reg[79:64]; // TDMA timeslot period sec h
|
|
16'h0144: axil_ctrl_rdata_reg <= set_tdma_active_period_reg[29:0]; // TDMA active period ns
|
|
16'h0148: axil_ctrl_rdata_reg <= set_tdma_active_period_reg[63:32]; // TDMA active period sec l
|
|
16'h014C: axil_ctrl_rdata_reg <= set_tdma_active_period_reg[79:64]; // TDMA active period sec h
|
|
endcase
|
|
end
|
|
|
|
if (rst) begin
|
|
axil_ctrl_awready_reg <= 1'b0;
|
|
axil_ctrl_wready_reg <= 1'b0;
|
|
axil_ctrl_bvalid_reg <= 1'b0;
|
|
axil_ctrl_arready_reg <= 1'b0;
|
|
axil_ctrl_rvalid_reg <= 1'b0;
|
|
|
|
sched_enable_reg <= 1'b0;
|
|
tdma_enable_reg <= 1'b0;
|
|
end
|
|
end
|
|
|
|
// AXI lite interconnect
|
|
parameter AXIL_S_COUNT = 1;
|
|
parameter AXIL_M_COUNT = SCHED_COUNT+1;
|
|
|
|
axil_interconnect #(
|
|
.DATA_WIDTH(AXIL_DATA_WIDTH),
|
|
.ADDR_WIDTH(AXIL_ADDR_WIDTH),
|
|
.STRB_WIDTH(AXIL_STRB_WIDTH),
|
|
.S_COUNT(AXIL_S_COUNT),
|
|
.M_COUNT(AXIL_M_COUNT),
|
|
.M_ADDR_WIDTH({AXIL_M_COUNT{w_32(AXIL_SCHED_ADDR_WIDTH)}}),
|
|
.M_CONNECT_READ({AXIL_M_COUNT{{AXIL_S_COUNT{1'b1}}}}),
|
|
.M_CONNECT_WRITE({AXIL_M_COUNT{{AXIL_S_COUNT{1'b1}}}})
|
|
)
|
|
axil_interconnect_inst (
|
|
.clk(clk),
|
|
.rst(rst),
|
|
.s_axil_awaddr(s_axil_awaddr),
|
|
.s_axil_awprot(s_axil_awprot),
|
|
.s_axil_awvalid(s_axil_awvalid),
|
|
.s_axil_awready(s_axil_awready),
|
|
.s_axil_wdata(s_axil_wdata),
|
|
.s_axil_wstrb(s_axil_wstrb),
|
|
.s_axil_wvalid(s_axil_wvalid),
|
|
.s_axil_wready(s_axil_wready),
|
|
.s_axil_bresp(s_axil_bresp),
|
|
.s_axil_bvalid(s_axil_bvalid),
|
|
.s_axil_bready(s_axil_bready),
|
|
.s_axil_araddr(s_axil_araddr),
|
|
.s_axil_arprot(s_axil_arprot),
|
|
.s_axil_arvalid(s_axil_arvalid),
|
|
.s_axil_arready(s_axil_arready),
|
|
.s_axil_rdata(s_axil_rdata),
|
|
.s_axil_rresp(s_axil_rresp),
|
|
.s_axil_rvalid(s_axil_rvalid),
|
|
.s_axil_rready(s_axil_rready),
|
|
.m_axil_awaddr( {axil_sched_awaddr, axil_ctrl_awaddr}),
|
|
.m_axil_awprot( {axil_sched_awprot, axil_ctrl_awprot}),
|
|
.m_axil_awvalid({axil_sched_awvalid, axil_ctrl_awvalid}),
|
|
.m_axil_awready({axil_sched_awready, axil_ctrl_awready}),
|
|
.m_axil_wdata( {axil_sched_wdata, axil_ctrl_wdata}),
|
|
.m_axil_wstrb( {axil_sched_wstrb, axil_ctrl_wstrb}),
|
|
.m_axil_wvalid( {axil_sched_wvalid, axil_ctrl_wvalid}),
|
|
.m_axil_wready( {axil_sched_wready, axil_ctrl_wready}),
|
|
.m_axil_bresp( {axil_sched_bresp, axil_ctrl_bresp}),
|
|
.m_axil_bvalid( {axil_sched_bvalid, axil_ctrl_bvalid}),
|
|
.m_axil_bready( {axil_sched_bready, axil_ctrl_bready}),
|
|
.m_axil_araddr( {axil_sched_araddr, axil_ctrl_araddr}),
|
|
.m_axil_arprot( {axil_sched_arprot, axil_ctrl_arprot}),
|
|
.m_axil_arvalid({axil_sched_arvalid, axil_ctrl_arvalid}),
|
|
.m_axil_arready({axil_sched_arready, axil_ctrl_arready}),
|
|
.m_axil_rdata( {axil_sched_rdata, axil_ctrl_rdata}),
|
|
.m_axil_rresp( {axil_sched_rresp, axil_ctrl_rresp}),
|
|
.m_axil_rvalid( {axil_sched_rvalid, axil_ctrl_rvalid}),
|
|
.m_axil_rready( {axil_sched_rready, axil_ctrl_rready})
|
|
);
|
|
|
|
desc_op_mux #(
|
|
.PORTS(2),
|
|
.SELECT_WIDTH(1),
|
|
.QUEUE_INDEX_WIDTH(QUEUE_INDEX_WIDTH),
|
|
.QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH),
|
|
.CPL_QUEUE_INDEX_WIDTH(CPL_QUEUE_INDEX_WIDTH),
|
|
.S_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH_INT),
|
|
.M_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH),
|
|
.AXIS_DATA_WIDTH(AXIS_DESC_DATA_WIDTH),
|
|
.AXIS_KEEP_WIDTH(AXIS_DESC_KEEP_WIDTH),
|
|
.ARB_TYPE("ROUND_ROBIN"),
|
|
.LSB_PRIORITY("HIGH")
|
|
)
|
|
desc_op_mux_inst (
|
|
.clk(clk),
|
|
.rst(rst),
|
|
|
|
/*
|
|
* Descriptor request output
|
|
*/
|
|
.m_axis_req_sel(m_axis_desc_req_sel),
|
|
.m_axis_req_queue(m_axis_desc_req_queue),
|
|
.m_axis_req_tag(m_axis_desc_req_tag),
|
|
.m_axis_req_valid(m_axis_desc_req_valid),
|
|
.m_axis_req_ready(m_axis_desc_req_ready),
|
|
|
|
/*
|
|
* Descriptor request status input
|
|
*/
|
|
.s_axis_req_status_queue(s_axis_desc_req_status_queue),
|
|
.s_axis_req_status_ptr(s_axis_desc_req_status_ptr),
|
|
.s_axis_req_status_cpl(s_axis_desc_req_status_cpl),
|
|
.s_axis_req_status_tag(s_axis_desc_req_status_tag),
|
|
.s_axis_req_status_empty(s_axis_desc_req_status_empty),
|
|
.s_axis_req_status_error(s_axis_desc_req_status_error),
|
|
.s_axis_req_status_valid(s_axis_desc_req_status_valid),
|
|
|
|
/*
|
|
* Descriptor data input
|
|
*/
|
|
.s_axis_desc_tdata(s_axis_desc_tdata),
|
|
.s_axis_desc_tkeep(s_axis_desc_tkeep),
|
|
.s_axis_desc_tvalid(s_axis_desc_tvalid),
|
|
.s_axis_desc_tready(s_axis_desc_tready),
|
|
.s_axis_desc_tlast(s_axis_desc_tlast),
|
|
.s_axis_desc_tid(s_axis_desc_tid),
|
|
.s_axis_desc_tuser(s_axis_desc_tuser),
|
|
|
|
/*
|
|
* Descriptor request input
|
|
*/
|
|
.s_axis_req_sel({rx_desc_req_sel, tx_desc_req_sel}),
|
|
.s_axis_req_queue({rx_desc_req_queue, tx_desc_req_queue}),
|
|
.s_axis_req_tag({rx_desc_req_tag, tx_desc_req_tag}),
|
|
.s_axis_req_valid({rx_desc_req_valid, tx_desc_req_valid}),
|
|
.s_axis_req_ready({rx_desc_req_ready, tx_desc_req_ready}),
|
|
|
|
/*
|
|
* Descriptor response output
|
|
*/
|
|
.m_axis_req_status_queue({rx_desc_req_status_queue, tx_desc_req_status_queue}),
|
|
.m_axis_req_status_ptr({rx_desc_req_status_ptr, tx_desc_req_status_ptr}),
|
|
.m_axis_req_status_cpl({rx_desc_req_status_cpl, tx_desc_req_status_cpl}),
|
|
.m_axis_req_status_tag({rx_desc_req_status_tag, tx_desc_req_status_tag}),
|
|
.m_axis_req_status_empty({rx_desc_req_status_empty, tx_desc_req_status_empty}),
|
|
.m_axis_req_status_error({rx_desc_req_status_error, tx_desc_req_status_error}),
|
|
.m_axis_req_status_valid({rx_desc_req_status_valid, tx_desc_req_status_valid}),
|
|
|
|
/*
|
|
* Descriptor data output
|
|
*/
|
|
.m_axis_desc_tdata({rx_desc_tdata, tx_desc_tdata}),
|
|
.m_axis_desc_tkeep({rx_desc_tkeep, tx_desc_tkeep}),
|
|
.m_axis_desc_tvalid({rx_desc_tvalid, tx_desc_tvalid}),
|
|
.m_axis_desc_tready({rx_desc_tready, tx_desc_tready}),
|
|
.m_axis_desc_tlast({rx_desc_tlast, tx_desc_tlast}),
|
|
.m_axis_desc_tid({rx_desc_tid, tx_desc_tid}),
|
|
.m_axis_desc_tuser({rx_desc_tuser, tx_desc_tuser})
|
|
);
|
|
|
|
cpl_op_mux #(
|
|
.PORTS(2),
|
|
.SELECT_WIDTH(1),
|
|
.QUEUE_INDEX_WIDTH(QUEUE_INDEX_WIDTH),
|
|
.S_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH_INT),
|
|
.M_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH),
|
|
.CPL_SIZE(CPL_SIZE),
|
|
.ARB_TYPE("ROUND_ROBIN"),
|
|
.LSB_PRIORITY("HIGH")
|
|
)
|
|
cpl_op_mux_inst (
|
|
.clk(clk),
|
|
.rst(rst),
|
|
|
|
/*
|
|
* Completion request output
|
|
*/
|
|
.m_axis_req_sel(m_axis_cpl_req_sel),
|
|
.m_axis_req_queue(m_axis_cpl_req_queue),
|
|
.m_axis_req_tag(m_axis_cpl_req_tag),
|
|
.m_axis_req_data(m_axis_cpl_req_data),
|
|
.m_axis_req_valid(m_axis_cpl_req_valid),
|
|
.m_axis_req_ready(m_axis_cpl_req_ready),
|
|
|
|
/*
|
|
* Completion request status input
|
|
*/
|
|
.s_axis_req_status_tag(s_axis_cpl_req_status_tag),
|
|
.s_axis_req_status_full(s_axis_cpl_req_status_full),
|
|
.s_axis_req_status_error(s_axis_cpl_req_status_error),
|
|
.s_axis_req_status_valid(s_axis_cpl_req_status_valid),
|
|
|
|
/*
|
|
* Completion request input
|
|
*/
|
|
.s_axis_req_sel({rx_cpl_req_sel, tx_cpl_req_sel}),
|
|
.s_axis_req_queue({rx_cpl_req_queue, tx_cpl_req_queue}),
|
|
.s_axis_req_tag({rx_cpl_req_tag, tx_cpl_req_tag}),
|
|
.s_axis_req_data({rx_cpl_req_data, tx_cpl_req_data}),
|
|
.s_axis_req_valid({rx_cpl_req_valid, tx_cpl_req_valid}),
|
|
.s_axis_req_ready({rx_cpl_req_ready, tx_cpl_req_ready}),
|
|
|
|
/*
|
|
* Completion response output
|
|
*/
|
|
.m_axis_req_status_tag({rx_cpl_req_status_tag, tx_cpl_req_status_tag}),
|
|
.m_axis_req_status_full({rx_cpl_req_status_full, tx_cpl_req_status_full}),
|
|
.m_axis_req_status_error({rx_cpl_req_status_error, tx_cpl_req_status_error}),
|
|
.m_axis_req_status_valid({rx_cpl_req_status_valid, tx_cpl_req_status_valid})
|
|
);
|
|
|
|
generate
|
|
|
|
if (TX_SCHEDULER == "RR" || TX_SCHEDULER == "TDMA_RR") begin
|
|
|
|
tx_scheduler_rr #(
|
|
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
|
|
.AXIL_ADDR_WIDTH(AXIL_SCHED_ADDR_WIDTH),
|
|
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
|
|
.DMA_CLIENT_LEN_WIDTH(DMA_CLIENT_LEN_WIDTH),
|
|
.REQ_TAG_WIDTH(REQ_TAG_WIDTH),
|
|
.OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
|
|
.QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
|
|
.PIPELINE(3),
|
|
.SCHED_CTRL_ENABLE(TX_SCHEDULER == "TDMA_RR")
|
|
)
|
|
tx_scheduler_inst (
|
|
.clk(clk),
|
|
.rst(rst),
|
|
|
|
/*
|
|
* Transmit request output (queue index)
|
|
*/
|
|
.m_axis_tx_req_queue(tx_req_queue),
|
|
.m_axis_tx_req_tag(tx_req_tag),
|
|
.m_axis_tx_req_valid(tx_req_valid),
|
|
.m_axis_tx_req_ready(tx_req_ready),
|
|
|
|
/*
|
|
* Transmit request status input
|
|
*/
|
|
.s_axis_tx_req_status_len(tx_req_status_len),
|
|
.s_axis_tx_req_status_tag(tx_req_status_tag),
|
|
.s_axis_tx_req_status_valid(tx_req_status_valid),
|
|
|
|
/*
|
|
* Doorbell input
|
|
*/
|
|
.s_axis_doorbell_queue(s_axis_tx_doorbell_queue),
|
|
.s_axis_doorbell_valid(s_axis_tx_doorbell_valid),
|
|
|
|
/*
|
|
* Scheduler control input
|
|
*/
|
|
.s_axis_sched_ctrl_queue(tx_sched_ctrl_queue),
|
|
.s_axis_sched_ctrl_enable(tx_sched_ctrl_enable),
|
|
.s_axis_sched_ctrl_valid(tx_sched_ctrl_valid),
|
|
.s_axis_sched_ctrl_ready(tx_sched_ctrl_ready),
|
|
|
|
/*
|
|
* AXI-Lite slave interface
|
|
*/
|
|
.s_axil_awaddr(axil_sched_awaddr[0*AXIL_ADDR_WIDTH +: AXIL_ADDR_WIDTH]),
|
|
.s_axil_awprot(axil_sched_awprot[0*3 +: 3]),
|
|
.s_axil_awvalid(axil_sched_awvalid[0*1 +: 1]),
|
|
.s_axil_awready(axil_sched_awready[0*1 +: 1]),
|
|
.s_axil_wdata(axil_sched_wdata[0*AXIL_DATA_WIDTH +: AXIL_DATA_WIDTH]),
|
|
.s_axil_wstrb(axil_sched_wstrb[0*AXIL_STRB_WIDTH +: AXIL_STRB_WIDTH]),
|
|
.s_axil_wvalid(axil_sched_wvalid[0*1 +: 1]),
|
|
.s_axil_wready(axil_sched_wready[0*1 +: 1]),
|
|
.s_axil_bresp(axil_sched_bresp[0*2 +: 2]),
|
|
.s_axil_bvalid(axil_sched_bvalid[0*1 +: 1]),
|
|
.s_axil_bready(axil_sched_bready[0*1 +: 1]),
|
|
.s_axil_araddr(axil_sched_araddr[0*AXIL_ADDR_WIDTH +: AXIL_ADDR_WIDTH]),
|
|
.s_axil_arprot(axil_sched_arprot[0*3 +: 3]),
|
|
.s_axil_arvalid(axil_sched_arvalid[0*1 +: 1]),
|
|
.s_axil_arready(axil_sched_arready[0*1 +: 1]),
|
|
.s_axil_rdata(axil_sched_rdata[0*AXIL_DATA_WIDTH +: AXIL_DATA_WIDTH]),
|
|
.s_axil_rresp(axil_sched_rresp[0*2 +: 2]),
|
|
.s_axil_rvalid(axil_sched_rvalid[0*1 +: 1]),
|
|
.s_axil_rready(axil_sched_rready[0*1 +: 1]),
|
|
|
|
/*
|
|
* Control
|
|
*/
|
|
.enable(sched_enable_reg),
|
|
.active()
|
|
);
|
|
|
|
end
|
|
|
|
if (TX_SCHEDULER == "TDMA_RR") begin
|
|
|
|
tdma_scheduler #(
|
|
.INDEX_WIDTH(TDMA_INDEX_WIDTH),
|
|
.SCHEDULE_START_S(48'h0),
|
|
.SCHEDULE_START_NS(30'h0),
|
|
.SCHEDULE_PERIOD_S(48'd0),
|
|
.SCHEDULE_PERIOD_NS(30'd1000000),
|
|
.TIMESLOT_PERIOD_S(48'd0),
|
|
.TIMESLOT_PERIOD_NS(30'd100000),
|
|
.ACTIVE_PERIOD_S(48'd0),
|
|
.ACTIVE_PERIOD_NS(30'd100000)
|
|
)
|
|
tdma_scheduler_inst (
|
|
.clk(clk),
|
|
.rst(rst),
|
|
.input_ts_96(ptp_ts_96),
|
|
.input_ts_step(ptp_ts_step),
|
|
.enable(tdma_enable_reg),
|
|
.input_schedule_start(set_tdma_schedule_start_reg),
|
|
.input_schedule_start_valid(set_tdma_schedule_start_valid_reg),
|
|
.input_schedule_period(set_tdma_schedule_period_reg),
|
|
.input_schedule_period_valid(set_tdma_schedule_period_valid_reg),
|
|
.input_timeslot_period(set_tdma_timeslot_period_reg),
|
|
.input_timeslot_period_valid(set_tdma_timeslot_period_valid_reg),
|
|
.input_active_period(set_tdma_active_period_reg),
|
|
.input_active_period_valid(set_tdma_active_period_valid_reg),
|
|
.locked(tdma_locked),
|
|
.error(tdma_error),
|
|
.schedule_start(tdma_schedule_start),
|
|
.timeslot_index(tdma_timeslot_index),
|
|
.timeslot_start(tdma_timeslot_start),
|
|
.timeslot_end(tdma_timeslot_end),
|
|
.timeslot_active(tdma_timeslot_active)
|
|
);
|
|
|
|
tx_scheduler_ctrl_tdma #(
|
|
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
|
|
.AXIL_ADDR_WIDTH(AXIL_SCHED_ADDR_WIDTH),
|
|
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
|
|
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
|
|
.QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
|
|
.PIPELINE(2)
|
|
)
|
|
tx_scheduler_ctrl_tdma_inst (
|
|
.clk(clk),
|
|
.rst(rst),
|
|
|
|
/*
|
|
* Scheduler control output
|
|
*/
|
|
.m_axis_sched_ctrl_queue(tx_sched_ctrl_queue),
|
|
.m_axis_sched_ctrl_enable(tx_sched_ctrl_enable),
|
|
.m_axis_sched_ctrl_valid(tx_sched_ctrl_valid),
|
|
.m_axis_sched_ctrl_ready(tx_sched_ctrl_ready),
|
|
|
|
/*
|
|
* AXI-Lite slave interface
|
|
*/
|
|
.s_axil_awaddr(axil_sched_awaddr[1*AXIL_ADDR_WIDTH +: AXIL_ADDR_WIDTH]),
|
|
.s_axil_awprot(axil_sched_awprot[1*3 +: 3]),
|
|
.s_axil_awvalid(axil_sched_awvalid[1*1 +: 1]),
|
|
.s_axil_awready(axil_sched_awready[1*1 +: 1]),
|
|
.s_axil_wdata(axil_sched_wdata[1*AXIL_DATA_WIDTH +: AXIL_DATA_WIDTH]),
|
|
.s_axil_wstrb(axil_sched_wstrb[1*AXIL_STRB_WIDTH +: AXIL_STRB_WIDTH]),
|
|
.s_axil_wvalid(axil_sched_wvalid[1*1 +: 1]),
|
|
.s_axil_wready(axil_sched_wready[1*1 +: 1]),
|
|
.s_axil_bresp(axil_sched_bresp[1*2 +: 2]),
|
|
.s_axil_bvalid(axil_sched_bvalid[1*1 +: 1]),
|
|
.s_axil_bready(axil_sched_bready[1*1 +: 1]),
|
|
.s_axil_araddr(axil_sched_araddr[1*AXIL_ADDR_WIDTH +: AXIL_ADDR_WIDTH]),
|
|
.s_axil_arprot(axil_sched_arprot[1*3 +: 3]),
|
|
.s_axil_arvalid(axil_sched_arvalid[1*1 +: 1]),
|
|
.s_axil_arready(axil_sched_arready[1*1 +: 1]),
|
|
.s_axil_rdata(axil_sched_rdata[1*AXIL_DATA_WIDTH +: AXIL_DATA_WIDTH]),
|
|
.s_axil_rresp(axil_sched_rresp[1*2 +: 2]),
|
|
.s_axil_rvalid(axil_sched_rvalid[1*1 +: 1]),
|
|
.s_axil_rready(axil_sched_rready[1*1 +: 1]),
|
|
|
|
/*
|
|
* TDMA schedule inputs
|
|
*/
|
|
.tdma_schedule_start(tdma_schedule_start),
|
|
.tdma_timeslot_index(tdma_timeslot_index),
|
|
.tdma_timeslot_start(tdma_timeslot_start),
|
|
.tdma_timeslot_end(tdma_timeslot_end),
|
|
.tdma_timeslot_active(tdma_timeslot_active)
|
|
);
|
|
|
|
end
|
|
|
|
endgenerate
|
|
|
|
tx_engine #(
|
|
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
|
|
.DMA_ADDR_WIDTH(DMA_ADDR_WIDTH),
|
|
.DMA_LEN_WIDTH(DMA_LEN_WIDTH),
|
|
.DMA_CLIENT_LEN_WIDTH(DMA_CLIENT_LEN_WIDTH),
|
|
.REQ_TAG_WIDTH(REQ_TAG_WIDTH),
|
|
.DESC_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH_INT),
|
|
.DMA_TAG_WIDTH(DMA_TAG_WIDTH),
|
|
.DMA_CLIENT_TAG_WIDTH(DMA_CLIENT_TAG_WIDTH),
|
|
.QUEUE_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH),
|
|
.QUEUE_OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH),
|
|
.QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
|
|
.QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH),
|
|
.CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
|
|
.DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
|
|
.PKT_TABLE_SIZE(TX_PKT_TABLE_SIZE),
|
|
.MAX_TX_SIZE(MAX_TX_SIZE),
|
|
.DESC_SIZE(DESC_SIZE),
|
|
.CPL_SIZE(CPL_SIZE),
|
|
.AXIS_DESC_DATA_WIDTH(AXIS_DESC_DATA_WIDTH),
|
|
.AXIS_DESC_KEEP_WIDTH(AXIS_DESC_KEEP_WIDTH),
|
|
.PTP_TS_ENABLE(PTP_TS_ENABLE),
|
|
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE)
|
|
)
|
|
tx_engine_inst (
|
|
.clk(clk),
|
|
.rst(rst),
|
|
|
|
/*
|
|
* Transmit request input (queue index)
|
|
*/
|
|
.s_axis_tx_req_queue(tx_req_queue),
|
|
.s_axis_tx_req_tag(tx_req_tag),
|
|
.s_axis_tx_req_valid(tx_req_valid),
|
|
.s_axis_tx_req_ready(tx_req_ready),
|
|
|
|
/*
|
|
* Transmit request status output
|
|
*/
|
|
.m_axis_tx_req_status_len(tx_req_status_len),
|
|
.m_axis_tx_req_status_tag(tx_req_status_tag),
|
|
.m_axis_tx_req_status_valid(tx_req_status_valid),
|
|
|
|
/*
|
|
* Descriptor request output
|
|
*/
|
|
.m_axis_desc_req_queue(tx_desc_req_queue),
|
|
.m_axis_desc_req_tag(tx_desc_req_tag),
|
|
.m_axis_desc_req_valid(tx_desc_req_valid),
|
|
.m_axis_desc_req_ready(tx_desc_req_ready),
|
|
|
|
/*
|
|
* Descriptor request status input
|
|
*/
|
|
.s_axis_desc_req_status_queue(tx_desc_req_status_queue),
|
|
.s_axis_desc_req_status_ptr(tx_desc_req_status_ptr),
|
|
.s_axis_desc_req_status_cpl(tx_desc_req_status_cpl),
|
|
.s_axis_desc_req_status_tag(tx_desc_req_status_tag),
|
|
.s_axis_desc_req_status_empty(tx_desc_req_status_empty),
|
|
.s_axis_desc_req_status_error(tx_desc_req_status_error),
|
|
.s_axis_desc_req_status_valid(tx_desc_req_status_valid),
|
|
|
|
/*
|
|
* Descriptor data input
|
|
*/
|
|
.s_axis_desc_tdata(tx_desc_tdata),
|
|
.s_axis_desc_tkeep(tx_desc_tkeep),
|
|
.s_axis_desc_tvalid(tx_desc_tvalid),
|
|
.s_axis_desc_tready(tx_desc_tready),
|
|
.s_axis_desc_tlast(tx_desc_tlast),
|
|
.s_axis_desc_tid(tx_desc_tid),
|
|
.s_axis_desc_tuser(tx_desc_tuser),
|
|
|
|
/*
|
|
* Completion request output
|
|
*/
|
|
.m_axis_cpl_req_queue(tx_cpl_req_queue),
|
|
.m_axis_cpl_req_tag(tx_cpl_req_tag),
|
|
.m_axis_cpl_req_data(tx_cpl_req_data),
|
|
.m_axis_cpl_req_valid(tx_cpl_req_valid),
|
|
.m_axis_cpl_req_ready(tx_cpl_req_ready),
|
|
|
|
/*
|
|
* Completion request status input
|
|
*/
|
|
.s_axis_cpl_req_status_tag(tx_cpl_req_status_tag),
|
|
.s_axis_cpl_req_status_full(tx_cpl_req_status_full),
|
|
.s_axis_cpl_req_status_error(tx_cpl_req_status_error),
|
|
.s_axis_cpl_req_status_valid(tx_cpl_req_status_valid),
|
|
|
|
/*
|
|
* DMA read descriptor output
|
|
*/
|
|
.m_axis_dma_read_desc_dma_addr(m_axis_dma_read_desc_dma_addr),
|
|
.m_axis_dma_read_desc_ram_addr(m_axis_dma_read_desc_ram_addr),
|
|
.m_axis_dma_read_desc_len(m_axis_dma_read_desc_len),
|
|
.m_axis_dma_read_desc_tag(m_axis_dma_read_desc_tag),
|
|
.m_axis_dma_read_desc_valid(m_axis_dma_read_desc_valid),
|
|
.m_axis_dma_read_desc_ready(m_axis_dma_read_desc_ready),
|
|
|
|
/*
|
|
* DMA read descriptor status input
|
|
*/
|
|
.s_axis_dma_read_desc_status_tag(s_axis_dma_read_desc_status_tag),
|
|
.s_axis_dma_read_desc_status_valid(s_axis_dma_read_desc_status_valid),
|
|
|
|
/*
|
|
* Transmit descriptor output
|
|
*/
|
|
.m_axis_tx_desc_addr(dma_tx_desc_addr),
|
|
.m_axis_tx_desc_len(dma_tx_desc_len),
|
|
.m_axis_tx_desc_tag(dma_tx_desc_tag),
|
|
.m_axis_tx_desc_user(dma_tx_desc_user),
|
|
.m_axis_tx_desc_valid(dma_tx_desc_valid),
|
|
.m_axis_tx_desc_ready(dma_tx_desc_ready),
|
|
|
|
/*
|
|
* Transmit descriptor status input
|
|
*/
|
|
.s_axis_tx_desc_status_tag(dma_tx_desc_status_tag),
|
|
.s_axis_tx_desc_status_valid(dma_tx_desc_status_valid),
|
|
|
|
/*
|
|
* Transmit checksum command output
|
|
*/
|
|
.m_axis_tx_csum_cmd_csum_enable(tx_csum_cmd_csum_enable),
|
|
.m_axis_tx_csum_cmd_csum_start(tx_csum_cmd_csum_start),
|
|
.m_axis_tx_csum_cmd_csum_offset(tx_csum_cmd_csum_offset),
|
|
.m_axis_tx_csum_cmd_valid(tx_csum_cmd_valid),
|
|
.m_axis_tx_csum_cmd_ready(tx_csum_cmd_ready),
|
|
|
|
/*
|
|
* Transmit timestamp input
|
|
*/
|
|
.s_axis_tx_ptp_ts_96(s_axis_tx_ptp_ts_96),
|
|
.s_axis_tx_ptp_ts_valid(s_axis_tx_ptp_ts_valid),
|
|
.s_axis_tx_ptp_ts_ready(s_axis_tx_ptp_ts_ready),
|
|
|
|
/*
|
|
* Configuration
|
|
*/
|
|
.enable(1'b1)
|
|
);
|
|
|
|
rx_engine #(
|
|
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
|
|
.DMA_ADDR_WIDTH(DMA_ADDR_WIDTH),
|
|
.DMA_LEN_WIDTH(DMA_LEN_WIDTH),
|
|
.DMA_CLIENT_LEN_WIDTH(DMA_CLIENT_LEN_WIDTH),
|
|
.REQ_TAG_WIDTH(REQ_TAG_WIDTH),
|
|
.DESC_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH_INT),
|
|
.DMA_TAG_WIDTH(DMA_TAG_WIDTH),
|
|
.DMA_CLIENT_TAG_WIDTH(DMA_CLIENT_TAG_WIDTH),
|
|
.QUEUE_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH),
|
|
.QUEUE_OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH),
|
|
.QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
|
|
.QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH),
|
|
.CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
|
|
.DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
|
|
.MAX_RX_SIZE(MAX_RX_SIZE),
|
|
.DESC_SIZE(DESC_SIZE),
|
|
.CPL_SIZE(CPL_SIZE),
|
|
.AXIS_DESC_DATA_WIDTH(AXIS_DESC_DATA_WIDTH),
|
|
.AXIS_DESC_KEEP_WIDTH(AXIS_DESC_KEEP_WIDTH),
|
|
.PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE),
|
|
.PTP_TS_ENABLE(PTP_TS_ENABLE),
|
|
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE)
|
|
)
|
|
rx_engine_inst (
|
|
.clk(clk),
|
|
.rst(rst),
|
|
|
|
/*
|
|
* Receive request input (queue index)
|
|
*/
|
|
.s_axis_rx_req_queue(rx_req_queue),
|
|
.s_axis_rx_req_tag(rx_req_tag),
|
|
.s_axis_rx_req_valid(rx_req_valid),
|
|
.s_axis_rx_req_ready(rx_req_ready),
|
|
|
|
/*
|
|
* Receive request status output
|
|
*/
|
|
.m_axis_rx_req_status_tag(rx_req_status_tag),
|
|
.m_axis_rx_req_status_valid(rx_req_status_valid),
|
|
|
|
/*
|
|
* Descriptor request output
|
|
*/
|
|
.m_axis_desc_req_queue(rx_desc_req_queue),
|
|
.m_axis_desc_req_tag(rx_desc_req_tag),
|
|
.m_axis_desc_req_valid(rx_desc_req_valid),
|
|
.m_axis_desc_req_ready(rx_desc_req_ready),
|
|
|
|
/*
|
|
* Descriptor request status input
|
|
*/
|
|
.s_axis_desc_req_status_queue(rx_desc_req_status_queue),
|
|
.s_axis_desc_req_status_ptr(rx_desc_req_status_ptr),
|
|
.s_axis_desc_req_status_cpl(rx_desc_req_status_cpl),
|
|
.s_axis_desc_req_status_tag(rx_desc_req_status_tag),
|
|
.s_axis_desc_req_status_empty(rx_desc_req_status_empty),
|
|
.s_axis_desc_req_status_error(rx_desc_req_status_error),
|
|
.s_axis_desc_req_status_valid(rx_desc_req_status_valid),
|
|
|
|
/*
|
|
* Descriptor data input
|
|
*/
|
|
.s_axis_desc_tdata(rx_desc_tdata),
|
|
.s_axis_desc_tkeep(rx_desc_tkeep),
|
|
.s_axis_desc_tvalid(rx_desc_tvalid),
|
|
.s_axis_desc_tready(rx_desc_tready),
|
|
.s_axis_desc_tlast(rx_desc_tlast),
|
|
.s_axis_desc_tid(rx_desc_tid),
|
|
.s_axis_desc_tuser(rx_desc_tuser),
|
|
|
|
/*
|
|
* Completion request output
|
|
*/
|
|
.m_axis_cpl_req_queue(rx_cpl_req_queue),
|
|
.m_axis_cpl_req_tag(rx_cpl_req_tag),
|
|
.m_axis_cpl_req_data(rx_cpl_req_data),
|
|
.m_axis_cpl_req_valid(rx_cpl_req_valid),
|
|
.m_axis_cpl_req_ready(rx_cpl_req_ready),
|
|
|
|
/*
|
|
* Completion request status input
|
|
*/
|
|
.s_axis_cpl_req_status_tag(rx_cpl_req_status_tag),
|
|
.s_axis_cpl_req_status_full(rx_cpl_req_status_full),
|
|
.s_axis_cpl_req_status_error(rx_cpl_req_status_error),
|
|
.s_axis_cpl_req_status_valid(rx_cpl_req_status_valid),
|
|
|
|
/*
|
|
* DMA write descriptor output
|
|
*/
|
|
.m_axis_dma_write_desc_dma_addr(m_axis_dma_write_desc_dma_addr),
|
|
.m_axis_dma_write_desc_ram_addr(m_axis_dma_write_desc_ram_addr),
|
|
.m_axis_dma_write_desc_len(m_axis_dma_write_desc_len),
|
|
.m_axis_dma_write_desc_tag(m_axis_dma_write_desc_tag),
|
|
.m_axis_dma_write_desc_valid(m_axis_dma_write_desc_valid),
|
|
.m_axis_dma_write_desc_ready(m_axis_dma_write_desc_ready),
|
|
|
|
/*
|
|
* DMA write descriptor status input
|
|
*/
|
|
.s_axis_dma_write_desc_status_tag(s_axis_dma_write_desc_status_tag),
|
|
.s_axis_dma_write_desc_status_valid(s_axis_dma_write_desc_status_valid),
|
|
|
|
/*
|
|
* Receive descriptor output
|
|
*/
|
|
.m_axis_rx_desc_addr(dma_rx_desc_addr),
|
|
.m_axis_rx_desc_len(dma_rx_desc_len),
|
|
.m_axis_rx_desc_tag(dma_rx_desc_tag),
|
|
.m_axis_rx_desc_valid(dma_rx_desc_valid),
|
|
.m_axis_rx_desc_ready(dma_rx_desc_ready),
|
|
|
|
/*
|
|
* Receive descriptor status input
|
|
*/
|
|
.s_axis_rx_desc_status_len(dma_rx_desc_status_len),
|
|
.s_axis_rx_desc_status_tag(dma_rx_desc_status_tag),
|
|
.s_axis_rx_desc_status_user(dma_rx_desc_status_user),
|
|
.s_axis_rx_desc_status_valid(dma_rx_desc_status_valid),
|
|
|
|
/*
|
|
* Receive timestamp input
|
|
*/
|
|
.s_axis_rx_ptp_ts_96(s_axis_rx_ptp_ts_96),
|
|
.s_axis_rx_ptp_ts_valid(s_axis_rx_ptp_ts_valid),
|
|
.s_axis_rx_ptp_ts_ready(s_axis_rx_ptp_ts_ready),
|
|
|
|
/*
|
|
* Receive checksum input
|
|
*/
|
|
.s_axis_rx_csum(rx_fifo_csum),
|
|
.s_axis_rx_csum_valid(rx_fifo_csum_valid),
|
|
.s_axis_rx_csum_ready(rx_fifo_csum_ready),
|
|
|
|
/*
|
|
* Configuration
|
|
*/
|
|
.enable(1'b1)
|
|
);
|
|
|
|
generate
|
|
|
|
if (RX_CHECKSUM_ENABLE) begin
|
|
|
|
rx_checksum #(
|
|
.DATA_WIDTH(AXIS_DATA_WIDTH)
|
|
)
|
|
rx_checksum_inst (
|
|
.clk(clk),
|
|
.rst(rst),
|
|
.s_axis_tdata(rx_axis_tdata),
|
|
.s_axis_tkeep(rx_axis_tkeep),
|
|
.s_axis_tvalid(rx_axis_tvalid & rx_axis_tready),
|
|
.s_axis_tlast(rx_axis_tlast),
|
|
.m_axis_csum(rx_csum),
|
|
.m_axis_csum_valid(rx_csum_valid)
|
|
);
|
|
|
|
axis_fifo #(
|
|
.DEPTH(16),
|
|
.DATA_WIDTH(16),
|
|
.KEEP_ENABLE(0),
|
|
.LAST_ENABLE(0),
|
|
.ID_ENABLE(0),
|
|
.DEST_ENABLE(0),
|
|
.USER_ENABLE(0),
|
|
.FRAME_FIFO(0)
|
|
)
|
|
rx_csum_fifo (
|
|
.clk(clk),
|
|
.rst(rst),
|
|
|
|
// AXI input
|
|
.s_axis_tdata(rx_csum),
|
|
.s_axis_tkeep(0),
|
|
.s_axis_tvalid(rx_csum_valid),
|
|
.s_axis_tready(),
|
|
.s_axis_tlast(0),
|
|
.s_axis_tid(0),
|
|
.s_axis_tdest(0),
|
|
.s_axis_tuser(0),
|
|
|
|
// AXI output
|
|
.m_axis_tdata(rx_fifo_csum),
|
|
.m_axis_tkeep(),
|
|
.m_axis_tvalid(rx_fifo_csum_valid),
|
|
.m_axis_tready(rx_fifo_csum_ready),
|
|
.m_axis_tlast(),
|
|
.m_axis_tid(),
|
|
.m_axis_tdest(),
|
|
.m_axis_tuser(),
|
|
|
|
// Status
|
|
.status_overflow(),
|
|
.status_bad_frame(),
|
|
.status_good_frame()
|
|
);
|
|
|
|
end else begin
|
|
|
|
assign rx_fifo_csum = 16'd0;
|
|
assign rx_fifo_csum_valid = 1'b0;
|
|
|
|
end
|
|
|
|
if (TX_CHECKSUM_ENABLE) begin
|
|
|
|
axis_fifo #(
|
|
.DEPTH(16),
|
|
.DATA_WIDTH(1+8+8),
|
|
.KEEP_ENABLE(0),
|
|
.LAST_ENABLE(0),
|
|
.ID_ENABLE(0),
|
|
.DEST_ENABLE(0),
|
|
.USER_ENABLE(0),
|
|
.FRAME_FIFO(0)
|
|
)
|
|
tx_csum_fifo (
|
|
.clk(clk),
|
|
.rst(rst),
|
|
|
|
// AXI input
|
|
.s_axis_tdata({tx_csum_cmd_csum_enable, tx_csum_cmd_csum_start, tx_csum_cmd_csum_offset}),
|
|
.s_axis_tkeep(0),
|
|
.s_axis_tvalid(tx_csum_cmd_valid),
|
|
.s_axis_tready(tx_csum_cmd_ready),
|
|
.s_axis_tlast(0),
|
|
.s_axis_tid(0),
|
|
.s_axis_tdest(0),
|
|
.s_axis_tuser(0),
|
|
|
|
// AXI output
|
|
.m_axis_tdata({tx_fifo_csum_cmd_csum_enable, tx_fifo_csum_cmd_csum_start, tx_fifo_csum_cmd_csum_offset}),
|
|
.m_axis_tkeep(),
|
|
.m_axis_tvalid(tx_fifo_csum_cmd_valid),
|
|
.m_axis_tready(tx_fifo_csum_cmd_ready),
|
|
.m_axis_tlast(),
|
|
.m_axis_tid(),
|
|
.m_axis_tdest(),
|
|
.m_axis_tuser(),
|
|
|
|
// Status
|
|
.status_overflow(),
|
|
.status_bad_frame(),
|
|
.status_good_frame()
|
|
);
|
|
|
|
tx_checksum #(
|
|
.DATA_WIDTH(AXIS_DATA_WIDTH),
|
|
.ID_ENABLE(0),
|
|
.DEST_ENABLE(0),
|
|
.USER_ENABLE(1),
|
|
.USER_WIDTH(1),
|
|
.USE_INIT_VALUE(0),
|
|
.DATA_FIFO_DEPTH(4096),
|
|
.CHECKSUM_FIFO_DEPTH(64)
|
|
)
|
|
tx_checksum_inst (
|
|
.clk(clk),
|
|
.rst(rst),
|
|
|
|
/*
|
|
* AXI input
|
|
*/
|
|
.s_axis_tdata(tx_axis_tdata_int),
|
|
.s_axis_tkeep(tx_axis_tkeep_int),
|
|
.s_axis_tvalid(tx_axis_tvalid_int),
|
|
.s_axis_tready(tx_axis_tready_int),
|
|
.s_axis_tlast(tx_axis_tlast_int),
|
|
.s_axis_tid(0),
|
|
.s_axis_tdest(0),
|
|
.s_axis_tuser(tx_axis_tuser_int),
|
|
|
|
/*
|
|
* AXI output
|
|
*/
|
|
.m_axis_tdata(tx_axis_tdata),
|
|
.m_axis_tkeep(tx_axis_tkeep),
|
|
.m_axis_tvalid(tx_axis_tvalid),
|
|
.m_axis_tready(tx_axis_tready),
|
|
.m_axis_tlast(tx_axis_tlast),
|
|
.m_axis_tid(),
|
|
.m_axis_tdest(),
|
|
.m_axis_tuser(tx_axis_tuser),
|
|
|
|
/*
|
|
* Control
|
|
*/
|
|
.s_axis_cmd_csum_enable(tx_fifo_csum_cmd_csum_enable),
|
|
.s_axis_cmd_csum_start(tx_fifo_csum_cmd_csum_start),
|
|
.s_axis_cmd_csum_offset(tx_fifo_csum_cmd_csum_offset),
|
|
.s_axis_cmd_csum_init(16'd0),
|
|
.s_axis_cmd_valid(tx_fifo_csum_cmd_valid),
|
|
.s_axis_cmd_ready(tx_fifo_csum_cmd_ready)
|
|
);
|
|
|
|
end else begin
|
|
|
|
assign tx_axis_tdata = tx_axis_tdata_int;
|
|
assign tx_axis_tkeep = tx_axis_tkeep_int;
|
|
assign tx_axis_tvalid = tx_axis_tvalid_int;
|
|
assign tx_axis_tready_int = tx_axis_tready;
|
|
assign tx_axis_tlast = tx_axis_tlast_int;
|
|
assign tx_axis_tuser = tx_axis_tuser_int;
|
|
|
|
assign tx_csum_cmd_ready = 1'b1;
|
|
|
|
end
|
|
|
|
endgenerate
|
|
|
|
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_rd_cmd_addr_int;
|
|
wire [SEG_COUNT-1:0] dma_ram_rd_cmd_valid_int;
|
|
wire [SEG_COUNT-1:0] dma_ram_rd_cmd_ready_int;
|
|
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_rd_resp_data_int;
|
|
wire [SEG_COUNT-1:0] dma_ram_rd_resp_valid_int;
|
|
wire [SEG_COUNT-1:0] dma_ram_rd_resp_ready_int;
|
|
|
|
dma_psdpram #(
|
|
.SIZE(TX_RAM_SIZE),
|
|
.SEG_COUNT(SEG_COUNT),
|
|
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
|
|
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
|
|
.SEG_BE_WIDTH(SEG_BE_WIDTH),
|
|
.PIPELINE(RAM_PIPELINE)
|
|
)
|
|
dma_psdpram_tx_inst (
|
|
/*
|
|
* Write port
|
|
*/
|
|
.clk_wr(clk),
|
|
.rst_wr(rst),
|
|
.wr_cmd_be(dma_ram_wr_cmd_be),
|
|
.wr_cmd_addr(dma_ram_wr_cmd_addr),
|
|
.wr_cmd_data(dma_ram_wr_cmd_data),
|
|
.wr_cmd_valid(dma_ram_wr_cmd_valid),
|
|
.wr_cmd_ready(dma_ram_wr_cmd_ready),
|
|
|
|
/*
|
|
* Read port
|
|
*/
|
|
.clk_rd(clk),
|
|
.rst_rd(rst),
|
|
.rd_cmd_addr(dma_ram_rd_cmd_addr_int),
|
|
.rd_cmd_valid(dma_ram_rd_cmd_valid_int),
|
|
.rd_cmd_ready(dma_ram_rd_cmd_ready_int),
|
|
.rd_resp_data(dma_ram_rd_resp_data_int),
|
|
.rd_resp_valid(dma_ram_rd_resp_valid_int),
|
|
.rd_resp_ready(dma_ram_rd_resp_ready_int)
|
|
);
|
|
|
|
dma_client_axis_source #(
|
|
.SEG_COUNT(SEG_COUNT),
|
|
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
|
|
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
|
|
.SEG_BE_WIDTH(SEG_BE_WIDTH),
|
|
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
|
|
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
|
|
.AXIS_KEEP_ENABLE(AXIS_KEEP_WIDTH > 1),
|
|
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
|
|
.AXIS_LAST_ENABLE(1),
|
|
.AXIS_ID_ENABLE(0),
|
|
.AXIS_DEST_ENABLE(0),
|
|
.AXIS_USER_ENABLE(1),
|
|
.AXIS_USER_WIDTH(1),
|
|
.LEN_WIDTH(DMA_CLIENT_LEN_WIDTH),
|
|
.TAG_WIDTH(DMA_CLIENT_TAG_WIDTH)
|
|
)
|
|
dma_client_axis_source_inst (
|
|
.clk(clk),
|
|
.rst(rst),
|
|
|
|
/*
|
|
* DMA read descriptor input
|
|
*/
|
|
.s_axis_read_desc_ram_addr(dma_tx_desc_addr),
|
|
.s_axis_read_desc_len(dma_tx_desc_len),
|
|
.s_axis_read_desc_tag(dma_tx_desc_tag),
|
|
.s_axis_read_desc_id(0),
|
|
.s_axis_read_desc_dest(0),
|
|
.s_axis_read_desc_user(dma_tx_desc_user),
|
|
.s_axis_read_desc_valid(dma_tx_desc_valid),
|
|
.s_axis_read_desc_ready(dma_tx_desc_ready),
|
|
|
|
/*
|
|
* DMA read descriptor status output
|
|
*/
|
|
.m_axis_read_desc_status_tag(dma_tx_desc_status_tag),
|
|
.m_axis_read_desc_status_valid(dma_tx_desc_status_valid),
|
|
|
|
/*
|
|
* AXI stream read data output
|
|
*/
|
|
.m_axis_read_data_tdata(tx_axis_tdata_int),
|
|
.m_axis_read_data_tkeep(tx_axis_tkeep_int),
|
|
.m_axis_read_data_tvalid(tx_axis_tvalid_int),
|
|
.m_axis_read_data_tready(tx_axis_tready_int),
|
|
.m_axis_read_data_tlast(tx_axis_tlast_int),
|
|
.m_axis_read_data_tid(),
|
|
.m_axis_read_data_tdest(),
|
|
.m_axis_read_data_tuser(tx_axis_tuser_int),
|
|
|
|
/*
|
|
* RAM interface
|
|
*/
|
|
.ram_rd_cmd_addr(dma_ram_rd_cmd_addr_int),
|
|
.ram_rd_cmd_valid(dma_ram_rd_cmd_valid_int),
|
|
.ram_rd_cmd_ready(dma_ram_rd_cmd_ready_int),
|
|
.ram_rd_resp_data(dma_ram_rd_resp_data_int),
|
|
.ram_rd_resp_valid(dma_ram_rd_resp_valid_int),
|
|
.ram_rd_resp_ready(dma_ram_rd_resp_ready_int),
|
|
|
|
/*
|
|
* Configuration
|
|
*/
|
|
.enable(dma_enable)
|
|
);
|
|
|
|
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] dma_ram_wr_cmd_be_int;
|
|
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_wr_cmd_addr_int;
|
|
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_wr_cmd_data_int;
|
|
wire [SEG_COUNT-1:0] dma_ram_wr_cmd_valid_int;
|
|
wire [SEG_COUNT-1:0] dma_ram_wr_cmd_ready_int;
|
|
|
|
dma_psdpram #(
|
|
.SIZE(RX_RAM_SIZE),
|
|
.SEG_COUNT(SEG_COUNT),
|
|
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
|
|
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
|
|
.SEG_BE_WIDTH(SEG_BE_WIDTH),
|
|
.PIPELINE(RAM_PIPELINE)
|
|
)
|
|
dma_psdpram_rx_inst (
|
|
/*
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|
* Write port
|
|
*/
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|
.clk_wr(clk),
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|
.rst_wr(rst),
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|
.wr_cmd_be(dma_ram_wr_cmd_be_int),
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|
.wr_cmd_addr(dma_ram_wr_cmd_addr_int),
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|
.wr_cmd_data(dma_ram_wr_cmd_data_int),
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|
.wr_cmd_valid(dma_ram_wr_cmd_valid_int),
|
|
.wr_cmd_ready(dma_ram_wr_cmd_ready_int),
|
|
|
|
/*
|
|
* Read port
|
|
*/
|
|
.clk_rd(clk),
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|
.rst_rd(rst),
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|
.rd_cmd_addr(dma_ram_rd_cmd_addr),
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|
.rd_cmd_valid(dma_ram_rd_cmd_valid),
|
|
.rd_cmd_ready(dma_ram_rd_cmd_ready),
|
|
.rd_resp_data(dma_ram_rd_resp_data),
|
|
.rd_resp_valid(dma_ram_rd_resp_valid),
|
|
.rd_resp_ready(dma_ram_rd_resp_ready)
|
|
);
|
|
|
|
dma_client_axis_sink #(
|
|
.SEG_COUNT(SEG_COUNT),
|
|
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
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|
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
|
|
.SEG_BE_WIDTH(SEG_BE_WIDTH),
|
|
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
|
|
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
|
|
.AXIS_KEEP_ENABLE(AXIS_KEEP_WIDTH > 1),
|
|
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
|
|
.AXIS_LAST_ENABLE(1),
|
|
.AXIS_ID_ENABLE(0),
|
|
.AXIS_DEST_ENABLE(0),
|
|
.AXIS_USER_ENABLE(1),
|
|
.AXIS_USER_WIDTH(1),
|
|
.LEN_WIDTH(DMA_CLIENT_LEN_WIDTH),
|
|
.TAG_WIDTH(DMA_CLIENT_TAG_WIDTH)
|
|
)
|
|
dma_client_axis_sink_inst (
|
|
.clk(clk),
|
|
.rst(rst),
|
|
|
|
/*
|
|
* DMA write descriptor input
|
|
*/
|
|
.s_axis_write_desc_ram_addr(dma_rx_desc_addr),
|
|
.s_axis_write_desc_len(dma_rx_desc_len),
|
|
.s_axis_write_desc_tag(dma_rx_desc_tag),
|
|
.s_axis_write_desc_valid(dma_rx_desc_valid),
|
|
.s_axis_write_desc_ready(dma_rx_desc_ready),
|
|
|
|
/*
|
|
* DMA write descriptor status output
|
|
*/
|
|
.m_axis_write_desc_status_len(dma_rx_desc_status_len),
|
|
.m_axis_write_desc_status_tag(dma_rx_desc_status_tag),
|
|
.m_axis_write_desc_status_id(),
|
|
.m_axis_write_desc_status_dest(),
|
|
.m_axis_write_desc_status_user(dma_rx_desc_status_user),
|
|
.m_axis_write_desc_status_valid(dma_rx_desc_status_valid),
|
|
|
|
/*
|
|
* AXI stream write data input
|
|
*/
|
|
.s_axis_write_data_tdata(rx_axis_tdata),
|
|
.s_axis_write_data_tkeep(rx_axis_tkeep),
|
|
.s_axis_write_data_tvalid(rx_axis_tvalid),
|
|
.s_axis_write_data_tready(rx_axis_tready),
|
|
.s_axis_write_data_tlast(rx_axis_tlast),
|
|
.s_axis_write_data_tid(0),
|
|
.s_axis_write_data_tdest(0),
|
|
.s_axis_write_data_tuser(rx_axis_tuser),
|
|
|
|
/*
|
|
* RAM interface
|
|
*/
|
|
.ram_wr_cmd_be(dma_ram_wr_cmd_be_int),
|
|
.ram_wr_cmd_addr(dma_ram_wr_cmd_addr_int),
|
|
.ram_wr_cmd_data(dma_ram_wr_cmd_data_int),
|
|
.ram_wr_cmd_valid(dma_ram_wr_cmd_valid_int),
|
|
.ram_wr_cmd_ready(dma_ram_wr_cmd_ready_int),
|
|
|
|
/*
|
|
* Configuration
|
|
*/
|
|
.enable(dma_enable),
|
|
.abort(1'b0)
|
|
);
|
|
|
|
endmodule
|