mirror of
https://github.com/corundum/corundum.git
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987 lines
26 KiB
Verilog
987 lines
26 KiB
Verilog
/*
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Copyright (c) 2014-2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* FPGA top-level module
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*/
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module fpga (
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/*
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* Reset: Push button, active low
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*/
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input wire reset,
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/*
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* GPIO
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*/
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input wire [3:0] sw,
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output wire [2:0] led,
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/*
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* I2C for board management
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*/
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inout wire i2c_scl,
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inout wire i2c_sda,
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/*
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* Ethernet: QSFP28
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*/
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output wire qsfp0_tx1_p,
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output wire qsfp0_tx1_n,
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input wire qsfp0_rx1_p,
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input wire qsfp0_rx1_n,
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output wire qsfp0_tx2_p,
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output wire qsfp0_tx2_n,
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input wire qsfp0_rx2_p,
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input wire qsfp0_rx2_n,
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output wire qsfp0_tx3_p,
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output wire qsfp0_tx3_n,
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input wire qsfp0_rx3_p,
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input wire qsfp0_rx3_n,
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output wire qsfp0_tx4_p,
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output wire qsfp0_tx4_n,
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input wire qsfp0_rx4_p,
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input wire qsfp0_rx4_n,
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// input wire qsfp0_mgt_refclk_0_p,
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// input wire qsfp0_mgt_refclk_0_n,
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input wire qsfp0_mgt_refclk_1_p,
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input wire qsfp0_mgt_refclk_1_n,
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output wire qsfp0_modsell,
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output wire qsfp0_resetl,
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input wire qsfp0_modprsl,
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input wire qsfp0_intl,
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output wire qsfp0_lpmode,
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output wire qsfp0_refclk_reset,
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output wire [1:0] qsfp0_fs,
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output wire qsfp1_tx1_p,
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output wire qsfp1_tx1_n,
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input wire qsfp1_rx1_p,
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input wire qsfp1_rx1_n,
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output wire qsfp1_tx2_p,
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output wire qsfp1_tx2_n,
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input wire qsfp1_rx2_p,
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input wire qsfp1_rx2_n,
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output wire qsfp1_tx3_p,
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output wire qsfp1_tx3_n,
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input wire qsfp1_rx3_p,
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input wire qsfp1_rx3_n,
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output wire qsfp1_tx4_p,
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output wire qsfp1_tx4_n,
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input wire qsfp1_rx4_p,
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input wire qsfp1_rx4_n,
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// input wire qsfp1_mgt_refclk_0_p,
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// input wire qsfp1_mgt_refclk_0_n,
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// input wire qsfp1_mgt_refclk_1_p,
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// input wire qsfp1_mgt_refclk_1_n,
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output wire qsfp1_modsell,
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output wire qsfp1_resetl,
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input wire qsfp1_modprsl,
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input wire qsfp1_intl,
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output wire qsfp1_lpmode,
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output wire qsfp1_refclk_reset,
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output wire [1:0] qsfp1_fs,
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/*
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* UART: 500000 bps, 8N1
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*/
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output wire uart_rxd,
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input wire uart_txd
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);
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// Clock and reset
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wire cfgmclk_int;
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wire clk_161mhz_ref_int;
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// Internal 125 MHz clock
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wire clk_125mhz_mmcm_out;
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wire clk_125mhz_int;
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wire rst_125mhz_int;
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// Internal 156.25 MHz clock
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wire clk_156mhz_int;
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wire rst_156mhz_int;
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wire mmcm_rst;
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wire mmcm_locked;
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wire mmcm_clkfb;
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// MMCM instance
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// 161.13 MHz in, 125 MHz out
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// PFD range: 10 MHz to 500 MHz
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// VCO range: 800 MHz to 1600 MHz
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// M = 64, D = 11 sets Fvco = 937.5 MHz (in range)
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// Divide by 7.5 to get output frequency of 125 MHz
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MMCME4_BASE #(
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.BANDWIDTH("OPTIMIZED"),
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.CLKOUT0_DIVIDE_F(7.5),
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT0_PHASE(0),
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.CLKOUT1_DIVIDE(1),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT1_PHASE(0),
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.CLKOUT2_DIVIDE(1),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT2_PHASE(0),
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.CLKOUT3_DIVIDE(1),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT3_PHASE(0),
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.CLKOUT4_DIVIDE(1),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT4_PHASE(0),
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.CLKOUT5_DIVIDE(1),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT5_PHASE(0),
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.CLKOUT6_DIVIDE(1),
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.CLKOUT6_DUTY_CYCLE(0.5),
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.CLKOUT6_PHASE(0),
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.CLKFBOUT_MULT_F(64),
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.CLKFBOUT_PHASE(0),
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.DIVCLK_DIVIDE(11),
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.REF_JITTER1(0.010),
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.CLKIN1_PERIOD(6.206),
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.STARTUP_WAIT("FALSE"),
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.CLKOUT4_CASCADE("FALSE")
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)
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clk_mmcm_inst (
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.CLKIN1(clk_161mhz_ref_int),
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.CLKFBIN(mmcm_clkfb),
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.RST(mmcm_rst),
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.PWRDWN(1'b0),
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.CLKOUT0(clk_125mhz_mmcm_out),
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.CLKOUT0B(),
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.CLKOUT1(),
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.CLKOUT1B(),
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.CLKOUT2(),
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.CLKOUT2B(),
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.CLKOUT3(),
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.CLKOUT3B(),
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.CLKOUT4(),
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.CLKOUT5(),
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.CLKOUT6(),
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.CLKFBOUT(mmcm_clkfb),
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.CLKFBOUTB(),
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.LOCKED(mmcm_locked)
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);
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BUFG
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clk_125mhz_bufg_inst (
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.I(clk_125mhz_mmcm_out),
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.O(clk_125mhz_int)
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);
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sync_reset #(
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.N(4)
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)
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sync_reset_125mhz_inst (
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.clk(clk_125mhz_int),
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.rst(~mmcm_locked),
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.out(rst_125mhz_int)
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);
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// GPIO
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wire [3:0] sw_int;
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debounce_switch #(
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.WIDTH(4),
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.N(4),
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.RATE(156000)
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)
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debounce_switch_inst (
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.clk(clk_156mhz_int),
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.rst(rst_156mhz_int),
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.in({sw}),
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.out({sw_int})
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);
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wire uart_txd_int;
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sync_signal #(
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.WIDTH(1),
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.N(2)
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)
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sync_signal_inst (
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.clk(clk_156mhz_int),
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.in({uart_txd}),
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.out({uart_txd_int})
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);
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// SI570 I2C
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wire i2c_scl_i;
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wire i2c_scl_o = 1'b1;
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wire i2c_scl_t = 1'b1;
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wire i2c_sda_i;
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wire i2c_sda_o = 1'b1;
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wire i2c_sda_t = 1'b1;
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assign i2c_scl_i = i2c_scl;
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assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
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assign i2c_sda_i = i2c_sda;
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assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o;
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// startupe3 instance
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wire cfgmclk;
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STARTUPE3
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startupe3_inst (
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.CFGCLK(),
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.CFGMCLK(cfgmclk),
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.DI(4'd0),
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.DO(),
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.DTS(1'b1),
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.EOS(),
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.FCSBO(1'b0),
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.FCSBTS(1'b1),
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.GSR(1'b0),
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.GTS(1'b0),
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.KEYCLEARB(1'b1),
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.PACK(1'b0),
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.PREQ(),
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.USRCCLKO(1'b0),
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.USRCCLKTS(1'b1),
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.USRDONEO(1'b0),
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.USRDONETS(1'b1)
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);
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BUFG
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cfgmclk_bufg_inst (
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.I(cfgmclk),
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.O(cfgmclk_int)
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);
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// configure SI5335 clock generators
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reg qsfp_refclk_reset_reg = 1'b1;
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reg sys_reset_reg = 1'b1;
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reg [9:0] reset_timer_reg = 0;
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assign mmcm_rst = sys_reset_reg;
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always @(posedge cfgmclk_int) begin
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if (&reset_timer_reg) begin
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if (qsfp_refclk_reset_reg) begin
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qsfp_refclk_reset_reg <= 1'b0;
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reset_timer_reg <= 0;
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end else begin
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qsfp_refclk_reset_reg <= 1'b0;
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sys_reset_reg <= 1'b0;
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end
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end else begin
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reset_timer_reg <= reset_timer_reg + 1;
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end
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if (!reset) begin
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qsfp_refclk_reset_reg <= 1'b1;
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sys_reset_reg <= 1'b1;
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reset_timer_reg <= 0;
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end
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end
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// XGMII 10G PHY
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assign qsfp0_modsell = 1'b0;
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assign qsfp0_resetl = 1'b1;
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assign qsfp0_lpmode = 1'b0;
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assign qsfp0_refclk_reset = qsfp_refclk_reset_reg;
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assign qsfp0_fs = 2'b10;
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wire qsfp0_tx_clk_1_int;
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wire qsfp0_tx_rst_1_int;
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wire [63:0] qsfp0_txd_1_int;
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wire [7:0] qsfp0_txc_1_int;
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wire qsfp0_rx_clk_1_int;
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wire qsfp0_rx_rst_1_int;
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wire [63:0] qsfp0_rxd_1_int;
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wire [7:0] qsfp0_rxc_1_int;
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wire qsfp0_tx_clk_2_int;
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wire qsfp0_tx_rst_2_int;
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wire [63:0] qsfp0_txd_2_int;
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wire [7:0] qsfp0_txc_2_int;
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wire qsfp0_rx_clk_2_int;
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wire qsfp0_rx_rst_2_int;
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wire [63:0] qsfp0_rxd_2_int;
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wire [7:0] qsfp0_rxc_2_int;
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wire qsfp0_tx_clk_3_int;
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wire qsfp0_tx_rst_3_int;
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wire [63:0] qsfp0_txd_3_int;
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wire [7:0] qsfp0_txc_3_int;
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wire qsfp0_rx_clk_3_int;
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wire qsfp0_rx_rst_3_int;
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wire [63:0] qsfp0_rxd_3_int;
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wire [7:0] qsfp0_rxc_3_int;
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wire qsfp0_tx_clk_4_int;
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wire qsfp0_tx_rst_4_int;
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wire [63:0] qsfp0_txd_4_int;
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wire [7:0] qsfp0_txc_4_int;
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wire qsfp0_rx_clk_4_int;
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wire qsfp0_rx_rst_4_int;
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wire [63:0] qsfp0_rxd_4_int;
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wire [7:0] qsfp0_rxc_4_int;
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assign qsfp1_modsell = 1'b0;
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assign qsfp1_resetl = 1'b1;
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assign qsfp1_lpmode = 1'b0;
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assign qsfp1_refclk_reset = qsfp_refclk_reset_reg;
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assign qsfp1_fs = 2'b10;
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wire qsfp1_tx_clk_1_int;
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wire qsfp1_tx_rst_1_int;
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wire [63:0] qsfp1_txd_1_int;
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wire [7:0] qsfp1_txc_1_int;
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wire qsfp1_rx_clk_1_int;
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wire qsfp1_rx_rst_1_int;
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wire [63:0] qsfp1_rxd_1_int;
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wire [7:0] qsfp1_rxc_1_int;
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wire qsfp1_tx_clk_2_int;
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wire qsfp1_tx_rst_2_int;
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wire [63:0] qsfp1_txd_2_int;
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wire [7:0] qsfp1_txc_2_int;
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wire qsfp1_rx_clk_2_int;
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wire qsfp1_rx_rst_2_int;
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wire [63:0] qsfp1_rxd_2_int;
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wire [7:0] qsfp1_rxc_2_int;
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wire qsfp1_tx_clk_3_int;
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wire qsfp1_tx_rst_3_int;
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wire [63:0] qsfp1_txd_3_int;
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wire [7:0] qsfp1_txc_3_int;
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wire qsfp1_rx_clk_3_int;
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wire qsfp1_rx_rst_3_int;
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wire [63:0] qsfp1_rxd_3_int;
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wire [7:0] qsfp1_rxc_3_int;
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wire qsfp1_tx_clk_4_int;
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wire qsfp1_tx_rst_4_int;
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wire [63:0] qsfp1_txd_4_int;
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wire [7:0] qsfp1_txc_4_int;
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wire qsfp1_rx_clk_4_int;
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wire qsfp1_rx_rst_4_int;
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wire [63:0] qsfp1_rxd_4_int;
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wire [7:0] qsfp1_rxc_4_int;
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wire qsfp0_rx_block_lock_1;
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wire qsfp0_rx_block_lock_2;
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wire qsfp0_rx_block_lock_3;
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wire qsfp0_rx_block_lock_4;
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wire qsfp1_rx_block_lock_1;
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wire qsfp1_rx_block_lock_2;
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wire qsfp1_rx_block_lock_3;
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wire qsfp1_rx_block_lock_4;
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wire [7:0] qsfp_gtpowergood;
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wire qsfp0_mgt_refclk_1;
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wire qsfp0_mgt_refclk_1_int;
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wire qsfp0_mgt_refclk_1_bufg;
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assign clk_161mhz_ref_int = qsfp0_mgt_refclk_1_bufg;
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wire [7:0] gt_txclkout;
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wire gt_txusrclk;
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wire [7:0] gt_rxclkout;
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wire [7:0] gt_rxusrclk;
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wire gt_reset_tx_done;
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wire gt_reset_rx_done;
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wire [7:0] gt_txprgdivresetdone;
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wire [7:0] gt_txpmaresetdone;
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wire [7:0] gt_rxprgdivresetdone;
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wire [7:0] gt_rxpmaresetdone;
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wire gt_tx_reset = ~((>_txprgdivresetdone) & (>_txpmaresetdone));
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wire gt_rx_reset = ~>_rxpmaresetdone;
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reg gt_userclk_tx_active = 1'b0;
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reg [7:0] gt_userclk_rx_active = 1'b0;
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IBUFDS_GTE4 ibufds_gte4_qsfp0_mgt_refclk_1_inst (
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.I (qsfp0_mgt_refclk_1_p),
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.IB (qsfp0_mgt_refclk_1_n),
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.CEB (1'b0),
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.O (qsfp0_mgt_refclk_1),
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.ODIV2 (qsfp0_mgt_refclk_1_int)
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);
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BUFG_GT bufg_gt_refclk_inst (
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.CE (&qsfp_gtpowergood),
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.CEMASK (1'b1),
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.CLR (1'b0),
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.CLRMASK (1'b1),
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.DIV (3'd0),
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.I (qsfp0_mgt_refclk_1_int),
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.O (qsfp0_mgt_refclk_1_bufg)
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);
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BUFG_GT bufg_gt_tx_usrclk_inst (
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.CE (1'b1),
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.CEMASK (1'b0),
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.CLR (gt_tx_reset),
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.CLRMASK (1'b0),
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.DIV (3'd0),
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.I (gt_txclkout[0]),
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.O (gt_txusrclk)
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);
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assign clk_156mhz_int = gt_txusrclk;
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always @(posedge gt_txusrclk, posedge gt_tx_reset) begin
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if (gt_tx_reset) begin
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gt_userclk_tx_active <= 1'b0;
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end else begin
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gt_userclk_tx_active <= 1'b1;
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end
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end
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genvar n;
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generate
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for (n = 0; n < 8; n = n + 1) begin
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|
BUFG_GT bufg_gt_rx_usrclk_inst (
|
|
.CE (1'b1),
|
|
.CEMASK (1'b0),
|
|
.CLR (gt_rx_reset),
|
|
.CLRMASK (1'b0),
|
|
.DIV (3'd0),
|
|
.I (gt_rxclkout[n]),
|
|
.O (gt_rxusrclk[n])
|
|
);
|
|
|
|
always @(posedge gt_rxusrclk[n], posedge gt_rx_reset) begin
|
|
if (gt_rx_reset) begin
|
|
gt_userclk_rx_active[n] <= 1'b0;
|
|
end else begin
|
|
gt_userclk_rx_active[n] <= 1'b1;
|
|
end
|
|
end
|
|
|
|
end
|
|
|
|
endgenerate
|
|
|
|
sync_reset #(
|
|
.N(4)
|
|
)
|
|
sync_reset_156mhz_inst (
|
|
.clk(clk_156mhz_int),
|
|
.rst(~gt_reset_tx_done),
|
|
.out(rst_156mhz_int)
|
|
);
|
|
|
|
wire [5:0] qsfp0_gt_txheader_1;
|
|
wire [63:0] qsfp0_gt_txdata_1;
|
|
wire qsfp0_gt_rxgearboxslip_1;
|
|
wire [5:0] qsfp0_gt_rxheader_1;
|
|
wire [1:0] qsfp0_gt_rxheadervalid_1;
|
|
wire [63:0] qsfp0_gt_rxdata_1;
|
|
wire [1:0] qsfp0_gt_rxdatavalid_1;
|
|
|
|
wire [5:0] qsfp0_gt_txheader_2;
|
|
wire [63:0] qsfp0_gt_txdata_2;
|
|
wire qsfp0_gt_rxgearboxslip_2;
|
|
wire [5:0] qsfp0_gt_rxheader_2;
|
|
wire [1:0] qsfp0_gt_rxheadervalid_2;
|
|
wire [63:0] qsfp0_gt_rxdata_2;
|
|
wire [1:0] qsfp0_gt_rxdatavalid_2;
|
|
|
|
wire [5:0] qsfp0_gt_txheader_3;
|
|
wire [63:0] qsfp0_gt_txdata_3;
|
|
wire qsfp0_gt_rxgearboxslip_3;
|
|
wire [5:0] qsfp0_gt_rxheader_3;
|
|
wire [1:0] qsfp0_gt_rxheadervalid_3;
|
|
wire [63:0] qsfp0_gt_rxdata_3;
|
|
wire [1:0] qsfp0_gt_rxdatavalid_3;
|
|
|
|
wire [5:0] qsfp0_gt_txheader_4;
|
|
wire [63:0] qsfp0_gt_txdata_4;
|
|
wire qsfp0_gt_rxgearboxslip_4;
|
|
wire [5:0] qsfp0_gt_rxheader_4;
|
|
wire [1:0] qsfp0_gt_rxheadervalid_4;
|
|
wire [63:0] qsfp0_gt_rxdata_4;
|
|
wire [1:0] qsfp0_gt_rxdatavalid_4;
|
|
|
|
wire [5:0] qsfp1_gt_txheader_1;
|
|
wire [63:0] qsfp1_gt_txdata_1;
|
|
wire qsfp1_gt_rxgearboxslip_1;
|
|
wire [5:0] qsfp1_gt_rxheader_1;
|
|
wire [1:0] qsfp1_gt_rxheadervalid_1;
|
|
wire [63:0] qsfp1_gt_rxdata_1;
|
|
wire [1:0] qsfp1_gt_rxdatavalid_1;
|
|
|
|
wire [5:0] qsfp1_gt_txheader_2;
|
|
wire [63:0] qsfp1_gt_txdata_2;
|
|
wire qsfp1_gt_rxgearboxslip_2;
|
|
wire [5:0] qsfp1_gt_rxheader_2;
|
|
wire [1:0] qsfp1_gt_rxheadervalid_2;
|
|
wire [63:0] qsfp1_gt_rxdata_2;
|
|
wire [1:0] qsfp1_gt_rxdatavalid_2;
|
|
|
|
wire [5:0] qsfp1_gt_txheader_3;
|
|
wire [63:0] qsfp1_gt_txdata_3;
|
|
wire qsfp1_gt_rxgearboxslip_3;
|
|
wire [5:0] qsfp1_gt_rxheader_3;
|
|
wire [1:0] qsfp1_gt_rxheadervalid_3;
|
|
wire [63:0] qsfp1_gt_rxdata_3;
|
|
wire [1:0] qsfp1_gt_rxdatavalid_3;
|
|
|
|
wire [5:0] qsfp1_gt_txheader_4;
|
|
wire [63:0] qsfp1_gt_txdata_4;
|
|
wire qsfp1_gt_rxgearboxslip_4;
|
|
wire [5:0] qsfp1_gt_rxheader_4;
|
|
wire [1:0] qsfp1_gt_rxheadervalid_4;
|
|
wire [63:0] qsfp1_gt_rxdata_4;
|
|
wire [1:0] qsfp1_gt_rxdatavalid_4;
|
|
|
|
gtwizard_ultrascale_0
|
|
qsfp_gty_inst (
|
|
.gtwiz_userclk_tx_active_in(>_userclk_tx_active),
|
|
.gtwiz_userclk_rx_active_in(>_userclk_rx_active),
|
|
|
|
.gtwiz_reset_clk_freerun_in(clk_125mhz_int),
|
|
.gtwiz_reset_all_in(rst_125mhz_int),
|
|
|
|
.gtwiz_reset_tx_pll_and_datapath_in(1'b0),
|
|
.gtwiz_reset_tx_datapath_in(1'b0),
|
|
|
|
.gtwiz_reset_rx_pll_and_datapath_in(1'b0),
|
|
.gtwiz_reset_rx_datapath_in(1'b0),
|
|
|
|
.gtwiz_reset_rx_cdr_stable_out(),
|
|
|
|
.gtwiz_reset_tx_done_out(gt_reset_tx_done),
|
|
.gtwiz_reset_rx_done_out(gt_reset_rx_done),
|
|
|
|
.gtrefclk00_in({2{qsfp0_mgt_refclk_1}}),
|
|
|
|
.qpll0outclk_out(),
|
|
.qpll0outrefclk_out(),
|
|
|
|
.gtyrxn_in({qsfp0_rx4_n, qsfp0_rx3_n, qsfp0_rx2_n, qsfp0_rx1_n, qsfp1_rx4_n, qsfp1_rx3_n, qsfp1_rx2_n, qsfp1_rx1_n}),
|
|
.gtyrxp_in({qsfp0_rx4_p, qsfp0_rx3_p, qsfp0_rx2_p, qsfp0_rx1_p, qsfp1_rx4_p, qsfp1_rx3_p, qsfp1_rx2_p, qsfp1_rx1_p}),
|
|
|
|
.rxusrclk_in(gt_rxusrclk),
|
|
.rxusrclk2_in(gt_rxusrclk),
|
|
|
|
.gtwiz_userdata_tx_in({qsfp0_gt_txdata_4, qsfp0_gt_txdata_3, qsfp0_gt_txdata_2, qsfp0_gt_txdata_1, qsfp1_gt_txdata_4, qsfp1_gt_txdata_3, qsfp1_gt_txdata_2, qsfp1_gt_txdata_1}),
|
|
.txheader_in({qsfp0_gt_txheader_4, qsfp0_gt_txheader_3, qsfp0_gt_txheader_2, qsfp0_gt_txheader_1, qsfp1_gt_txheader_4, qsfp1_gt_txheader_3, qsfp1_gt_txheader_2, qsfp1_gt_txheader_1}),
|
|
.txsequence_in({8{1'b0}}),
|
|
|
|
.txusrclk_in({8{gt_txusrclk}}),
|
|
.txusrclk2_in({8{gt_txusrclk}}),
|
|
|
|
.gtpowergood_out(qsfp_gtpowergood),
|
|
|
|
.gtytxn_out({qsfp0_tx4_n, qsfp0_tx3_n, qsfp0_tx2_n, qsfp0_tx1_n, qsfp1_tx4_n, qsfp1_tx3_n, qsfp1_tx2_n, qsfp1_tx1_n}),
|
|
.gtytxp_out({qsfp0_tx4_p, qsfp0_tx3_p, qsfp0_tx2_p, qsfp0_tx1_p, qsfp1_tx4_p, qsfp1_tx3_p, qsfp1_tx2_p, qsfp1_tx1_p}),
|
|
|
|
.rxgearboxslip_in({qsfp0_gt_rxgearboxslip_4, qsfp0_gt_rxgearboxslip_3, qsfp0_gt_rxgearboxslip_2, qsfp0_gt_rxgearboxslip_1, qsfp1_gt_rxgearboxslip_4, qsfp1_gt_rxgearboxslip_3, qsfp1_gt_rxgearboxslip_2, qsfp1_gt_rxgearboxslip_1}),
|
|
.gtwiz_userdata_rx_out({qsfp0_gt_rxdata_4, qsfp0_gt_rxdata_3, qsfp0_gt_rxdata_2, qsfp0_gt_rxdata_1, qsfp1_gt_rxdata_4, qsfp1_gt_rxdata_3, qsfp1_gt_rxdata_2, qsfp1_gt_rxdata_1}),
|
|
.rxdatavalid_out({qsfp0_gt_rxdatavalid_4, qsfp0_gt_rxdatavalid_3, qsfp0_gt_rxdatavalid_2, qsfp0_gt_rxdatavalid_1, qsfp1_gt_rxdatavalid_4, qsfp1_gt_rxdatavalid_3, qsfp1_gt_rxdatavalid_2, qsfp1_gt_rxdatavalid_1}),
|
|
.rxheader_out({qsfp0_gt_rxheader_4, qsfp0_gt_rxheader_3, qsfp0_gt_rxheader_2, qsfp0_gt_rxheader_1, qsfp1_gt_rxheader_4, qsfp1_gt_rxheader_3, qsfp1_gt_rxheader_2, qsfp1_gt_rxheader_1}),
|
|
.rxheadervalid_out({qsfp0_gt_rxheadervalid_4, qsfp0_gt_rxheadervalid_3, qsfp0_gt_rxheadervalid_2, qsfp0_gt_rxheadervalid_1, qsfp1_gt_rxheadervalid_4, qsfp1_gt_rxheadervalid_3, qsfp1_gt_rxheadervalid_2, qsfp1_gt_rxheadervalid_1}),
|
|
.rxoutclk_out(gt_rxclkout),
|
|
.rxpmaresetdone_out(gt_rxpmaresetdone),
|
|
.rxprgdivresetdone_out(gt_rxprgdivresetdone),
|
|
.rxstartofseq_out(),
|
|
|
|
.txoutclk_out(gt_txclkout),
|
|
.txpmaresetdone_out(gt_txpmaresetdone),
|
|
.txprgdivresetdone_out(gt_txprgdivresetdone)
|
|
);
|
|
|
|
assign qsfp0_tx_clk_1_int = clk_156mhz_int;
|
|
assign qsfp0_tx_rst_1_int = rst_156mhz_int;
|
|
|
|
assign qsfp0_rx_clk_1_int = gt_rxusrclk[4];
|
|
|
|
sync_reset #(
|
|
.N(4)
|
|
)
|
|
qsfp0_rx_rst_1_reset_sync_inst (
|
|
.clk(qsfp0_rx_clk_1_int),
|
|
.rst(~gt_reset_rx_done),
|
|
.out(qsfp0_rx_rst_1_int)
|
|
);
|
|
|
|
eth_phy_10g #(
|
|
.BIT_REVERSE(1)
|
|
)
|
|
qsfp0_phy_1_inst (
|
|
.tx_clk(qsfp0_tx_clk_1_int),
|
|
.tx_rst(qsfp0_tx_rst_1_int),
|
|
.rx_clk(qsfp0_rx_clk_1_int),
|
|
.rx_rst(qsfp0_rx_rst_1_int),
|
|
.xgmii_txd(qsfp0_txd_1_int),
|
|
.xgmii_txc(qsfp0_txc_1_int),
|
|
.xgmii_rxd(qsfp0_rxd_1_int),
|
|
.xgmii_rxc(qsfp0_rxc_1_int),
|
|
.serdes_tx_data(qsfp0_gt_txdata_1),
|
|
.serdes_tx_hdr(qsfp0_gt_txheader_1),
|
|
.serdes_rx_data(qsfp0_gt_rxdata_1),
|
|
.serdes_rx_hdr(qsfp0_gt_rxheader_1),
|
|
.serdes_rx_bitslip(qsfp0_gt_rxgearboxslip_1),
|
|
.rx_block_lock(qsfp0_rx_block_lock_1),
|
|
.rx_high_ber()
|
|
);
|
|
|
|
assign qsfp0_tx_clk_2_int = clk_156mhz_int;
|
|
assign qsfp0_tx_rst_2_int = rst_156mhz_int;
|
|
|
|
assign qsfp0_rx_clk_2_int = gt_rxusrclk[5];
|
|
|
|
sync_reset #(
|
|
.N(4)
|
|
)
|
|
qsfp0_rx_rst_2_reset_sync_inst (
|
|
.clk(qsfp0_rx_clk_2_int),
|
|
.rst(~gt_reset_rx_done),
|
|
.out(qsfp0_rx_rst_2_int)
|
|
);
|
|
|
|
eth_phy_10g #(
|
|
.BIT_REVERSE(1)
|
|
)
|
|
qsfp0_phy_2_inst (
|
|
.tx_clk(qsfp0_tx_clk_2_int),
|
|
.tx_rst(qsfp0_tx_rst_2_int),
|
|
.rx_clk(qsfp0_rx_clk_2_int),
|
|
.rx_rst(qsfp0_rx_rst_2_int),
|
|
.xgmii_txd(qsfp0_txd_2_int),
|
|
.xgmii_txc(qsfp0_txc_2_int),
|
|
.xgmii_rxd(qsfp0_rxd_2_int),
|
|
.xgmii_rxc(qsfp0_rxc_2_int),
|
|
.serdes_tx_data(qsfp0_gt_txdata_2),
|
|
.serdes_tx_hdr(qsfp0_gt_txheader_2),
|
|
.serdes_rx_data(qsfp0_gt_rxdata_2),
|
|
.serdes_rx_hdr(qsfp0_gt_rxheader_2),
|
|
.serdes_rx_bitslip(qsfp0_gt_rxgearboxslip_2),
|
|
.rx_block_lock(qsfp0_rx_block_lock_2),
|
|
.rx_high_ber()
|
|
);
|
|
|
|
assign qsfp0_tx_clk_3_int = clk_156mhz_int;
|
|
assign qsfp0_tx_rst_3_int = rst_156mhz_int;
|
|
|
|
assign qsfp0_rx_clk_3_int = gt_rxusrclk[6];
|
|
|
|
sync_reset #(
|
|
.N(4)
|
|
)
|
|
qsfp0_rx_rst_3_reset_sync_inst (
|
|
.clk(qsfp0_rx_clk_3_int),
|
|
.rst(~gt_reset_rx_done),
|
|
.out(qsfp0_rx_rst_3_int)
|
|
);
|
|
|
|
eth_phy_10g #(
|
|
.BIT_REVERSE(1)
|
|
)
|
|
qsfp0_phy_3_inst (
|
|
.tx_clk(qsfp0_tx_clk_3_int),
|
|
.tx_rst(qsfp0_tx_rst_3_int),
|
|
.rx_clk(qsfp0_rx_clk_3_int),
|
|
.rx_rst(qsfp0_rx_rst_3_int),
|
|
.xgmii_txd(qsfp0_txd_3_int),
|
|
.xgmii_txc(qsfp0_txc_3_int),
|
|
.xgmii_rxd(qsfp0_rxd_3_int),
|
|
.xgmii_rxc(qsfp0_rxc_3_int),
|
|
.serdes_tx_data(qsfp0_gt_txdata_3),
|
|
.serdes_tx_hdr(qsfp0_gt_txheader_3),
|
|
.serdes_rx_data(qsfp0_gt_rxdata_3),
|
|
.serdes_rx_hdr(qsfp0_gt_rxheader_3),
|
|
.serdes_rx_bitslip(qsfp0_gt_rxgearboxslip_3),
|
|
.rx_block_lock(qsfp0_rx_block_lock_3),
|
|
.rx_high_ber()
|
|
);
|
|
|
|
assign qsfp0_tx_clk_4_int = clk_156mhz_int;
|
|
assign qsfp0_tx_rst_4_int = rst_156mhz_int;
|
|
|
|
assign qsfp0_rx_clk_4_int = gt_rxusrclk[7];
|
|
|
|
sync_reset #(
|
|
.N(4)
|
|
)
|
|
qsfp0_rx_rst_4_reset_sync_inst (
|
|
.clk(qsfp0_rx_clk_4_int),
|
|
.rst(~gt_reset_rx_done),
|
|
.out(qsfp0_rx_rst_4_int)
|
|
);
|
|
|
|
eth_phy_10g #(
|
|
.BIT_REVERSE(1)
|
|
)
|
|
qsfp0_phy_4_inst (
|
|
.tx_clk(qsfp0_tx_clk_4_int),
|
|
.tx_rst(qsfp0_tx_rst_4_int),
|
|
.rx_clk(qsfp0_rx_clk_4_int),
|
|
.rx_rst(qsfp0_rx_rst_4_int),
|
|
.xgmii_txd(qsfp0_txd_4_int),
|
|
.xgmii_txc(qsfp0_txc_4_int),
|
|
.xgmii_rxd(qsfp0_rxd_4_int),
|
|
.xgmii_rxc(qsfp0_rxc_4_int),
|
|
.serdes_tx_data(qsfp0_gt_txdata_4),
|
|
.serdes_tx_hdr(qsfp0_gt_txheader_4),
|
|
.serdes_rx_data(qsfp0_gt_rxdata_4),
|
|
.serdes_rx_hdr(qsfp0_gt_rxheader_4),
|
|
.serdes_rx_bitslip(qsfp0_gt_rxgearboxslip_4),
|
|
.rx_block_lock(qsfp0_rx_block_lock_4),
|
|
.rx_high_ber()
|
|
);
|
|
|
|
assign qsfp1_tx_clk_1_int = clk_156mhz_int;
|
|
assign qsfp1_tx_rst_1_int = rst_156mhz_int;
|
|
|
|
assign qsfp1_rx_clk_1_int = gt_rxusrclk[0];
|
|
|
|
sync_reset #(
|
|
.N(4)
|
|
)
|
|
qsfp1_rx_rst_1_reset_sync_inst (
|
|
.clk(qsfp1_rx_clk_1_int),
|
|
.rst(~gt_reset_rx_done),
|
|
.out(qsfp1_rx_rst_1_int)
|
|
);
|
|
|
|
eth_phy_10g #(
|
|
.BIT_REVERSE(1)
|
|
)
|
|
qsfp1_phy_1_inst (
|
|
.tx_clk(qsfp1_tx_clk_1_int),
|
|
.tx_rst(qsfp1_tx_rst_1_int),
|
|
.rx_clk(qsfp1_rx_clk_1_int),
|
|
.rx_rst(qsfp1_rx_rst_1_int),
|
|
.xgmii_txd(qsfp1_txd_1_int),
|
|
.xgmii_txc(qsfp1_txc_1_int),
|
|
.xgmii_rxd(qsfp1_rxd_1_int),
|
|
.xgmii_rxc(qsfp1_rxc_1_int),
|
|
.serdes_tx_data(qsfp1_gt_txdata_1),
|
|
.serdes_tx_hdr(qsfp1_gt_txheader_1),
|
|
.serdes_rx_data(qsfp1_gt_rxdata_1),
|
|
.serdes_rx_hdr(qsfp1_gt_rxheader_1),
|
|
.serdes_rx_bitslip(qsfp1_gt_rxgearboxslip_1),
|
|
.rx_block_lock(qsfp1_rx_block_lock_1),
|
|
.rx_high_ber()
|
|
);
|
|
|
|
assign qsfp1_tx_clk_2_int = clk_156mhz_int;
|
|
assign qsfp1_tx_rst_2_int = rst_156mhz_int;
|
|
|
|
assign qsfp1_rx_clk_2_int = gt_rxusrclk[1];
|
|
|
|
sync_reset #(
|
|
.N(4)
|
|
)
|
|
qsfp1_rx_rst_2_reset_sync_inst (
|
|
.clk(qsfp1_rx_clk_2_int),
|
|
.rst(~gt_reset_rx_done),
|
|
.out(qsfp1_rx_rst_2_int)
|
|
);
|
|
|
|
eth_phy_10g #(
|
|
.BIT_REVERSE(1)
|
|
)
|
|
qsfp1_phy_2_inst (
|
|
.tx_clk(qsfp1_tx_clk_2_int),
|
|
.tx_rst(qsfp1_tx_rst_2_int),
|
|
.rx_clk(qsfp1_rx_clk_2_int),
|
|
.rx_rst(qsfp1_rx_rst_2_int),
|
|
.xgmii_txd(qsfp1_txd_2_int),
|
|
.xgmii_txc(qsfp1_txc_2_int),
|
|
.xgmii_rxd(qsfp1_rxd_2_int),
|
|
.xgmii_rxc(qsfp1_rxc_2_int),
|
|
.serdes_tx_data(qsfp1_gt_txdata_2),
|
|
.serdes_tx_hdr(qsfp1_gt_txheader_2),
|
|
.serdes_rx_data(qsfp1_gt_rxdata_2),
|
|
.serdes_rx_hdr(qsfp1_gt_rxheader_2),
|
|
.serdes_rx_bitslip(qsfp1_gt_rxgearboxslip_2),
|
|
.rx_block_lock(qsfp1_rx_block_lock_2),
|
|
.rx_high_ber()
|
|
);
|
|
|
|
assign qsfp1_tx_clk_3_int = clk_156mhz_int;
|
|
assign qsfp1_tx_rst_3_int = rst_156mhz_int;
|
|
|
|
assign qsfp1_rx_clk_3_int = gt_rxusrclk[2];
|
|
|
|
sync_reset #(
|
|
.N(4)
|
|
)
|
|
qsfp1_rx_rst_3_reset_sync_inst (
|
|
.clk(qsfp1_rx_clk_3_int),
|
|
.rst(~gt_reset_rx_done),
|
|
.out(qsfp1_rx_rst_3_int)
|
|
);
|
|
|
|
eth_phy_10g #(
|
|
.BIT_REVERSE(1)
|
|
)
|
|
qsfp1_phy_3_inst (
|
|
.tx_clk(qsfp1_tx_clk_3_int),
|
|
.tx_rst(qsfp1_tx_rst_3_int),
|
|
.rx_clk(qsfp1_rx_clk_3_int),
|
|
.rx_rst(qsfp1_rx_rst_3_int),
|
|
.xgmii_txd(qsfp1_txd_3_int),
|
|
.xgmii_txc(qsfp1_txc_3_int),
|
|
.xgmii_rxd(qsfp1_rxd_3_int),
|
|
.xgmii_rxc(qsfp1_rxc_3_int),
|
|
.serdes_tx_data(qsfp1_gt_txdata_3),
|
|
.serdes_tx_hdr(qsfp1_gt_txheader_3),
|
|
.serdes_rx_data(qsfp1_gt_rxdata_3),
|
|
.serdes_rx_hdr(qsfp1_gt_rxheader_3),
|
|
.serdes_rx_bitslip(qsfp1_gt_rxgearboxslip_3),
|
|
.rx_block_lock(qsfp1_rx_block_lock_3),
|
|
.rx_high_ber()
|
|
);
|
|
|
|
assign qsfp1_tx_clk_4_int = clk_156mhz_int;
|
|
assign qsfp1_tx_rst_4_int = rst_156mhz_int;
|
|
|
|
assign qsfp1_rx_clk_4_int = gt_rxusrclk[3];
|
|
|
|
sync_reset #(
|
|
.N(4)
|
|
)
|
|
qsfp1_rx_rst_4_reset_sync_inst (
|
|
.clk(qsfp1_rx_clk_4_int),
|
|
.rst(~gt_reset_rx_done),
|
|
.out(qsfp1_rx_rst_4_int)
|
|
);
|
|
|
|
eth_phy_10g #(
|
|
.BIT_REVERSE(1)
|
|
)
|
|
qsfp1_phy_4_inst (
|
|
.tx_clk(qsfp1_tx_clk_4_int),
|
|
.tx_rst(qsfp1_tx_rst_4_int),
|
|
.rx_clk(qsfp1_rx_clk_4_int),
|
|
.rx_rst(qsfp1_rx_rst_4_int),
|
|
.xgmii_txd(qsfp1_txd_4_int),
|
|
.xgmii_txc(qsfp1_txc_4_int),
|
|
.xgmii_rxd(qsfp1_rxd_4_int),
|
|
.xgmii_rxc(qsfp1_rxc_4_int),
|
|
.serdes_tx_data(qsfp1_gt_txdata_4),
|
|
.serdes_tx_hdr(qsfp1_gt_txheader_4),
|
|
.serdes_rx_data(qsfp1_gt_rxdata_4),
|
|
.serdes_rx_hdr(qsfp1_gt_rxheader_4),
|
|
.serdes_rx_bitslip(qsfp1_gt_rxgearboxslip_4),
|
|
.rx_block_lock(qsfp1_rx_block_lock_4),
|
|
.rx_high_ber()
|
|
);
|
|
|
|
fpga_core
|
|
core_inst (
|
|
/*
|
|
* Clock: 156.25 MHz
|
|
* Synchronous reset
|
|
*/
|
|
.clk(clk_156mhz_int),
|
|
.rst(rst_156mhz_int),
|
|
/*
|
|
* GPIO
|
|
*/
|
|
.sw(sw_int),
|
|
.led(led),
|
|
/*
|
|
* Ethernet: QSFP28
|
|
*/
|
|
.qsfp0_tx_clk_1(qsfp0_tx_clk_1_int),
|
|
.qsfp0_tx_rst_1(qsfp0_tx_rst_1_int),
|
|
.qsfp0_txd_1(qsfp0_txd_1_int),
|
|
.qsfp0_txc_1(qsfp0_txc_1_int),
|
|
.qsfp0_rx_clk_1(qsfp0_rx_clk_1_int),
|
|
.qsfp0_rx_rst_1(qsfp0_rx_rst_1_int),
|
|
.qsfp0_rxd_1(qsfp0_rxd_1_int),
|
|
.qsfp0_rxc_1(qsfp0_rxc_1_int),
|
|
.qsfp0_tx_clk_2(qsfp0_tx_clk_2_int),
|
|
.qsfp0_tx_rst_2(qsfp0_tx_rst_2_int),
|
|
.qsfp0_txd_2(qsfp0_txd_2_int),
|
|
.qsfp0_txc_2(qsfp0_txc_2_int),
|
|
.qsfp0_rx_clk_2(qsfp0_rx_clk_2_int),
|
|
.qsfp0_rx_rst_2(qsfp0_rx_rst_2_int),
|
|
.qsfp0_rxd_2(qsfp0_rxd_2_int),
|
|
.qsfp0_rxc_2(qsfp0_rxc_2_int),
|
|
.qsfp0_tx_clk_3(qsfp0_tx_clk_3_int),
|
|
.qsfp0_tx_rst_3(qsfp0_tx_rst_3_int),
|
|
.qsfp0_txd_3(qsfp0_txd_3_int),
|
|
.qsfp0_txc_3(qsfp0_txc_3_int),
|
|
.qsfp0_rx_clk_3(qsfp0_rx_clk_3_int),
|
|
.qsfp0_rx_rst_3(qsfp0_rx_rst_3_int),
|
|
.qsfp0_rxd_3(qsfp0_rxd_3_int),
|
|
.qsfp0_rxc_3(qsfp0_rxc_3_int),
|
|
.qsfp0_tx_clk_4(qsfp0_tx_clk_4_int),
|
|
.qsfp0_tx_rst_4(qsfp0_tx_rst_4_int),
|
|
.qsfp0_txd_4(qsfp0_txd_4_int),
|
|
.qsfp0_txc_4(qsfp0_txc_4_int),
|
|
.qsfp0_rx_clk_4(qsfp0_rx_clk_4_int),
|
|
.qsfp0_rx_rst_4(qsfp0_rx_rst_4_int),
|
|
.qsfp0_rxd_4(qsfp0_rxd_4_int),
|
|
.qsfp0_rxc_4(qsfp0_rxc_4_int),
|
|
.qsfp1_tx_clk_1(qsfp1_tx_clk_1_int),
|
|
.qsfp1_tx_rst_1(qsfp1_tx_rst_1_int),
|
|
.qsfp1_txd_1(qsfp1_txd_1_int),
|
|
.qsfp1_txc_1(qsfp1_txc_1_int),
|
|
.qsfp1_rx_clk_1(qsfp1_rx_clk_1_int),
|
|
.qsfp1_rx_rst_1(qsfp1_rx_rst_1_int),
|
|
.qsfp1_rxd_1(qsfp1_rxd_1_int),
|
|
.qsfp1_rxc_1(qsfp1_rxc_1_int),
|
|
.qsfp1_tx_clk_2(qsfp1_tx_clk_2_int),
|
|
.qsfp1_tx_rst_2(qsfp1_tx_rst_2_int),
|
|
.qsfp1_txd_2(qsfp1_txd_2_int),
|
|
.qsfp1_txc_2(qsfp1_txc_2_int),
|
|
.qsfp1_rx_clk_2(qsfp1_rx_clk_2_int),
|
|
.qsfp1_rx_rst_2(qsfp1_rx_rst_2_int),
|
|
.qsfp1_rxd_2(qsfp1_rxd_2_int),
|
|
.qsfp1_rxc_2(qsfp1_rxc_2_int),
|
|
.qsfp1_tx_clk_3(qsfp1_tx_clk_3_int),
|
|
.qsfp1_tx_rst_3(qsfp1_tx_rst_3_int),
|
|
.qsfp1_txd_3(qsfp1_txd_3_int),
|
|
.qsfp1_txc_3(qsfp1_txc_3_int),
|
|
.qsfp1_rx_clk_3(qsfp1_rx_clk_3_int),
|
|
.qsfp1_rx_rst_3(qsfp1_rx_rst_3_int),
|
|
.qsfp1_rxd_3(qsfp1_rxd_3_int),
|
|
.qsfp1_rxc_3(qsfp1_rxc_3_int),
|
|
.qsfp1_tx_clk_4(qsfp1_tx_clk_4_int),
|
|
.qsfp1_tx_rst_4(qsfp1_tx_rst_4_int),
|
|
.qsfp1_txd_4(qsfp1_txd_4_int),
|
|
.qsfp1_txc_4(qsfp1_txc_4_int),
|
|
.qsfp1_rx_clk_4(qsfp1_rx_clk_4_int),
|
|
.qsfp1_rx_rst_4(qsfp1_rx_rst_4_int),
|
|
.qsfp1_rxd_4(qsfp1_rxd_4_int),
|
|
.qsfp1_rxc_4(qsfp1_rxc_4_int),
|
|
/*
|
|
* UART: 115200 bps, 8N1
|
|
*/
|
|
.uart_rxd(uart_rxd),
|
|
.uart_txd(uart_txd_int)
|
|
);
|
|
|
|
endmodule
|