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FPGA
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corundum
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Alex Forencich
ad453b12db
Add AXI lite RAM module and testbench
2018-08-14 23:49:40 -07:00
..
axi_fifo_rd.v
Add AXI FIFOs and testbenches
2018-08-13 15:31:04 -07:00
axi_fifo_wr.v
Add AXI FIFOs and testbenches
2018-08-13 15:31:04 -07:00
axi_fifo.v
Add AXI FIFOs and testbenches
2018-08-13 15:31:04 -07:00
axi_ram.v
Fix some more issues in AXI RAM module
2018-08-13 16:00:29 -07:00
axi_register_rd.v
Add AXI registers and testbenches
2018-08-13 23:36:47 -07:00
axi_register_wr.v
Add AXI registers and testbenches
2018-08-13 23:36:47 -07:00
axi_register.v
Add AXI registers and testbenches
2018-08-13 23:36:47 -07:00
axil_ram.v
Add AXI lite RAM module and testbench
2018-08-14 23:49:40 -07:00