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corundum/example/AU50/fpga_axi/rtl
History
Alex Forencich e4508b242f Update example designs
2021-08-02 18:36:25 -07:00
..
axi_ram.v
Add AU50 AXI example design
2020-07-17 00:04:13 -07:00
axis_register.v
Add AU50 AXI example design
2020-07-17 00:04:13 -07:00
fpga_core.v
Update example designs
2021-08-02 18:36:25 -07:00
fpga.v
Add AU50 AXI example design
2020-07-17 00:04:13 -07:00
sync_reset.v
Add AU50 AXI example design
2020-07-17 00:04:13 -07:00
sync_signal.v
Add AU50 AXI example design
2020-07-17 00:04:13 -07:00