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327 lines
13 KiB
Verilog
327 lines
13 KiB
Verilog
/*
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Copyright (c) 2019-2021 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* DMA RAM demux (write)
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*/
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module dma_ram_demux_wr #
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(
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// Number of ports
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parameter PORTS = 2,
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// RAM segment count
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parameter SEG_COUNT = 2,
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// RAM segment data width
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parameter SEG_DATA_WIDTH = 64,
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// RAM segment byte enable width
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parameter SEG_BE_WIDTH = SEG_DATA_WIDTH/8,
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// RAM segment address width
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parameter SEG_ADDR_WIDTH = 8,
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// Input RAM segment select width
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parameter S_RAM_SEL_WIDTH = 2,
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// Output RAM segment select width
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// Additional bits required for response routing
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parameter M_RAM_SEL_WIDTH = S_RAM_SEL_WIDTH+$clog2(PORTS)
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)
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(
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input wire clk,
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input wire rst,
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/*
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* RAM interface (from DMA interface)
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*/
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input wire [SEG_COUNT*M_RAM_SEL_WIDTH-1:0] ctrl_wr_cmd_sel,
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input wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ctrl_wr_cmd_be,
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input wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_wr_cmd_addr,
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input wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_wr_cmd_data,
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input wire [SEG_COUNT-1:0] ctrl_wr_cmd_valid,
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output wire [SEG_COUNT-1:0] ctrl_wr_cmd_ready,
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output wire [SEG_COUNT-1:0] ctrl_wr_done,
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/*
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* RAM interface (towards RAM)
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*/
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output wire [PORTS*SEG_COUNT*S_RAM_SEL_WIDTH-1:0] ram_wr_cmd_sel,
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output wire [PORTS*SEG_COUNT*SEG_BE_WIDTH-1:0] ram_wr_cmd_be,
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output wire [PORTS*SEG_COUNT*SEG_ADDR_WIDTH-1:0] ram_wr_cmd_addr,
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output wire [PORTS*SEG_COUNT*SEG_DATA_WIDTH-1:0] ram_wr_cmd_data,
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output wire [PORTS*SEG_COUNT-1:0] ram_wr_cmd_valid,
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input wire [PORTS*SEG_COUNT-1:0] ram_wr_cmd_ready,
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input wire [PORTS*SEG_COUNT-1:0] ram_wr_done
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);
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parameter CL_PORTS = $clog2(PORTS);
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parameter S_RAM_SEL_WIDTH_INT = S_RAM_SEL_WIDTH > 0 ? S_RAM_SEL_WIDTH : 1;
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parameter FIFO_ADDR_WIDTH = 5;
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// check configuration
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initial begin
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if (M_RAM_SEL_WIDTH < S_RAM_SEL_WIDTH+$clog2(PORTS)) begin
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$error("Error: M_RAM_SEL_WIDTH must be at least $clog2(PORTS) larger than S_RAM_SEL_WIDTH (instance %m)");
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$finish;
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end
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end
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generate
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genvar n, p;
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for (n = 0; n < SEG_COUNT; n = n + 1) begin
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// FIFO to maintain response ordering
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reg [FIFO_ADDR_WIDTH+1-1:0] fifo_wr_ptr_reg = 0;
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reg [FIFO_ADDR_WIDTH+1-1:0] fifo_rd_ptr_reg = 0;
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(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
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reg [CL_PORTS-1:0] fifo_sel[(2**FIFO_ADDR_WIDTH)-1:0];
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wire fifo_empty = fifo_wr_ptr_reg == fifo_rd_ptr_reg;
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wire fifo_full = fifo_wr_ptr_reg == (fifo_rd_ptr_reg ^ (1 << FIFO_ADDR_WIDTH));
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integer i;
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initial begin
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for (i = 0; i < 2**FIFO_ADDR_WIDTH; i = i + 1) begin
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fifo_sel[i] = 0;
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end
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end
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// RAM write command demux
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wire [M_RAM_SEL_WIDTH-1:0] seg_ctrl_wr_cmd_sel = ctrl_wr_cmd_sel[M_RAM_SEL_WIDTH*n +: M_RAM_SEL_WIDTH];
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wire [SEG_BE_WIDTH-1:0] seg_ctrl_wr_cmd_be = ctrl_wr_cmd_be[SEG_BE_WIDTH*n +: SEG_BE_WIDTH];
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wire [SEG_ADDR_WIDTH-1:0] seg_ctrl_wr_cmd_addr = ctrl_wr_cmd_addr[SEG_ADDR_WIDTH*n +: SEG_ADDR_WIDTH];
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wire [SEG_DATA_WIDTH-1:0] seg_ctrl_wr_cmd_data = ctrl_wr_cmd_data[SEG_DATA_WIDTH*n +: SEG_DATA_WIDTH];
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wire seg_ctrl_wr_cmd_valid = ctrl_wr_cmd_valid[n];
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wire seg_ctrl_wr_cmd_ready;
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assign ctrl_wr_cmd_ready[n] = seg_ctrl_wr_cmd_ready;
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wire [PORTS*S_RAM_SEL_WIDTH-1:0] seg_ram_wr_cmd_sel;
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wire [PORTS*SEG_BE_WIDTH-1:0] seg_ram_wr_cmd_be;
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wire [PORTS*SEG_ADDR_WIDTH-1:0] seg_ram_wr_cmd_addr;
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wire [PORTS*SEG_DATA_WIDTH-1:0] seg_ram_wr_cmd_data;
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wire [PORTS-1:0] seg_ram_wr_cmd_valid;
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wire [PORTS-1:0] seg_ram_wr_cmd_ready;
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for (p = 0; p < PORTS; p = p + 1) begin
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if (S_RAM_SEL_WIDTH > 0) begin
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assign ram_wr_cmd_sel[(p*SEG_COUNT+n)*S_RAM_SEL_WIDTH +: S_RAM_SEL_WIDTH_INT] = seg_ram_wr_cmd_sel[p*S_RAM_SEL_WIDTH +: S_RAM_SEL_WIDTH_INT];
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end
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assign ram_wr_cmd_be[(p*SEG_COUNT+n)*SEG_BE_WIDTH +: SEG_BE_WIDTH] = seg_ram_wr_cmd_be[p*SEG_BE_WIDTH +: SEG_BE_WIDTH];
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assign ram_wr_cmd_addr[(p*SEG_COUNT+n)*SEG_ADDR_WIDTH +: SEG_ADDR_WIDTH] = seg_ram_wr_cmd_addr[p*SEG_ADDR_WIDTH +: SEG_ADDR_WIDTH];
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assign ram_wr_cmd_data[(p*SEG_COUNT+n)*SEG_DATA_WIDTH +: SEG_DATA_WIDTH] = seg_ram_wr_cmd_data[p*SEG_DATA_WIDTH +: SEG_DATA_WIDTH];
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assign ram_wr_cmd_valid[p*SEG_COUNT+n] = seg_ram_wr_cmd_valid[p];
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assign seg_ram_wr_cmd_ready[p] = ram_wr_cmd_ready[p*SEG_COUNT+n];
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end
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if (S_RAM_SEL_WIDTH == 0) begin
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assign ram_wr_cmd_sel = 0;
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end
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// internal datapath
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reg [S_RAM_SEL_WIDTH-1:0] seg_ram_wr_cmd_sel_int;
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reg [SEG_BE_WIDTH-1:0] seg_ram_wr_cmd_be_int;
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reg [SEG_ADDR_WIDTH-1:0] seg_ram_wr_cmd_addr_int;
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reg [SEG_DATA_WIDTH-1:0] seg_ram_wr_cmd_data_int;
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reg [PORTS-1:0] seg_ram_wr_cmd_valid_int;
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reg seg_ram_wr_cmd_ready_int_reg = 1'b0;
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wire seg_ram_wr_cmd_ready_int_early;
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assign seg_ctrl_wr_cmd_ready = seg_ram_wr_cmd_ready_int_reg && !fifo_full;
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wire [CL_PORTS-1:0] select_cmd = PORTS > 1 ? (seg_ctrl_wr_cmd_sel >> (M_RAM_SEL_WIDTH - CL_PORTS)) : 0;
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always @* begin
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seg_ram_wr_cmd_sel_int = seg_ctrl_wr_cmd_sel;
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seg_ram_wr_cmd_be_int = seg_ctrl_wr_cmd_be;
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seg_ram_wr_cmd_addr_int = seg_ctrl_wr_cmd_addr;
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seg_ram_wr_cmd_data_int = seg_ctrl_wr_cmd_data;
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seg_ram_wr_cmd_valid_int = (seg_ctrl_wr_cmd_valid && seg_ctrl_wr_cmd_ready) << select_cmd;
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end
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always @(posedge clk) begin
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if (seg_ctrl_wr_cmd_valid && seg_ctrl_wr_cmd_ready) begin
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fifo_sel[fifo_wr_ptr_reg[FIFO_ADDR_WIDTH-1:0]] <= select_cmd;
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fifo_wr_ptr_reg <= fifo_wr_ptr_reg + 1;
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end
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if (rst) begin
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fifo_wr_ptr_reg <= 0;
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end
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end
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// output datapath logic
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reg [S_RAM_SEL_WIDTH-1:0] seg_ram_wr_cmd_sel_reg = {S_RAM_SEL_WIDTH_INT{1'b0}};
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reg [SEG_BE_WIDTH-1:0] seg_ram_wr_cmd_be_reg = {SEG_BE_WIDTH{1'b0}};
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reg [SEG_ADDR_WIDTH-1:0] seg_ram_wr_cmd_addr_reg = {SEG_ADDR_WIDTH{1'b0}};
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reg [SEG_DATA_WIDTH-1:0] seg_ram_wr_cmd_data_reg = {SEG_DATA_WIDTH{1'b0}};
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reg [PORTS-1:0] seg_ram_wr_cmd_valid_reg = {PORTS{1'b0}}, seg_ram_wr_cmd_valid_next;
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reg [S_RAM_SEL_WIDTH-1:0] temp_seg_ram_wr_cmd_sel_reg = {S_RAM_SEL_WIDTH_INT{1'b0}};
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reg [SEG_BE_WIDTH-1:0] temp_seg_ram_wr_cmd_be_reg = {SEG_BE_WIDTH{1'b0}};
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reg [SEG_ADDR_WIDTH-1:0] temp_seg_ram_wr_cmd_addr_reg = {SEG_ADDR_WIDTH{1'b0}};
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reg [SEG_DATA_WIDTH-1:0] temp_seg_ram_wr_cmd_data_reg = {SEG_DATA_WIDTH{1'b0}};
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reg [PORTS-1:0] temp_seg_ram_wr_cmd_valid_reg = {PORTS{1'b0}}, temp_seg_ram_wr_cmd_valid_next;
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// datapath control
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reg store_axis_resp_int_to_output;
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reg store_axis_resp_int_to_temp;
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reg store_axis_resp_temp_to_output;
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assign seg_ram_wr_cmd_sel = {PORTS{seg_ram_wr_cmd_sel_reg}};
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assign seg_ram_wr_cmd_be = {PORTS{seg_ram_wr_cmd_be_reg}};
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assign seg_ram_wr_cmd_addr = {PORTS{seg_ram_wr_cmd_addr_reg}};
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assign seg_ram_wr_cmd_data = {PORTS{seg_ram_wr_cmd_data_reg}};
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assign seg_ram_wr_cmd_valid = seg_ram_wr_cmd_valid_reg;
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// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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assign seg_ram_wr_cmd_ready_int_early = (seg_ram_wr_cmd_ready & seg_ram_wr_cmd_valid_reg) || (!temp_seg_ram_wr_cmd_valid_reg && (!seg_ram_wr_cmd_valid_reg || !seg_ram_wr_cmd_valid_int));
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always @* begin
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// transfer sink ready state to source
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seg_ram_wr_cmd_valid_next = seg_ram_wr_cmd_valid_reg;
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temp_seg_ram_wr_cmd_valid_next = temp_seg_ram_wr_cmd_valid_reg;
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store_axis_resp_int_to_output = 1'b0;
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store_axis_resp_int_to_temp = 1'b0;
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store_axis_resp_temp_to_output = 1'b0;
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if (seg_ram_wr_cmd_ready_int_reg) begin
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// input is ready
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if ((seg_ram_wr_cmd_ready & seg_ram_wr_cmd_valid_reg) || !seg_ram_wr_cmd_valid_reg) begin
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// output is ready or currently not valid, transfer data to output
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seg_ram_wr_cmd_valid_next = seg_ram_wr_cmd_valid_int;
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store_axis_resp_int_to_output = 1'b1;
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end else begin
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// output is not ready, store input in temp
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temp_seg_ram_wr_cmd_valid_next = seg_ram_wr_cmd_valid_int;
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store_axis_resp_int_to_temp = 1'b1;
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end
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end else if (seg_ram_wr_cmd_ready & seg_ram_wr_cmd_valid_reg) begin
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// input is not ready, but output is ready
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seg_ram_wr_cmd_valid_next = temp_seg_ram_wr_cmd_valid_reg;
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temp_seg_ram_wr_cmd_valid_next = {PORTS{1'b0}};
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store_axis_resp_temp_to_output = 1'b1;
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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seg_ram_wr_cmd_valid_reg <= {PORTS{1'b0}};
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seg_ram_wr_cmd_ready_int_reg <= 1'b0;
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temp_seg_ram_wr_cmd_valid_reg <= {PORTS{1'b0}};
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end else begin
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seg_ram_wr_cmd_valid_reg <= seg_ram_wr_cmd_valid_next;
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seg_ram_wr_cmd_ready_int_reg <= seg_ram_wr_cmd_ready_int_early;
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temp_seg_ram_wr_cmd_valid_reg <= temp_seg_ram_wr_cmd_valid_next;
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end
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// datapath
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if (store_axis_resp_int_to_output) begin
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seg_ram_wr_cmd_sel_reg <= seg_ram_wr_cmd_sel_int;
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seg_ram_wr_cmd_be_reg <= seg_ram_wr_cmd_be_int;
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seg_ram_wr_cmd_addr_reg <= seg_ram_wr_cmd_addr_int;
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seg_ram_wr_cmd_data_reg <= seg_ram_wr_cmd_data_int;
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end else if (store_axis_resp_temp_to_output) begin
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seg_ram_wr_cmd_sel_reg <= temp_seg_ram_wr_cmd_sel_reg;
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seg_ram_wr_cmd_be_reg <= temp_seg_ram_wr_cmd_be_reg;
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seg_ram_wr_cmd_addr_reg <= temp_seg_ram_wr_cmd_addr_reg;
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seg_ram_wr_cmd_data_reg <= temp_seg_ram_wr_cmd_data_reg;
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end
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if (store_axis_resp_int_to_temp) begin
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temp_seg_ram_wr_cmd_sel_reg <= seg_ram_wr_cmd_sel_int;
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temp_seg_ram_wr_cmd_be_reg <= seg_ram_wr_cmd_be_int;
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temp_seg_ram_wr_cmd_addr_reg <= seg_ram_wr_cmd_addr_int;
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temp_seg_ram_wr_cmd_data_reg <= seg_ram_wr_cmd_data_int;
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end
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end
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// RAM write done mux
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wire [PORTS-1:0] seg_ram_wr_done;
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wire [PORTS-1:0] seg_ram_wr_done_sel;
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wire seg_ctrl_wr_done;
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for (p = 0; p < PORTS; p = p + 1) begin
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assign seg_ram_wr_done[p] = ram_wr_done[p*SEG_COUNT+n];
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end
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assign ctrl_wr_done[n] = seg_ctrl_wr_done;
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wire [CL_PORTS-1:0] select_resp = fifo_sel[fifo_rd_ptr_reg[FIFO_ADDR_WIDTH-1:0]];
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for (p = 0; p < PORTS; p = p + 1) begin
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reg [FIFO_ADDR_WIDTH+1-1:0] done_count_reg = 0;
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reg done_reg = 1'b0;
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assign seg_ram_wr_done_sel[p] = done_reg;
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always @(posedge clk) begin
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if (select_resp == p && (done_count_reg != 0 || seg_ram_wr_done[p])) begin
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done_reg <= 1'b1;
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if (!seg_ram_wr_done[p]) begin
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done_count_reg <= done_count_reg - 1;
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end
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end else begin
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done_reg <= 1'b0;
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if (seg_ram_wr_done[p]) begin
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done_count_reg <= done_count_reg + 1;
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end
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end
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if (rst) begin
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done_count_reg <= 0;
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done_reg <= 1'b0;
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end
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end
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end
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assign seg_ctrl_wr_done = seg_ram_wr_done_sel != 0;
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always @(posedge clk) begin
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if (seg_ctrl_wr_done && !fifo_empty) begin
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fifo_rd_ptr_reg <= fifo_rd_ptr_reg + 1;
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end
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if (rst) begin
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fifo_rd_ptr_reg <= 0;
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end
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end
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end
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endgenerate
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endmodule
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`resetall
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