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141 lines
5.7 KiB
Makefile
141 lines
5.7 KiB
Makefile
# Copyright (c) 2021 Alex Forencich
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#
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# Permission is hereby granted, free of charge, to any person obtaining a copy
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# of this software and associated documentation files (the "Software"), to deal
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# in the Software without restriction, including without limitation the rights
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# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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# copies of the Software, and to permit persons to whom the Software is
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# furnished to do so, subject to the following conditions:
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#
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# The above copyright notice and this permission notice shall be included in
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# all copies or substantial portions of the Software.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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# THE SOFTWARE.
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TOPLEVEL_LANG = verilog
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SIM ?= icarus
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WAVES ?= 0
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COCOTB_HDL_TIMEUNIT = 1ns
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COCOTB_HDL_TIMEPRECISION = 1ps
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export PARAM_S_COUNT ?= 4
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export PARAM_M_COUNT ?= 4
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DUT = axis_ram_switch
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WRAPPER = $(DUT)_wrap_$(PARAM_S_COUNT)x$(PARAM_M_COUNT)
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TOPLEVEL = $(WRAPPER)
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MODULE = test_$(DUT)
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VERILOG_SOURCES += $(WRAPPER).v
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VERILOG_SOURCES += ../../rtl/$(DUT).v
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VERILOG_SOURCES += ../../rtl/axis_adapter.v
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VERILOG_SOURCES += ../../rtl/arbiter.v
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VERILOG_SOURCES += ../../rtl/priority_encoder.v
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# module parameters
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export PARAM_FIFO_DEPTH ?= 4096
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export PARAM_CMD_FIFO_DEPTH ?= 32
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export PARAM_SPEEDUP ?= 0
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export PARAM_S_DATA_WIDTH ?= 8
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export PARAM_S_KEEP_ENABLE ?= $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 )
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export PARAM_S_KEEP_WIDTH ?= $(shell expr $(PARAM_S_DATA_WIDTH) / 8 )
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export PARAM_M_DATA_WIDTH ?= 8
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export PARAM_M_KEEP_ENABLE ?= $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 )
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export PARAM_M_KEEP_WIDTH ?= $(shell expr $(PARAM_M_DATA_WIDTH) / 8 )
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export PARAM_ID_ENABLE ?= 1
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export PARAM_ID_WIDTH ?= 16
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export PARAM_DEST_WIDTH ?= 8
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export PARAM_USER_ENABLE ?= 1
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export PARAM_USER_WIDTH ?= 1
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export PARAM_USER_BAD_FRAME_VALUE ?= 1
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export PARAM_USER_BAD_FRAME_MASK ?= 1
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export PARAM_DROP_BAD_FRAME ?= 0
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export PARAM_DROP_WHEN_FULL ?= 0
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export PARAM_ARB_TYPE_ROUND_ROBIN ?= 1
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export PARAM_ARB_LSB_HIGH_PRIORITY ?= 1
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export PARAM_RAM_PIPELINE ?= 2
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ifeq ($(SIM), icarus)
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PLUSARGS += -fst
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COMPILE_ARGS += -P $(TOPLEVEL).FIFO_DEPTH=$(PARAM_FIFO_DEPTH)
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COMPILE_ARGS += -P $(TOPLEVEL).CMD_FIFO_DEPTH=$(PARAM_CMD_FIFO_DEPTH)
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COMPILE_ARGS += -P $(TOPLEVEL).SPEEDUP=$(PARAM_SPEEDUP)
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COMPILE_ARGS += -P $(TOPLEVEL).S_DATA_WIDTH=$(PARAM_S_DATA_WIDTH)
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COMPILE_ARGS += -P $(TOPLEVEL).S_KEEP_ENABLE=$(PARAM_S_KEEP_ENABLE)
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COMPILE_ARGS += -P $(TOPLEVEL).S_KEEP_WIDTH=$(PARAM_S_KEEP_WIDTH)
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COMPILE_ARGS += -P $(TOPLEVEL).M_DATA_WIDTH=$(PARAM_M_DATA_WIDTH)
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COMPILE_ARGS += -P $(TOPLEVEL).M_KEEP_ENABLE=$(PARAM_M_KEEP_ENABLE)
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COMPILE_ARGS += -P $(TOPLEVEL).M_KEEP_WIDTH=$(PARAM_M_KEEP_WIDTH)
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COMPILE_ARGS += -P $(TOPLEVEL).ID_ENABLE=$(PARAM_ID_ENABLE)
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COMPILE_ARGS += -P $(TOPLEVEL).ID_WIDTH=$(PARAM_ID_WIDTH)
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COMPILE_ARGS += -P $(TOPLEVEL).DEST_WIDTH=$(PARAM_DEST_WIDTH)
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COMPILE_ARGS += -P $(TOPLEVEL).USER_ENABLE=$(PARAM_USER_ENABLE)
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COMPILE_ARGS += -P $(TOPLEVEL).USER_WIDTH=$(PARAM_USER_WIDTH)
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COMPILE_ARGS += -P $(TOPLEVEL).USER_BAD_FRAME_VALUE=$(PARAM_USER_BAD_FRAME_VALUE)
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COMPILE_ARGS += -P $(TOPLEVEL).USER_BAD_FRAME_MASK=$(PARAM_USER_BAD_FRAME_MASK)
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COMPILE_ARGS += -P $(TOPLEVEL).DROP_BAD_FRAME=$(PARAM_DROP_BAD_FRAME)
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COMPILE_ARGS += -P $(TOPLEVEL).DROP_WHEN_FULL=$(PARAM_DROP_WHEN_FULL)
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COMPILE_ARGS += -P $(TOPLEVEL).ARB_TYPE_ROUND_ROBIN=$(PARAM_ARB_TYPE_ROUND_ROBIN)
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COMPILE_ARGS += -P $(TOPLEVEL).ARB_LSB_HIGH_PRIORITY=$(PARAM_ARB_LSB_HIGH_PRIORITY)
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COMPILE_ARGS += -P $(TOPLEVEL).RAM_PIPELINE=$(PARAM_RAM_PIPELINE)
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ifeq ($(WAVES), 1)
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VERILOG_SOURCES += iverilog_dump.v
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COMPILE_ARGS += -s iverilog_dump
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endif
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else ifeq ($(SIM), verilator)
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COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
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COMPILE_ARGS += -GFIFO_DEPTH=$(PARAM_FIFO_DEPTH)
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COMPILE_ARGS += -GCMD_FIFO_DEPTH=$(PARAM_CMD_FIFO_DEPTH)
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COMPILE_ARGS += -GSPEEDUP=$(PARAM_SPEEDUP)
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COMPILE_ARGS += -GS_DATA_WIDTH=$(PARAM_S_DATA_WIDTH)
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COMPILE_ARGS += -GS_KEEP_ENABLE=$(PARAM_S_KEEP_ENABLE)
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COMPILE_ARGS += -GS_KEEP_WIDTH=$(PARAM_S_KEEP_WIDTH)
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COMPILE_ARGS += -GM_DATA_WIDTH=$(PARAM_M_DATA_WIDTH)
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COMPILE_ARGS += -GM_KEEP_ENABLE=$(PARAM_M_KEEP_ENABLE)
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COMPILE_ARGS += -GM_KEEP_WIDTH=$(PARAM_M_KEEP_WIDTH)
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COMPILE_ARGS += -GID_ENABLE=$(PARAM_ID_ENABLE)
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COMPILE_ARGS += -GID_WIDTH=$(PARAM_ID_WIDTH)
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COMPILE_ARGS += -GDEST_WIDTH=$(PARAM_DEST_WIDTH)
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COMPILE_ARGS += -GUSER_ENABLE=$(PARAM_USER_ENABLE)
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COMPILE_ARGS += -GUSER_WIDTH=$(PARAM_USER_WIDTH)
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COMPILE_ARGS += -GUSER_BAD_FRAME_VALUE=$(PARAM_USER_BAD_FRAME_VALUE)
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COMPILE_ARGS += -GUSER_BAD_FRAME_MASK=$(PARAM_USER_BAD_FRAME_MASK)
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COMPILE_ARGS += -GDROP_BAD_FRAME=$(PARAM_DROP_BAD_FRAME)
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COMPILE_ARGS += -GDROP_WHEN_FULL=$(PARAM_DROP_WHEN_FULL)
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COMPILE_ARGS += -GARB_TYPE_ROUND_ROBIN=$(PARAM_ARB_TYPE_ROUND_ROBIN)
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COMPILE_ARGS += -GARB_LSB_HIGH_PRIORITY=$(PARAM_ARB_LSB_HIGH_PRIORITY)
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COMPILE_ARGS += -GRAM_PIPELINE=$(PARAM_RAM_PIPELINE)
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ifeq ($(WAVES), 1)
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COMPILE_ARGS += --trace-fst
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endif
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endif
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include $(shell cocotb-config --makefiles)/Makefile.sim
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$(WRAPPER).v: ../../rtl/$(DUT)_wrap.py
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$< -p $(PARAM_S_COUNT) $(PARAM_M_COUNT)
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iverilog_dump.v:
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echo 'module iverilog_dump();' > $@
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echo 'initial begin' >> $@
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echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@
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echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@
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echo 'end' >> $@
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echo 'endmodule' >> $@
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clean::
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@rm -rf iverilog_dump.v
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@rm -rf dump.fst $(TOPLEVEL).fst
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@rm -rf *_wrap_*.v
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