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219 lines
7.1 KiB
Verilog
219 lines
7.1 KiB
Verilog
/*
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Copyright 2019, The Regents of the University of California.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
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IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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The views and conclusions contained in the software and documentation are those
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of the authors and should not be interpreted as representing official policies,
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either expressed or implied, of The Regents of the University of California.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* Testbench for queue_manager
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*/
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module test_queue_manager;
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// Parameters
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parameter ADDR_WIDTH = 64;
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parameter REQ_TAG_WIDTH = 8;
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parameter OP_TABLE_SIZE = 16;
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parameter OP_TAG_WIDTH = 8;
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parameter QUEUE_INDEX_WIDTH = 8;
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parameter CPL_INDEX_WIDTH = 8;
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parameter QUEUE_PTR_WIDTH = 16;
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parameter LOG_QUEUE_SIZE_WIDTH = 4;
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parameter DESC_SIZE = 16;
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parameter PIPELINE = 2;
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parameter AXIL_DATA_WIDTH = 32;
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parameter AXIL_ADDR_WIDTH = 16;
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parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8);
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// Inputs
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reg clk = 0;
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reg rst = 0;
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reg [7:0] current_test = 0;
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reg [QUEUE_INDEX_WIDTH-1:0] s_axis_dequeue_req_queue = 0;
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reg [REQ_TAG_WIDTH-1:0] s_axis_dequeue_req_tag = 0;
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reg s_axis_dequeue_req_valid = 0;
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reg m_axis_dequeue_resp_ready = 0;
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reg [OP_TAG_WIDTH-1:0] s_axis_dequeue_commit_op_tag = 0;
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reg s_axis_dequeue_commit_valid = 0;
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reg [AXIL_ADDR_WIDTH-1:0] s_axil_awaddr = 0;
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reg [2:0] s_axil_awprot = 0;
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reg s_axil_awvalid = 0;
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reg [AXIL_DATA_WIDTH-1:0] s_axil_wdata = 0;
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reg [AXIL_STRB_WIDTH-1:0] s_axil_wstrb = 0;
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reg s_axil_wvalid = 0;
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reg s_axil_bready = 0;
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reg [AXIL_ADDR_WIDTH-1:0] s_axil_araddr = 0;
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reg [2:0] s_axil_arprot = 0;
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reg s_axil_arvalid = 0;
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reg s_axil_rready = 0;
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reg enable = 0;
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// Outputs
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wire s_axis_dequeue_req_ready;
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wire [QUEUE_INDEX_WIDTH-1:0] m_axis_dequeue_resp_queue;
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wire [QUEUE_PTR_WIDTH-1:0] m_axis_dequeue_resp_ptr;
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wire [ADDR_WIDTH-1:0] m_axis_dequeue_resp_addr;
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wire [CPL_INDEX_WIDTH-1:0] m_axis_dequeue_resp_cpl;
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wire [REQ_TAG_WIDTH-1:0] m_axis_dequeue_resp_tag;
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wire [OP_TAG_WIDTH-1:0] m_axis_dequeue_resp_op_tag;
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wire m_axis_dequeue_resp_empty;
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wire m_axis_dequeue_resp_error;
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wire m_axis_dequeue_resp_valid;
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wire s_axis_dequeue_commit_ready;
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wire [QUEUE_INDEX_WIDTH-1:0] m_axis_doorbell_queue;
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wire m_axis_doorbell_valid;
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wire s_axil_awready;
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wire s_axil_wready;
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wire [1:0] s_axil_bresp;
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wire s_axil_bvalid;
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wire s_axil_arready;
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wire [AXIL_DATA_WIDTH-1:0] s_axil_rdata;
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wire [1:0] s_axil_rresp;
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wire s_axil_rvalid;
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initial begin
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// myhdl integration
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$from_myhdl(
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clk,
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rst,
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current_test,
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s_axis_dequeue_req_queue,
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s_axis_dequeue_req_tag,
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s_axis_dequeue_req_valid,
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m_axis_dequeue_resp_ready,
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s_axis_dequeue_commit_op_tag,
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s_axis_dequeue_commit_valid,
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s_axil_awaddr,
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s_axil_awprot,
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s_axil_awvalid,
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s_axil_wdata,
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s_axil_wstrb,
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s_axil_wvalid,
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s_axil_bready,
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s_axil_araddr,
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s_axil_arprot,
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s_axil_arvalid,
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s_axil_rready,
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enable
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);
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$to_myhdl(
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s_axis_dequeue_req_ready,
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m_axis_dequeue_resp_queue,
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m_axis_dequeue_resp_ptr,
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m_axis_dequeue_resp_addr,
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m_axis_dequeue_resp_cpl,
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m_axis_dequeue_resp_tag,
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m_axis_dequeue_resp_op_tag,
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m_axis_dequeue_resp_empty,
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m_axis_dequeue_resp_error,
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m_axis_dequeue_resp_valid,
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s_axis_dequeue_commit_ready,
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m_axis_doorbell_queue,
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m_axis_doorbell_valid,
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s_axil_awready,
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s_axil_wready,
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s_axil_bresp,
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s_axil_bvalid,
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s_axil_arready,
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s_axil_rdata,
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s_axil_rresp,
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s_axil_rvalid
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);
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// dump file
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$dumpfile("test_queue_manager.lxt");
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$dumpvars(0, test_queue_manager);
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end
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queue_manager #(
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.ADDR_WIDTH(ADDR_WIDTH),
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.REQ_TAG_WIDTH(REQ_TAG_WIDTH),
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.OP_TABLE_SIZE(OP_TABLE_SIZE),
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.OP_TAG_WIDTH(OP_TAG_WIDTH),
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.QUEUE_INDEX_WIDTH(QUEUE_INDEX_WIDTH),
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.CPL_INDEX_WIDTH(CPL_INDEX_WIDTH),
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.QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH),
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.LOG_QUEUE_SIZE_WIDTH(LOG_QUEUE_SIZE_WIDTH),
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.DESC_SIZE(DESC_SIZE),
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.PIPELINE(PIPELINE),
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.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
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.AXIL_ADDR_WIDTH(AXIL_ADDR_WIDTH),
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.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH)
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)
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UUT (
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.clk(clk),
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.rst(rst),
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.s_axis_dequeue_req_queue(s_axis_dequeue_req_queue),
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.s_axis_dequeue_req_tag(s_axis_dequeue_req_tag),
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.s_axis_dequeue_req_valid(s_axis_dequeue_req_valid),
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.s_axis_dequeue_req_ready(s_axis_dequeue_req_ready),
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.m_axis_dequeue_resp_queue(m_axis_dequeue_resp_queue),
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.m_axis_dequeue_resp_ptr(m_axis_dequeue_resp_ptr),
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.m_axis_dequeue_resp_addr(m_axis_dequeue_resp_addr),
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.m_axis_dequeue_resp_cpl(m_axis_dequeue_resp_cpl),
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.m_axis_dequeue_resp_tag(m_axis_dequeue_resp_tag),
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.m_axis_dequeue_resp_op_tag(m_axis_dequeue_resp_op_tag),
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.m_axis_dequeue_resp_empty(m_axis_dequeue_resp_empty),
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.m_axis_dequeue_resp_error(m_axis_dequeue_resp_error),
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.m_axis_dequeue_resp_valid(m_axis_dequeue_resp_valid),
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.m_axis_dequeue_resp_ready(m_axis_dequeue_resp_ready),
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.s_axis_dequeue_commit_op_tag(s_axis_dequeue_commit_op_tag),
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.s_axis_dequeue_commit_valid(s_axis_dequeue_commit_valid),
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.s_axis_dequeue_commit_ready(s_axis_dequeue_commit_ready),
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.m_axis_doorbell_queue(m_axis_doorbell_queue),
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.m_axis_doorbell_valid(m_axis_doorbell_valid),
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.s_axil_awaddr(s_axil_awaddr),
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.s_axil_awprot(s_axil_awprot),
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.s_axil_awvalid(s_axil_awvalid),
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.s_axil_awready(s_axil_awready),
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.s_axil_wdata(s_axil_wdata),
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.s_axil_wstrb(s_axil_wstrb),
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.s_axil_wvalid(s_axil_wvalid),
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.s_axil_wready(s_axil_wready),
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.s_axil_bresp(s_axil_bresp),
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.s_axil_bvalid(s_axil_bvalid),
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.s_axil_bready(s_axil_bready),
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.s_axil_araddr(s_axil_araddr),
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.s_axil_arprot(s_axil_arprot),
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.s_axil_arvalid(s_axil_arvalid),
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.s_axil_arready(s_axil_arready),
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.s_axil_rdata(s_axil_rdata),
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.s_axil_rresp(s_axil_rresp),
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.s_axil_rvalid(s_axil_rvalid),
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.s_axil_rready(s_axil_rready),
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.enable(enable)
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);
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endmodule
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