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182 lines
5.3 KiB
Verilog
182 lines
5.3 KiB
Verilog
/*
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Copyright 2019, The Regents of the University of California.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
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IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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The views and conclusions contained in the software and documentation are those
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of the authors and should not be interpreted as representing official policies,
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either expressed or implied, of The Regents of the University of California.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* Testbench for tdma_ber
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*/
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module test_tdma_ber;
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// Parameters
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parameter COUNT = 2;
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parameter INDEX_WIDTH = 6;
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parameter SLICE_WIDTH = 5;
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parameter AXIL_DATA_WIDTH = 32;
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parameter AXIL_ADDR_WIDTH = INDEX_WIDTH+4+1+$clog2(COUNT);
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parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8);
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parameter SCHEDULE_START_S = 48'h0;
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parameter SCHEDULE_START_NS = 30'h0;
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parameter SCHEDULE_PERIOD_S = 48'd0;
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parameter SCHEDULE_PERIOD_NS = 30'd1000000;
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parameter TIMESLOT_PERIOD_S = 48'd0;
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parameter TIMESLOT_PERIOD_NS = 30'd100000;
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parameter ACTIVE_PERIOD_S = 48'd0;
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parameter ACTIVE_PERIOD_NS = 30'd100000;
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// Inputs
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reg clk = 0;
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reg rst = 0;
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reg [7:0] current_test = 0;
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reg [COUNT-1:0] phy_tx_clk = 0;
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reg [COUNT-1:0] phy_rx_clk = 0;
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reg [COUNT*7-1:0] phy_rx_error_count = 0;
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reg [AXIL_ADDR_WIDTH-1:0] s_axil_awaddr = 0;
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reg [2:0] s_axil_awprot = 0;
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reg s_axil_awvalid = 0;
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reg [AXIL_DATA_WIDTH-1:0] s_axil_wdata = 0;
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reg [AXIL_STRB_WIDTH-1:0] s_axil_wstrb = 0;
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reg s_axil_wvalid = 0;
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reg s_axil_bready = 0;
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reg [AXIL_ADDR_WIDTH-1:0] s_axil_araddr = 0;
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reg [2:0] s_axil_arprot = 0;
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reg s_axil_arvalid = 0;
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reg s_axil_rready = 0;
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reg [95:0] ptp_ts_96 = 0;
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reg ptp_ts_step = 0;
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// Outputs
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wire [COUNT-1:0] phy_tx_prbs31_enable;
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wire [COUNT-1:0] phy_rx_prbs31_enable;
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wire s_axil_awready;
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wire s_axil_wready;
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wire [1:0] s_axil_bresp;
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wire s_axil_bvalid;
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wire s_axil_arready;
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wire [AXIL_DATA_WIDTH-1:0] s_axil_rdata;
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wire [1:0] s_axil_rresp;
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wire s_axil_rvalid;
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initial begin
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// myhdl integration
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$from_myhdl(
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clk,
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rst,
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current_test,
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phy_tx_clk,
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phy_rx_clk,
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phy_rx_error_count,
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s_axil_awaddr,
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s_axil_awprot,
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s_axil_awvalid,
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s_axil_wdata,
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s_axil_wstrb,
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s_axil_wvalid,
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s_axil_bready,
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s_axil_araddr,
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s_axil_arprot,
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s_axil_arvalid,
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s_axil_rready,
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ptp_ts_96,
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ptp_ts_step
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);
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$to_myhdl(
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phy_tx_prbs31_enable,
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phy_rx_prbs31_enable,
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s_axil_awready,
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s_axil_wready,
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s_axil_bresp,
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s_axil_bvalid,
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s_axil_arready,
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s_axil_rdata,
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s_axil_rresp,
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s_axil_rvalid
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);
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// dump file
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$dumpfile("test_tdma_ber.lxt");
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$dumpvars(0, test_tdma_ber);
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end
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tdma_ber #(
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.COUNT(COUNT),
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.INDEX_WIDTH(INDEX_WIDTH),
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.SLICE_WIDTH(SLICE_WIDTH),
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.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
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.AXIL_ADDR_WIDTH(AXIL_ADDR_WIDTH),
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.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
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.SCHEDULE_START_S(SCHEDULE_START_S),
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.SCHEDULE_START_NS(SCHEDULE_START_NS),
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.SCHEDULE_PERIOD_S(SCHEDULE_PERIOD_S),
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.SCHEDULE_PERIOD_NS(SCHEDULE_PERIOD_NS),
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.TIMESLOT_PERIOD_S(TIMESLOT_PERIOD_S),
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.TIMESLOT_PERIOD_NS(TIMESLOT_PERIOD_NS),
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.ACTIVE_PERIOD_S(ACTIVE_PERIOD_S),
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.ACTIVE_PERIOD_NS(ACTIVE_PERIOD_NS)
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)
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UUT (
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.clk(clk),
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.rst(rst),
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.phy_tx_clk(phy_tx_clk),
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.phy_rx_clk(phy_rx_clk),
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.phy_rx_error_count(phy_rx_error_count),
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.phy_tx_prbs31_enable(phy_tx_prbs31_enable),
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.phy_rx_prbs31_enable(phy_rx_prbs31_enable),
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.s_axil_awaddr(s_axil_awaddr),
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.s_axil_awprot(s_axil_awprot),
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.s_axil_awvalid(s_axil_awvalid),
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.s_axil_awready(s_axil_awready),
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.s_axil_wdata(s_axil_wdata),
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.s_axil_wstrb(s_axil_wstrb),
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.s_axil_wvalid(s_axil_wvalid),
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.s_axil_wready(s_axil_wready),
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.s_axil_bresp(s_axil_bresp),
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.s_axil_bvalid(s_axil_bvalid),
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.s_axil_bready(s_axil_bready),
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.s_axil_araddr(s_axil_araddr),
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.s_axil_arprot(s_axil_arprot),
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.s_axil_arvalid(s_axil_arvalid),
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.s_axil_arready(s_axil_arready),
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.s_axil_rdata(s_axil_rdata),
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.s_axil_rresp(s_axil_rresp),
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.s_axil_rvalid(s_axil_rvalid),
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.s_axil_rready(s_axil_rready),
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.ptp_ts_96(ptp_ts_96),
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.ptp_ts_step(ptp_ts_step)
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);
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endmodule
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