Alex Forencich 52068fbb31 fpga/mqnic: Rename Intel development kit designs based on part number ...

Signed-off-by: Alex Forencich <alex@alexforencich.com>

2023-04-20 21:51:35 -07:00

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app

Add RX indirection table

2023-04-10 15:05:32 -07:00

common

fpga/common: Increase event FIFO size

2023-04-14 01:03:19 -07:00

lib

merged changes in axi

2023-03-30 00:13:02 -07:00

mqnic

fpga/mqnic: Rename Intel development kit designs based on part number

2023-04-20 21:51:35 -07:00

build_images_project.ini

Rework build_images settings

2022-07-13 01:18:42 -07:00

build_images.py

fpga/build_images.py: update quartus message parsing

2022-08-04 13:40:34 -07:00

collect_utilization.py

Add build automation scripts

2022-03-02 23:20:59 -08:00

watch.sh

Change interval

2022-07-13 01:18:55 -07:00