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98 lines
2.4 KiB
Verilog
98 lines
2.4 KiB
Verilog
/*
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Copyright (c) 2014-2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* Testbench for axis_ll_bridge
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*/
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module test_axis_ll_bridge;
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// Parameters
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parameter DATA_WIDTH = 8;
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// Inputs
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reg clk = 0;
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reg rst = 0;
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reg [7:0] current_test = 0;
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reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
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reg s_axis_tvalid = 0;
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reg s_axis_tlast = 0;
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reg ll_dst_rdy_in_n = 1;
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// Outputs
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wire [DATA_WIDTH-1:0] ll_data_out;
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wire ll_sof_out_n;
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wire ll_eof_out_n;
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wire ll_src_rdy_out_n;
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wire s_axis_tready;
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initial begin
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// myhdl integration
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$from_myhdl(
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clk,
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rst,
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current_test,
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s_axis_tdata,
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s_axis_tvalid,
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s_axis_tlast,
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ll_dst_rdy_in_n
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);
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$to_myhdl(
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ll_data_out,
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ll_sof_out_n,
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ll_eof_out_n,
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ll_src_rdy_out_n,
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s_axis_tready
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);
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// dump file
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$dumpfile("test_axis_ll_bridge.lxt");
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$dumpvars(0, test_axis_ll_bridge);
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end
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axis_ll_bridge #(
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.DATA_WIDTH(DATA_WIDTH)
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)
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UUT (
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.clk(clk),
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.rst(rst),
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// axi input
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.s_axis_tdata(s_axis_tdata),
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.s_axis_tvalid(s_axis_tvalid),
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.s_axis_tready(s_axis_tready),
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.s_axis_tlast(s_axis_tlast),
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// locallink output
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.ll_data_out(ll_data_out),
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.ll_sof_out_n(ll_sof_out_n),
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.ll_eof_out_n(ll_eof_out_n),
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.ll_src_rdy_out_n(ll_src_rdy_out_n),
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.ll_dst_rdy_in_n(ll_dst_rdy_in_n)
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);
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endmodule
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