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411 lines
17 KiB
Verilog
411 lines
17 KiB
Verilog
/*
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Copyright (c) 2021 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI DMA interface
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*/
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module dma_if_axi #
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(
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// Width of AXI data bus in bits
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parameter AXI_DATA_WIDTH = 32,
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// Width of AXI address bus in bits
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parameter AXI_ADDR_WIDTH = 16,
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// Width of AXI wstrb (width of data bus in words)
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parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8),
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// Width of AXI ID signal
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parameter AXI_ID_WIDTH = 8,
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// Maximum AXI burst length to generate
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parameter AXI_MAX_BURST_LEN = 256,
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// RAM select width
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parameter RAM_SEL_WIDTH = 2,
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// RAM address width
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parameter RAM_ADDR_WIDTH = 16,
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// RAM segment count
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parameter RAM_SEG_COUNT = 2,
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// RAM segment data width
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parameter RAM_SEG_DATA_WIDTH = AXI_DATA_WIDTH*2/RAM_SEG_COUNT,
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// RAM segment byte enable width
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parameter RAM_SEG_BE_WIDTH = RAM_SEG_DATA_WIDTH/8,
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// RAM segment address width
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parameter RAM_SEG_ADDR_WIDTH = RAM_ADDR_WIDTH-$clog2(RAM_SEG_COUNT*RAM_SEG_BE_WIDTH),
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// Immediate enable
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parameter IMM_ENABLE = 0,
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// Immediate width
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parameter IMM_WIDTH = 32,
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// Length field width
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parameter LEN_WIDTH = 16,
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// Tag field width
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parameter TAG_WIDTH = 8,
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// Operation table size (read)
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parameter READ_OP_TABLE_SIZE = 2**(AXI_ID_WIDTH),
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// Operation table size (write)
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parameter WRITE_OP_TABLE_SIZE = 2**(AXI_ID_WIDTH),
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// Use AXI ID signals (read)
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parameter READ_USE_AXI_ID = 0,
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// Use AXI ID signals (write)
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parameter WRITE_USE_AXI_ID = 1
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI master interface
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*/
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output wire [AXI_ID_WIDTH-1:0] m_axi_awid,
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output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
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output wire [7:0] m_axi_awlen,
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output wire [2:0] m_axi_awsize,
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output wire [1:0] m_axi_awburst,
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output wire m_axi_awlock,
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output wire [3:0] m_axi_awcache,
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output wire [2:0] m_axi_awprot,
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output wire m_axi_awvalid,
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input wire m_axi_awready,
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output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata,
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output wire [AXI_STRB_WIDTH-1:0] m_axi_wstrb,
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output wire m_axi_wlast,
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output wire m_axi_wvalid,
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input wire m_axi_wready,
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input wire [AXI_ID_WIDTH-1:0] m_axi_bid,
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input wire [1:0] m_axi_bresp,
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input wire m_axi_bvalid,
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output wire m_axi_bready,
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output wire [AXI_ID_WIDTH-1:0] m_axi_arid,
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output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr,
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output wire [7:0] m_axi_arlen,
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output wire [2:0] m_axi_arsize,
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output wire [1:0] m_axi_arburst,
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output wire m_axi_arlock,
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output wire [3:0] m_axi_arcache,
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output wire [2:0] m_axi_arprot,
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output wire m_axi_arvalid,
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input wire m_axi_arready,
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input wire [AXI_ID_WIDTH-1:0] m_axi_rid,
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input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata,
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input wire [1:0] m_axi_rresp,
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input wire m_axi_rlast,
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input wire m_axi_rvalid,
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output wire m_axi_rready,
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/*
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* AXI read descriptor input
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*/
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input wire [AXI_ADDR_WIDTH-1:0] s_axis_read_desc_axi_addr,
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input wire [RAM_SEL_WIDTH-1:0] s_axis_read_desc_ram_sel,
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input wire [RAM_ADDR_WIDTH-1:0] s_axis_read_desc_ram_addr,
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input wire [LEN_WIDTH-1:0] s_axis_read_desc_len,
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input wire [TAG_WIDTH-1:0] s_axis_read_desc_tag,
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input wire s_axis_read_desc_valid,
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output wire s_axis_read_desc_ready,
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/*
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* AXI read descriptor status output
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*/
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output wire [TAG_WIDTH-1:0] m_axis_read_desc_status_tag,
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output wire [3:0] m_axis_read_desc_status_error,
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output wire m_axis_read_desc_status_valid,
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/*
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* AXI write descriptor input
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*/
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input wire [AXI_ADDR_WIDTH-1:0] s_axis_write_desc_axi_addr,
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input wire [RAM_SEL_WIDTH-1:0] s_axis_write_desc_ram_sel,
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input wire [RAM_ADDR_WIDTH-1:0] s_axis_write_desc_ram_addr,
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input wire [IMM_WIDTH-1:0] s_axis_write_desc_imm,
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input wire s_axis_write_desc_imm_en,
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input wire [LEN_WIDTH-1:0] s_axis_write_desc_len,
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input wire [TAG_WIDTH-1:0] s_axis_write_desc_tag,
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input wire s_axis_write_desc_valid,
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output wire s_axis_write_desc_ready,
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/*
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* AXI write descriptor status output
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*/
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output wire [TAG_WIDTH-1:0] m_axis_write_desc_status_tag,
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output wire [3:0] m_axis_write_desc_status_error,
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output wire m_axis_write_desc_status_valid,
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/*
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* RAM interface
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*/
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output wire [RAM_SEG_COUNT*RAM_SEL_WIDTH-1:0] ram_wr_cmd_sel,
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output wire [RAM_SEG_COUNT*RAM_SEG_BE_WIDTH-1:0] ram_wr_cmd_be,
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output wire [RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0] ram_wr_cmd_addr,
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output wire [RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0] ram_wr_cmd_data,
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output wire [RAM_SEG_COUNT-1:0] ram_wr_cmd_valid,
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input wire [RAM_SEG_COUNT-1:0] ram_wr_cmd_ready,
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input wire [RAM_SEG_COUNT-1:0] ram_wr_done,
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output wire [RAM_SEG_COUNT*RAM_SEL_WIDTH-1:0] ram_rd_cmd_sel,
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output wire [RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0] ram_rd_cmd_addr,
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output wire [RAM_SEG_COUNT-1:0] ram_rd_cmd_valid,
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input wire [RAM_SEG_COUNT-1:0] ram_rd_cmd_ready,
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input wire [RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0] ram_rd_resp_data,
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input wire [RAM_SEG_COUNT-1:0] ram_rd_resp_valid,
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output wire [RAM_SEG_COUNT-1:0] ram_rd_resp_ready,
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/*
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* Configuration
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*/
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input wire read_enable,
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input wire write_enable,
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/*
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* Statistics
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*/
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output wire [$clog2(READ_OP_TABLE_SIZE)-1:0] stat_rd_op_start_tag,
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output wire [LEN_WIDTH-1:0] stat_rd_op_start_len,
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output wire stat_rd_op_start_valid,
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output wire [$clog2(READ_OP_TABLE_SIZE)-1:0] stat_rd_op_finish_tag,
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output wire [3:0] stat_rd_op_finish_status,
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output wire stat_rd_op_finish_valid,
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output wire [$clog2(READ_OP_TABLE_SIZE)-1:0] stat_rd_req_start_tag,
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output wire [12:0] stat_rd_req_start_len,
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output wire stat_rd_req_start_valid,
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output wire [$clog2(READ_OP_TABLE_SIZE)-1:0] stat_rd_req_finish_tag,
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output wire [3:0] stat_rd_req_finish_status,
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output wire stat_rd_req_finish_valid,
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output wire stat_rd_op_table_full,
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output wire stat_rd_tx_stall,
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output wire [$clog2(WRITE_OP_TABLE_SIZE)-1:0] stat_wr_op_start_tag,
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output wire [LEN_WIDTH-1:0] stat_wr_op_start_len,
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output wire stat_wr_op_start_valid,
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output wire [$clog2(WRITE_OP_TABLE_SIZE)-1:0] stat_wr_op_finish_tag,
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output wire [3:0] stat_wr_op_finish_status,
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output wire stat_wr_op_finish_valid,
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output wire [$clog2(WRITE_OP_TABLE_SIZE)-1:0] stat_wr_req_start_tag,
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output wire [12:0] stat_wr_req_start_len,
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output wire stat_wr_req_start_valid,
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output wire [$clog2(WRITE_OP_TABLE_SIZE)-1:0] stat_wr_req_finish_tag,
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output wire [3:0] stat_wr_req_finish_status,
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output wire stat_wr_req_finish_valid,
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output wire stat_wr_op_table_full,
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output wire stat_wr_tx_stall
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);
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dma_if_axi_rd #(
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.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
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.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
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.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
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.AXI_ID_WIDTH(AXI_ID_WIDTH),
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.AXI_MAX_BURST_LEN(AXI_MAX_BURST_LEN),
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.RAM_SEL_WIDTH(RAM_SEL_WIDTH),
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.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
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.RAM_SEG_COUNT(RAM_SEG_COUNT),
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.RAM_SEG_DATA_WIDTH(RAM_SEG_DATA_WIDTH),
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.RAM_SEG_BE_WIDTH(RAM_SEG_BE_WIDTH),
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.RAM_SEG_ADDR_WIDTH(RAM_SEG_ADDR_WIDTH),
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.LEN_WIDTH(LEN_WIDTH),
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.TAG_WIDTH(TAG_WIDTH),
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.OP_TABLE_SIZE(READ_OP_TABLE_SIZE),
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.USE_AXI_ID(READ_USE_AXI_ID)
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)
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dma_if_axi_rd_inst (
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.clk(clk),
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.rst(rst),
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/*
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* AXI master interface
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*/
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.m_axi_arid(m_axi_arid),
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.m_axi_araddr(m_axi_araddr),
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.m_axi_arlen(m_axi_arlen),
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.m_axi_arsize(m_axi_arsize),
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.m_axi_arburst(m_axi_arburst),
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.m_axi_arlock(m_axi_arlock),
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.m_axi_arcache(m_axi_arcache),
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.m_axi_arprot(m_axi_arprot),
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.m_axi_arvalid(m_axi_arvalid),
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.m_axi_arready(m_axi_arready),
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.m_axi_rid(m_axi_rid),
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.m_axi_rdata(m_axi_rdata),
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.m_axi_rresp(m_axi_rresp),
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.m_axi_rlast(m_axi_rlast),
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.m_axi_rvalid(m_axi_rvalid),
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.m_axi_rready(m_axi_rready),
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/*
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* AXI read descriptor input
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*/
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.s_axis_read_desc_axi_addr(s_axis_read_desc_axi_addr),
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.s_axis_read_desc_ram_sel(s_axis_read_desc_ram_sel),
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.s_axis_read_desc_ram_addr(s_axis_read_desc_ram_addr),
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.s_axis_read_desc_len(s_axis_read_desc_len),
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.s_axis_read_desc_tag(s_axis_read_desc_tag),
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.s_axis_read_desc_valid(s_axis_read_desc_valid),
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.s_axis_read_desc_ready(s_axis_read_desc_ready),
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/*
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* AXI read descriptor status output
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*/
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.m_axis_read_desc_status_tag(m_axis_read_desc_status_tag),
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.m_axis_read_desc_status_error(m_axis_read_desc_status_error),
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.m_axis_read_desc_status_valid(m_axis_read_desc_status_valid),
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/*
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* RAM interface
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*/
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.ram_wr_cmd_sel(ram_wr_cmd_sel),
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.ram_wr_cmd_be(ram_wr_cmd_be),
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.ram_wr_cmd_addr(ram_wr_cmd_addr),
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.ram_wr_cmd_data(ram_wr_cmd_data),
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.ram_wr_cmd_valid(ram_wr_cmd_valid),
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.ram_wr_cmd_ready(ram_wr_cmd_ready),
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.ram_wr_done(ram_wr_done),
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/*
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* Configuration
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*/
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.enable(read_enable),
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/*
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* Statistics
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*/
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.stat_rd_op_start_tag(stat_rd_op_start_tag),
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.stat_rd_op_start_len(stat_rd_op_start_len),
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.stat_rd_op_start_valid(stat_rd_op_start_valid),
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.stat_rd_op_finish_tag(stat_rd_op_finish_tag),
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.stat_rd_op_finish_status(stat_rd_op_finish_status),
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.stat_rd_op_finish_valid(stat_rd_op_finish_valid),
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.stat_rd_req_start_tag(stat_rd_req_start_tag),
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.stat_rd_req_start_len(stat_rd_req_start_len),
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.stat_rd_req_start_valid(stat_rd_req_start_valid),
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.stat_rd_req_finish_tag(stat_rd_req_finish_tag),
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.stat_rd_req_finish_status(stat_rd_req_finish_status),
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.stat_rd_req_finish_valid(stat_rd_req_finish_valid),
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.stat_rd_op_table_full(stat_rd_op_table_full),
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.stat_rd_tx_stall(stat_rd_tx_stall)
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);
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dma_if_axi_wr #(
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.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
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.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
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.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
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.AXI_ID_WIDTH(AXI_ID_WIDTH),
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.AXI_MAX_BURST_LEN(AXI_MAX_BURST_LEN),
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.RAM_SEL_WIDTH(RAM_SEL_WIDTH),
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.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
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.RAM_SEG_COUNT(RAM_SEG_COUNT),
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.RAM_SEG_DATA_WIDTH(RAM_SEG_DATA_WIDTH),
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.RAM_SEG_BE_WIDTH(RAM_SEG_BE_WIDTH),
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.RAM_SEG_ADDR_WIDTH(RAM_SEG_ADDR_WIDTH),
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.IMM_ENABLE(IMM_ENABLE),
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.IMM_WIDTH(IMM_WIDTH),
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.LEN_WIDTH(LEN_WIDTH),
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.TAG_WIDTH(TAG_WIDTH),
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.OP_TABLE_SIZE(WRITE_OP_TABLE_SIZE),
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.USE_AXI_ID(WRITE_USE_AXI_ID)
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)
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dma_if_axi_wr_inst (
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.clk(clk),
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.rst(rst),
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/*
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* AXI master interface
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*/
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.m_axi_awid(m_axi_awid),
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.m_axi_awaddr(m_axi_awaddr),
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.m_axi_awlen(m_axi_awlen),
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.m_axi_awsize(m_axi_awsize),
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.m_axi_awburst(m_axi_awburst),
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.m_axi_awlock(m_axi_awlock),
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.m_axi_awcache(m_axi_awcache),
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.m_axi_awprot(m_axi_awprot),
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.m_axi_awvalid(m_axi_awvalid),
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.m_axi_awready(m_axi_awready),
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.m_axi_wdata(m_axi_wdata),
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.m_axi_wstrb(m_axi_wstrb),
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.m_axi_wlast(m_axi_wlast),
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.m_axi_wvalid(m_axi_wvalid),
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.m_axi_wready(m_axi_wready),
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.m_axi_bid(m_axi_bid),
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.m_axi_bresp(m_axi_bresp),
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.m_axi_bvalid(m_axi_bvalid),
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.m_axi_bready(m_axi_bready),
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/*
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* AXI write descriptor input
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*/
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.s_axis_write_desc_axi_addr(s_axis_write_desc_axi_addr),
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.s_axis_write_desc_ram_sel(s_axis_write_desc_ram_sel),
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.s_axis_write_desc_ram_addr(s_axis_write_desc_ram_addr),
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.s_axis_write_desc_imm(s_axis_write_desc_imm),
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.s_axis_write_desc_imm_en(s_axis_write_desc_imm_en),
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.s_axis_write_desc_len(s_axis_write_desc_len),
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.s_axis_write_desc_tag(s_axis_write_desc_tag),
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.s_axis_write_desc_valid(s_axis_write_desc_valid),
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.s_axis_write_desc_ready(s_axis_write_desc_ready),
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/*
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* AXI write descriptor status output
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*/
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.m_axis_write_desc_status_tag(m_axis_write_desc_status_tag),
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.m_axis_write_desc_status_error(m_axis_write_desc_status_error),
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.m_axis_write_desc_status_valid(m_axis_write_desc_status_valid),
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/*
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* RAM interface
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*/
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.ram_rd_cmd_sel(ram_rd_cmd_sel),
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.ram_rd_cmd_addr(ram_rd_cmd_addr),
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.ram_rd_cmd_valid(ram_rd_cmd_valid),
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.ram_rd_cmd_ready(ram_rd_cmd_ready),
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.ram_rd_resp_data(ram_rd_resp_data),
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.ram_rd_resp_valid(ram_rd_resp_valid),
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.ram_rd_resp_ready(ram_rd_resp_ready),
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/*
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* Configuration
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*/
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.enable(write_enable),
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/*
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* Statistics
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*/
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.stat_wr_op_start_tag(stat_wr_op_start_tag),
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.stat_wr_op_start_len(stat_wr_op_start_len),
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.stat_wr_op_start_valid(stat_wr_op_start_valid),
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.stat_wr_op_finish_tag(stat_wr_op_finish_tag),
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.stat_wr_op_finish_status(stat_wr_op_finish_status),
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.stat_wr_op_finish_valid(stat_wr_op_finish_valid),
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.stat_wr_req_start_tag(stat_wr_req_start_tag),
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.stat_wr_req_start_len(stat_wr_req_start_len),
|
|
.stat_wr_req_start_valid(stat_wr_req_start_valid),
|
|
.stat_wr_req_finish_tag(stat_wr_req_finish_tag),
|
|
.stat_wr_req_finish_status(stat_wr_req_finish_status),
|
|
.stat_wr_req_finish_valid(stat_wr_req_finish_valid),
|
|
.stat_wr_op_table_full(stat_wr_op_table_full),
|
|
.stat_wr_tx_stall(stat_wr_tx_stall)
|
|
);
|
|
|
|
endmodule
|
|
|
|
`resetall
|