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646 lines
24 KiB
Verilog
646 lines
24 KiB
Verilog
/*
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Copyright (c) 2021 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Xilinx UltraScale PCIe interface adapter
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*/
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module pcie_us_if #
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(
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// Width of PCIe AXI stream interfaces in bits
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parameter AXIS_PCIE_DATA_WIDTH = 256,
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// PCIe AXI stream tkeep signal width (words per cycle)
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parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32),
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// PCIe AXI stream RC tuser signal width
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parameter AXIS_PCIE_RC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 75 : 161,
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// PCIe AXI stream RQ tuser signal width
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parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 60 : 137,
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// PCIe AXI stream CQ tuser signal width
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parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
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// PCIe AXI stream CC tuser signal width
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parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
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// RQ sequence number width
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parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
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// TLP data width
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parameter TLP_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH,
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// TLP strobe width
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parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32,
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// TLP header width
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parameter TLP_HDR_WIDTH = 128,
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// TLP segment count
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parameter TLP_SEG_COUNT = 1,
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// TX sequence number count
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parameter TX_SEQ_NUM_COUNT = AXIS_PCIE_DATA_WIDTH < 512 ? 1 : 2,
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// TX sequence number width
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parameter TX_SEQ_NUM_WIDTH = RQ_SEQ_NUM_WIDTH-1,
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// Number of PFs
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parameter PF_COUNT = 1,
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// Number of VFs
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parameter VF_COUNT = 0,
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// Total number of functions
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parameter F_COUNT = PF_COUNT+VF_COUNT,
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// Read extended tag enable bit
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parameter READ_EXT_TAG_ENABLE = 1,
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// Read max read request size field
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parameter READ_MAX_READ_REQ_SIZE = 1,
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// Read max payload size field
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parameter READ_MAX_PAYLOAD_SIZE = 1,
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// enable MSI-X support
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parameter MSIX_ENABLE = 1,
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// enable MSI support
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parameter MSI_ENABLE = 0,
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// MSI vector count
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parameter MSI_COUNT = 32
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI input (RC)
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*/
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input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rc_tdata,
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input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rc_tkeep,
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input wire s_axis_rc_tvalid,
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output wire s_axis_rc_tready,
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input wire s_axis_rc_tlast,
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input wire [AXIS_PCIE_RC_USER_WIDTH-1:0] s_axis_rc_tuser,
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/*
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* AXI output (RQ)
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*/
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output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata,
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output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep,
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output wire m_axis_rq_tvalid,
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input wire m_axis_rq_tready,
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output wire m_axis_rq_tlast,
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output wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser,
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/*
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* AXI input (CQ)
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*/
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input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata,
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input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep,
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input wire s_axis_cq_tvalid,
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output wire s_axis_cq_tready,
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input wire s_axis_cq_tlast,
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input wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser,
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/*
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* AXI output (CC)
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*/
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output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata,
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output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep,
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output wire m_axis_cc_tvalid,
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input wire m_axis_cc_tready,
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output wire m_axis_cc_tlast,
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output wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser,
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/*
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* Transmit sequence number input
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*/
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input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0,
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input wire s_axis_rq_seq_num_valid_0,
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input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1,
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input wire s_axis_rq_seq_num_valid_1,
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/*
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* Flow control
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*/
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input wire [7:0] cfg_fc_ph,
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input wire [11:0] cfg_fc_pd,
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input wire [7:0] cfg_fc_nph,
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input wire [11:0] cfg_fc_npd,
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input wire [7:0] cfg_fc_cplh,
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input wire [11:0] cfg_fc_cpld,
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output wire [2:0] cfg_fc_sel,
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/*
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* Configuration interface
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*/
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output wire [9:0] cfg_mgmt_addr,
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output wire [7:0] cfg_mgmt_function_number,
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output wire cfg_mgmt_write,
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output wire [31:0] cfg_mgmt_write_data,
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output wire [3:0] cfg_mgmt_byte_enable,
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output wire cfg_mgmt_read,
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input wire [31:0] cfg_mgmt_read_data,
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input wire cfg_mgmt_read_write_done,
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/*
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* Interrupt interface
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*/
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input wire [3:0] cfg_interrupt_msi_enable,
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input wire [7:0] cfg_interrupt_msi_vf_enable,
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input wire [11:0] cfg_interrupt_msi_mmenable,
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input wire cfg_interrupt_msi_mask_update,
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input wire [31:0] cfg_interrupt_msi_data,
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output wire [3:0] cfg_interrupt_msi_select,
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output wire [31:0] cfg_interrupt_msi_int,
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output wire [31:0] cfg_interrupt_msi_pending_status,
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output wire cfg_interrupt_msi_pending_status_data_enable,
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output wire [3:0] cfg_interrupt_msi_pending_status_function_num,
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input wire cfg_interrupt_msi_sent,
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input wire cfg_interrupt_msi_fail,
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input wire [3:0] cfg_interrupt_msix_enable,
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input wire [3:0] cfg_interrupt_msix_mask,
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input wire [251:0] cfg_interrupt_msix_vf_enable,
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input wire [251:0] cfg_interrupt_msix_vf_mask,
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output wire [63:0] cfg_interrupt_msix_address,
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output wire [31:0] cfg_interrupt_msix_data,
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output wire cfg_interrupt_msix_int,
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output wire [1:0] cfg_interrupt_msix_vec_pending,
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input wire cfg_interrupt_msix_vec_pending_status,
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input wire cfg_interrupt_msix_sent,
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input wire cfg_interrupt_msix_fail,
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output wire [2:0] cfg_interrupt_msi_attr,
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output wire cfg_interrupt_msi_tph_present,
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output wire [1:0] cfg_interrupt_msi_tph_type,
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output wire [8:0] cfg_interrupt_msi_tph_st_tag,
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output wire [7:0] cfg_interrupt_msi_function_number,
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/*
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* TLP output (request to BAR)
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*/
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output wire [TLP_DATA_WIDTH-1:0] rx_req_tlp_data,
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output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_req_tlp_hdr,
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output wire [TLP_SEG_COUNT*3-1:0] rx_req_tlp_bar_id,
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output wire [TLP_SEG_COUNT*8-1:0] rx_req_tlp_func_num,
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output wire [TLP_SEG_COUNT-1:0] rx_req_tlp_valid,
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output wire [TLP_SEG_COUNT-1:0] rx_req_tlp_sop,
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output wire [TLP_SEG_COUNT-1:0] rx_req_tlp_eop,
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input wire rx_req_tlp_ready,
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/*
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* TLP output (completion to DMA)
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*/
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output wire [TLP_DATA_WIDTH-1:0] rx_cpl_tlp_data,
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output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_cpl_tlp_hdr,
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output wire [TLP_SEG_COUNT*4-1:0] rx_cpl_tlp_error,
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output wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_valid,
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output wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_sop,
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output wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_eop,
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input wire rx_cpl_tlp_ready,
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/*
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* TLP input (read request from DMA)
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*/
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input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_rd_req_tlp_hdr,
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input wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] tx_rd_req_tlp_seq,
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input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_valid,
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input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_sop,
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input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_eop,
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output wire tx_rd_req_tlp_ready,
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/*
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* Transmit sequence number output (DMA read request)
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*/
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output wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] m_axis_rd_req_tx_seq_num,
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output wire [TX_SEQ_NUM_COUNT-1:0] m_axis_rd_req_tx_seq_num_valid,
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/*
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* TLP input (write request from DMA)
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*/
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input wire [TLP_DATA_WIDTH-1:0] tx_wr_req_tlp_data,
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input wire [TLP_STRB_WIDTH-1:0] tx_wr_req_tlp_strb,
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input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_wr_req_tlp_hdr,
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input wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] tx_wr_req_tlp_seq,
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input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_valid,
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input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_sop,
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input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_eop,
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output wire tx_wr_req_tlp_ready,
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/*
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* Transmit sequence number output (DMA write request)
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*/
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output wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] m_axis_wr_req_tx_seq_num,
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output wire [TX_SEQ_NUM_COUNT-1:0] m_axis_wr_req_tx_seq_num_valid,
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/*
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* TLP input (completion from BAR)
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*/
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input wire [TLP_DATA_WIDTH-1:0] tx_cpl_tlp_data,
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input wire [TLP_STRB_WIDTH-1:0] tx_cpl_tlp_strb,
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input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_cpl_tlp_hdr,
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input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_valid,
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input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_sop,
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input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_eop,
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output wire tx_cpl_tlp_ready,
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/*
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* TLP input (write request from MSI-X)
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*/
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input wire [TLP_DATA_WIDTH-1:0] tx_msix_wr_req_tlp_data,
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input wire [TLP_STRB_WIDTH-1:0] tx_msix_wr_req_tlp_strb,
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input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_msix_wr_req_tlp_hdr,
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input wire [TLP_SEG_COUNT-1:0] tx_msix_wr_req_tlp_valid,
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input wire [TLP_SEG_COUNT-1:0] tx_msix_wr_req_tlp_sop,
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input wire [TLP_SEG_COUNT-1:0] tx_msix_wr_req_tlp_eop,
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output wire tx_msix_wr_req_tlp_ready,
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/*
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* Flow control
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*/
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output wire [7:0] tx_fc_ph_av,
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output wire [11:0] tx_fc_pd_av,
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output wire [7:0] tx_fc_nph_av,
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output wire [11:0] tx_fc_npd_av,
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output wire [7:0] tx_fc_cplh_av,
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output wire [11:0] tx_fc_cpld_av,
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/*
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* Configuration outputs
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*/
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output wire [F_COUNT-1:0] ext_tag_enable,
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output wire [F_COUNT*3-1:0] max_read_request_size,
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output wire [F_COUNT*3-1:0] max_payload_size,
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output wire [F_COUNT-1:0] msix_enable,
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output wire [F_COUNT-1:0] msix_mask,
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/*
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* MSI request inputs
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*/
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input wire [MSI_COUNT-1:0] msi_irq
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);
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pcie_us_if_rc #(
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.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
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.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
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.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
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.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
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.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
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.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
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.TLP_SEG_COUNT(TLP_SEG_COUNT)
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)
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pcie_us_if_rc_inst
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(
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.clk(clk),
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.rst(rst),
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/*
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* AXI input (RC)
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*/
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.s_axis_rc_tdata(s_axis_rc_tdata),
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.s_axis_rc_tkeep(s_axis_rc_tkeep),
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.s_axis_rc_tvalid(s_axis_rc_tvalid),
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.s_axis_rc_tready(s_axis_rc_tready),
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.s_axis_rc_tlast(s_axis_rc_tlast),
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.s_axis_rc_tuser(s_axis_rc_tuser),
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/*
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* TLP output (completion to DMA)
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*/
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.rx_cpl_tlp_data(rx_cpl_tlp_data),
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.rx_cpl_tlp_hdr(rx_cpl_tlp_hdr),
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.rx_cpl_tlp_error(rx_cpl_tlp_error),
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.rx_cpl_tlp_valid(rx_cpl_tlp_valid),
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.rx_cpl_tlp_sop(rx_cpl_tlp_sop),
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.rx_cpl_tlp_eop(rx_cpl_tlp_eop),
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.rx_cpl_tlp_ready(rx_cpl_tlp_ready)
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);
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pcie_us_if_rq #(
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.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
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.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
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.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
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.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
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.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
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.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
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.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
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.TLP_SEG_COUNT(TLP_SEG_COUNT),
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.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
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.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH)
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)
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pcie_us_if_rq_inst
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(
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.clk(clk),
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.rst(rst),
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/*
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* AXI output (RQ)
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*/
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.m_axis_rq_tdata(m_axis_rq_tdata),
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.m_axis_rq_tkeep(m_axis_rq_tkeep),
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.m_axis_rq_tvalid(m_axis_rq_tvalid),
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.m_axis_rq_tready(m_axis_rq_tready),
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.m_axis_rq_tlast(m_axis_rq_tlast),
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.m_axis_rq_tuser(m_axis_rq_tuser),
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/*
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* Transmit sequence number input
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*/
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.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
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.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
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.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
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.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
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/*
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* TLP input (read request from DMA)
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*/
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.tx_rd_req_tlp_hdr(tx_rd_req_tlp_hdr),
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.tx_rd_req_tlp_seq(tx_rd_req_tlp_seq),
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.tx_rd_req_tlp_valid(tx_rd_req_tlp_valid),
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.tx_rd_req_tlp_sop(tx_rd_req_tlp_sop),
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.tx_rd_req_tlp_eop(tx_rd_req_tlp_eop),
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.tx_rd_req_tlp_ready(tx_rd_req_tlp_ready),
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/*
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* Transmit sequence number output (DMA read request)
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*/
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.m_axis_rd_req_tx_seq_num(m_axis_rd_req_tx_seq_num),
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.m_axis_rd_req_tx_seq_num_valid(m_axis_rd_req_tx_seq_num_valid),
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/*
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* TLP input (write request from DMA)
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*/
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.tx_wr_req_tlp_data(tx_wr_req_tlp_data),
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.tx_wr_req_tlp_strb(tx_wr_req_tlp_strb),
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.tx_wr_req_tlp_hdr(tx_wr_req_tlp_hdr),
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.tx_wr_req_tlp_seq(tx_wr_req_tlp_seq),
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.tx_wr_req_tlp_valid(tx_wr_req_tlp_valid),
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.tx_wr_req_tlp_sop(tx_wr_req_tlp_sop),
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.tx_wr_req_tlp_eop(tx_wr_req_tlp_eop),
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.tx_wr_req_tlp_ready(tx_wr_req_tlp_ready),
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/*
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* Transmit sequence number output (DMA write request)
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*/
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.m_axis_wr_req_tx_seq_num(m_axis_wr_req_tx_seq_num),
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.m_axis_wr_req_tx_seq_num_valid(m_axis_wr_req_tx_seq_num_valid)
|
|
);
|
|
|
|
pcie_us_if_cq #(
|
|
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
|
|
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
|
|
.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
|
|
.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
|
|
.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
|
|
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
|
|
.TLP_SEG_COUNT(TLP_SEG_COUNT)
|
|
)
|
|
pcie_us_if_cq_inst
|
|
(
|
|
.clk(clk),
|
|
.rst(rst),
|
|
|
|
/*
|
|
* AXI input (CQ)
|
|
*/
|
|
.s_axis_cq_tdata(s_axis_cq_tdata),
|
|
.s_axis_cq_tkeep(s_axis_cq_tkeep),
|
|
.s_axis_cq_tvalid(s_axis_cq_tvalid),
|
|
.s_axis_cq_tready(s_axis_cq_tready),
|
|
.s_axis_cq_tlast(s_axis_cq_tlast),
|
|
.s_axis_cq_tuser(s_axis_cq_tuser),
|
|
|
|
/*
|
|
* TLP output (request to BAR)
|
|
*/
|
|
.rx_req_tlp_data(rx_req_tlp_data),
|
|
.rx_req_tlp_hdr(rx_req_tlp_hdr),
|
|
.rx_req_tlp_bar_id(rx_req_tlp_bar_id),
|
|
.rx_req_tlp_func_num(rx_req_tlp_func_num),
|
|
.rx_req_tlp_valid(rx_req_tlp_valid),
|
|
.rx_req_tlp_sop(rx_req_tlp_sop),
|
|
.rx_req_tlp_eop(rx_req_tlp_eop),
|
|
.rx_req_tlp_ready(rx_req_tlp_ready)
|
|
);
|
|
|
|
pcie_us_if_cc #(
|
|
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
|
|
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
|
|
.AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
|
|
.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
|
|
.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
|
|
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
|
|
.TLP_SEG_COUNT(TLP_SEG_COUNT)
|
|
)
|
|
pcie_us_if_cc_inst
|
|
(
|
|
.clk(clk),
|
|
.rst(rst),
|
|
|
|
/*
|
|
* AXI output (CC)
|
|
*/
|
|
.m_axis_cc_tdata(m_axis_cc_tdata),
|
|
.m_axis_cc_tkeep(m_axis_cc_tkeep),
|
|
.m_axis_cc_tvalid(m_axis_cc_tvalid),
|
|
.m_axis_cc_tready(m_axis_cc_tready),
|
|
.m_axis_cc_tlast(m_axis_cc_tlast),
|
|
.m_axis_cc_tuser(m_axis_cc_tuser),
|
|
|
|
/*
|
|
* TLP input (completion from BAR)
|
|
*/
|
|
.tx_cpl_tlp_data(tx_cpl_tlp_data),
|
|
.tx_cpl_tlp_strb(tx_cpl_tlp_strb),
|
|
.tx_cpl_tlp_hdr(tx_cpl_tlp_hdr),
|
|
.tx_cpl_tlp_valid(tx_cpl_tlp_valid),
|
|
.tx_cpl_tlp_sop(tx_cpl_tlp_sop),
|
|
.tx_cpl_tlp_eop(tx_cpl_tlp_eop),
|
|
.tx_cpl_tlp_ready(tx_cpl_tlp_ready)
|
|
);
|
|
|
|
assign tx_fc_ph_av = cfg_fc_ph;
|
|
assign tx_fc_pd_av = cfg_fc_pd;
|
|
assign tx_fc_nph_av = cfg_fc_nph;
|
|
assign tx_fc_npd_av = cfg_fc_npd;
|
|
assign tx_fc_cplh_av = cfg_fc_cplh;
|
|
assign tx_fc_cpld_av = cfg_fc_cpld;
|
|
|
|
assign cfg_fc_sel = 3'b100;
|
|
|
|
generate
|
|
|
|
if (READ_EXT_TAG_ENABLE || READ_MAX_READ_REQ_SIZE || READ_MAX_PAYLOAD_SIZE) begin
|
|
|
|
pcie_us_cfg #(
|
|
.PF_COUNT(PF_COUNT),
|
|
.VF_COUNT(VF_COUNT),
|
|
.VF_OFFSET(AXIS_PCIE_RQ_USER_WIDTH == 60 ? 64 : 4),
|
|
.PCIE_CAP_OFFSET(AXIS_PCIE_RQ_USER_WIDTH == 60 ? 12'h0C0 : 12'h070)
|
|
)
|
|
pcie_us_cfg_inst (
|
|
.clk(clk),
|
|
.rst(rst),
|
|
|
|
/*
|
|
* Configuration outputs
|
|
*/
|
|
.ext_tag_enable(ext_tag_enable),
|
|
.max_read_request_size(max_read_request_size),
|
|
.max_payload_size(max_payload_size),
|
|
|
|
/*
|
|
* Interface to Ultrascale PCIe IP core
|
|
*/
|
|
.cfg_mgmt_addr(cfg_mgmt_addr),
|
|
.cfg_mgmt_function_number(cfg_mgmt_function_number),
|
|
.cfg_mgmt_write(cfg_mgmt_write),
|
|
.cfg_mgmt_write_data(cfg_mgmt_write_data),
|
|
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
|
|
.cfg_mgmt_read(cfg_mgmt_read),
|
|
.cfg_mgmt_read_data(cfg_mgmt_read_data),
|
|
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done)
|
|
);
|
|
|
|
end else begin
|
|
|
|
assign ext_tag_enable = 0;
|
|
assign max_read_request_size = 0;
|
|
assign max_payload_size = 0;
|
|
|
|
assign cfg_mgmt_addr = 0;
|
|
assign cfg_mgmt_function_number = 0;
|
|
assign cfg_mgmt_write = 0;
|
|
assign cfg_mgmt_write_data = 0;
|
|
assign cfg_mgmt_byte_enable = 0;
|
|
assign cfg_mgmt_read = 0;
|
|
|
|
end
|
|
|
|
assign msix_enable = cfg_interrupt_msix_enable;
|
|
assign msix_mask = cfg_interrupt_msix_mask;
|
|
|
|
wire [7:0] cfg_interrupt_msi_function_number_msix;
|
|
wire [7:0] cfg_interrupt_msi_function_number_msi;
|
|
|
|
assign cfg_interrupt_msi_function_number = (MSI_ENABLE && (!MSIX_ENABLE || cfg_interrupt_msi_int)) ?
|
|
cfg_interrupt_msi_function_number_msi : cfg_interrupt_msi_function_number_msix;
|
|
|
|
if (MSIX_ENABLE) begin
|
|
|
|
reg cfg_interrupt_msix_int_reg = 1'b0;
|
|
reg tx_msix_wr_req_tlp_ready_reg = 1'b0;
|
|
|
|
reg msix_active_reg = 1'b0;
|
|
|
|
assign tx_msix_wr_req_tlp_ready = tx_msix_wr_req_tlp_ready_reg;
|
|
|
|
assign cfg_interrupt_msix_address = {tx_msix_wr_req_tlp_hdr[63:2], 2'b00};
|
|
assign cfg_interrupt_msix_data = tx_msix_wr_req_tlp_data;
|
|
assign cfg_interrupt_msix_int = cfg_interrupt_msix_int_reg;
|
|
assign cfg_interrupt_msi_function_number_msix = tx_msix_wr_req_tlp_hdr[87:80];
|
|
assign cfg_interrupt_msix_vec_pending = 0;
|
|
|
|
always @(posedge clk) begin
|
|
cfg_interrupt_msix_int_reg <= 1'b0;
|
|
tx_msix_wr_req_tlp_ready_reg <= 1'b0;
|
|
|
|
if (!msix_active_reg) begin
|
|
if (tx_msix_wr_req_tlp_valid && !tx_msix_wr_req_tlp_ready) begin
|
|
cfg_interrupt_msix_int_reg <= 1'b1;
|
|
msix_active_reg <= 1'b1;
|
|
end
|
|
end else begin
|
|
if (cfg_interrupt_msix_sent || cfg_interrupt_msix_fail) begin
|
|
tx_msix_wr_req_tlp_ready_reg <= tx_msix_wr_req_tlp_valid;
|
|
msix_active_reg <= 1'b0;
|
|
end
|
|
end
|
|
|
|
if (rst) begin
|
|
cfg_interrupt_msix_int_reg <= 1'b0;
|
|
tx_msix_wr_req_tlp_ready_reg <= 1'b0;
|
|
msix_active_reg <= 1'b0;
|
|
end
|
|
end
|
|
|
|
end else begin
|
|
|
|
assign tx_msix_wr_req_tlp_ready = 0;
|
|
|
|
assign cfg_interrupt_msix_address = 0;
|
|
assign cfg_interrupt_msix_data = 0;
|
|
assign cfg_interrupt_msix_int = 0;
|
|
assign cfg_interrupt_msix_vec_pending = 0;
|
|
|
|
assign cfg_interrupt_msi_function_number_msix = 0;
|
|
|
|
end
|
|
|
|
if (MSI_ENABLE) begin
|
|
|
|
pcie_us_msi #(
|
|
.MSI_COUNT(MSI_COUNT)
|
|
)
|
|
pcie_us_msi_inst (
|
|
.clk(clk),
|
|
.rst(rst),
|
|
|
|
/*
|
|
* Interrupt request inputs
|
|
*/
|
|
.msi_irq(msi_irq),
|
|
|
|
/*
|
|
* Interface to Ultrascale PCIe IP core
|
|
*/
|
|
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
|
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
|
|
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
|
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
|
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
|
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
|
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
|
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
|
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
|
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
|
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
|
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
|
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
|
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
|
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
|
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
|
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number_msi)
|
|
);
|
|
|
|
end else begin
|
|
|
|
assign cfg_interrupt_msi_select = 0;
|
|
assign cfg_interrupt_msi_int = 0;
|
|
assign cfg_interrupt_msi_pending_status = 0;
|
|
assign cfg_interrupt_msi_pending_status_data_enable = 0;
|
|
assign cfg_interrupt_msi_pending_status_function_num = 0;
|
|
assign cfg_interrupt_msi_attr = 0;
|
|
assign cfg_interrupt_msi_tph_present = 0;
|
|
assign cfg_interrupt_msi_tph_type = 0;
|
|
assign cfg_interrupt_msi_tph_st_tag = 0;
|
|
|
|
assign cfg_interrupt_msi_function_number_msi = 0;
|
|
|
|
end
|
|
|
|
endgenerate
|
|
|
|
endmodule
|
|
|
|
`resetall
|