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352 lines
13 KiB
Verilog
352 lines
13 KiB
Verilog
/*
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Copyright (c) 2022 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* P-Tile PCIe interface adapter (transmit)
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*/
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module pcie_ptile_if_tx #
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(
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// P-Tile AVST segment count
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parameter SEG_COUNT = 1,
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// P-Tile AVST segment data width
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parameter SEG_DATA_WIDTH = 128,
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// P-Tile AVST segment header width
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parameter SEG_HDR_WIDTH = 128,
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// P-Tile AVST segment TLP prefix width
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parameter SEG_PRFX_WIDTH = 32,
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// TLP data width
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parameter TLP_DATA_WIDTH = SEG_COUNT*SEG_DATA_WIDTH,
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// TLP strobe width
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parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32,
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// TLP header width
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parameter TLP_HDR_WIDTH = 128,
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// TLP segment count
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parameter TLP_SEG_COUNT = 1,
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// TX sequence number width
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parameter TX_SEQ_NUM_WIDTH = 6
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)
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(
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input wire clk,
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input wire rst,
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/*
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* P-Tile TX AVST interface
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*/
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output wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] tx_st_data,
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output wire [SEG_COUNT-1:0] tx_st_sop,
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output wire [SEG_COUNT-1:0] tx_st_eop,
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output wire [SEG_COUNT-1:0] tx_st_valid,
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input wire tx_st_ready,
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output wire [SEG_COUNT-1:0] tx_st_err,
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output wire [SEG_COUNT*SEG_HDR_WIDTH-1:0] tx_st_hdr,
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output wire [SEG_COUNT*SEG_PRFX_WIDTH-1:0] tx_st_tlp_prfx,
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/*
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* TLP input (read request from DMA)
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*/
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input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_rd_req_tlp_hdr,
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input wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] tx_rd_req_tlp_seq,
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input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_valid,
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input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_sop,
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input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_eop,
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output wire tx_rd_req_tlp_ready,
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/*
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* Transmit sequence number output (DMA read request)
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*/
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output wire [SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] m_axis_rd_req_tx_seq_num,
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output wire [SEG_COUNT-1:0] m_axis_rd_req_tx_seq_num_valid,
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/*
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* TLP input (write request from DMA)
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*/
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input wire [TLP_DATA_WIDTH-1:0] tx_wr_req_tlp_data,
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input wire [TLP_STRB_WIDTH-1:0] tx_wr_req_tlp_strb,
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input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_wr_req_tlp_hdr,
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input wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] tx_wr_req_tlp_seq,
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input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_valid,
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input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_sop,
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input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_eop,
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output wire tx_wr_req_tlp_ready,
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/*
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* Transmit sequence number output (DMA write request)
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*/
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output wire [SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] m_axis_wr_req_tx_seq_num,
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output wire [SEG_COUNT-1:0] m_axis_wr_req_tx_seq_num_valid,
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/*
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* TLP input (completion from BAR)
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*/
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input wire [TLP_DATA_WIDTH-1:0] tx_cpl_tlp_data,
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input wire [TLP_STRB_WIDTH-1:0] tx_cpl_tlp_strb,
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input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_cpl_tlp_hdr,
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input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_valid,
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input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_sop,
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input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_eop,
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output wire tx_cpl_tlp_ready,
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/*
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* TLP input (write request from MSI)
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*/
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input wire [31:0] tx_msi_wr_req_tlp_data,
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input wire tx_msi_wr_req_tlp_strb,
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input wire [TLP_HDR_WIDTH-1:0] tx_msi_wr_req_tlp_hdr,
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input wire tx_msi_wr_req_tlp_valid,
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input wire tx_msi_wr_req_tlp_sop,
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input wire tx_msi_wr_req_tlp_eop,
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output wire tx_msi_wr_req_tlp_ready
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);
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parameter SEG_STRB_WIDTH = SEG_DATA_WIDTH/32;
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parameter INT_TLP_SEG_COUNT = SEG_COUNT;
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parameter INT_TLP_SEG_DATA_WIDTH = TLP_DATA_WIDTH / INT_TLP_SEG_COUNT;
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parameter INT_TLP_SEG_STRB_WIDTH = TLP_STRB_WIDTH / INT_TLP_SEG_COUNT;
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parameter SEG_SEL_WIDTH = $clog2(INT_TLP_SEG_COUNT);
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parameter PORTS = 4;
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parameter CL_PORTS = $clog2(PORTS);
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// bus width assertions
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initial begin
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if (SEG_HDR_WIDTH != 128) begin
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$error("Error: segment header width must be 128 (instance %m)");
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$finish;
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end
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if (SEG_PRFX_WIDTH != 32) begin
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$error("Error: segment TLP prefix width must be 32 (instance %m)");
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$finish;
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end
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if (TLP_DATA_WIDTH != SEG_COUNT*SEG_DATA_WIDTH) begin
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$error("Error: Interface widths must match (instance %m)");
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$finish;
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end
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if (TLP_HDR_WIDTH != 128) begin
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$error("Error: TLP segment header width must be 128 (instance %m)");
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$finish;
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end
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end
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reg frame_reg = 1'b0, frame_next, frame_cyc;
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reg [SEG_SEL_WIDTH-1:0] seg_offset_cyc;
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reg [SEG_SEL_WIDTH+1-1:0] seg_count_cyc;
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reg valid, sop, eop;
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reg frame, abort;
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reg [INT_TLP_SEG_COUNT-1:0] port_seg_valid;
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reg [INT_TLP_SEG_COUNT-1:0] port_seg_sop;
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reg [INT_TLP_SEG_COUNT-1:0] port_seg_eop;
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reg [INT_TLP_SEG_COUNT-1:0] out_sel_reg = 0, out_sel_next, out_sel_cyc;
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reg [INT_TLP_SEG_COUNT-1:0] out_sop_reg = 0, out_sop_next;
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reg [INT_TLP_SEG_COUNT-1:0] out_eop_reg = 0, out_eop_next;
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reg [SEG_SEL_WIDTH+1-1:0] out_sel_seg_reg[0:INT_TLP_SEG_COUNT-1], out_sel_seg_next[0:INT_TLP_SEG_COUNT-1];
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reg [SEG_COUNT*SEG_DATA_WIDTH-1:0] tx_st_data_reg = 0, tx_st_data_next;
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reg [SEG_COUNT-1:0] tx_st_sop_reg = 0, tx_st_sop_next;
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reg [SEG_COUNT-1:0] tx_st_eop_reg = 0, tx_st_eop_next;
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reg [SEG_COUNT-1:0] tx_st_valid_reg = 0, tx_st_valid_next;
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reg [SEG_COUNT*SEG_HDR_WIDTH-1:0] tx_st_hdr_reg = 0, tx_st_hdr_next;
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reg [1:0] tx_st_ready_delay_reg = 0;
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wire [PORTS*TLP_DATA_WIDTH-1:0] mux_in_tlp_data;
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wire [PORTS*TLP_STRB_WIDTH-1:0] mux_in_tlp_strb;
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wire [PORTS*TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] mux_in_tlp_hdr;
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wire [PORTS*TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] mux_in_tlp_seq;
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wire [PORTS*TLP_SEG_COUNT-1:0] mux_in_tlp_valid;
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wire [PORTS*TLP_SEG_COUNT-1:0] mux_in_tlp_sop;
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wire [PORTS*TLP_SEG_COUNT-1:0] mux_in_tlp_eop;
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wire [PORTS-1:0] mux_in_tlp_ready;
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wire [TLP_DATA_WIDTH-1:0] mux_out_tlp_data;
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wire [TLP_STRB_WIDTH-1:0] mux_out_tlp_strb;
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wire [INT_TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] mux_out_tlp_hdr;
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wire [INT_TLP_SEG_COUNT-1:0] mux_out_tlp_valid;
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wire [INT_TLP_SEG_COUNT-1:0] mux_out_tlp_sop;
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wire [INT_TLP_SEG_COUNT-1:0] mux_out_tlp_eop;
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reg mux_out_tlp_ready_cmb;
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wire [PORTS*INT_TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] mux_out_sel_tlp_seq;
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wire [PORTS*INT_TLP_SEG_COUNT-1:0] mux_out_sel_tlp_seq_valid;
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assign mux_in_tlp_data[TLP_DATA_WIDTH*0 +: TLP_DATA_WIDTH] = tx_msi_wr_req_tlp_data;
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assign mux_in_tlp_strb[TLP_STRB_WIDTH*0 +: TLP_STRB_WIDTH] = tx_msi_wr_req_tlp_strb;
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assign mux_in_tlp_hdr[TLP_SEG_COUNT*TLP_HDR_WIDTH*0 +: TLP_SEG_COUNT*TLP_HDR_WIDTH] = tx_msi_wr_req_tlp_hdr;
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assign mux_in_tlp_seq[TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH*0 +: TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH] = 0;
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assign mux_in_tlp_valid[TLP_SEG_COUNT*0 +: TLP_SEG_COUNT] = tx_msi_wr_req_tlp_valid;
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assign mux_in_tlp_sop[TLP_SEG_COUNT*0 +: TLP_SEG_COUNT] = tx_msi_wr_req_tlp_sop;
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assign mux_in_tlp_eop[TLP_SEG_COUNT*0 +: TLP_SEG_COUNT] = tx_msi_wr_req_tlp_eop;
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assign tx_msi_wr_req_tlp_ready = mux_in_tlp_ready[0 +: 1];
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assign mux_in_tlp_data[TLP_DATA_WIDTH*1 +: TLP_DATA_WIDTH] = tx_cpl_tlp_data;
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assign mux_in_tlp_strb[TLP_STRB_WIDTH*1 +: TLP_STRB_WIDTH] = tx_cpl_tlp_strb;
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assign mux_in_tlp_hdr[TLP_SEG_COUNT*TLP_HDR_WIDTH*1 +: TLP_SEG_COUNT*TLP_HDR_WIDTH] = tx_cpl_tlp_hdr;
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assign mux_in_tlp_seq[TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH*1 +: TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH] = 0;
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assign mux_in_tlp_valid[TLP_SEG_COUNT*1 +: TLP_SEG_COUNT] = tx_cpl_tlp_valid;
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assign mux_in_tlp_sop[TLP_SEG_COUNT*1 +: TLP_SEG_COUNT] = tx_cpl_tlp_sop;
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assign mux_in_tlp_eop[TLP_SEG_COUNT*1 +: TLP_SEG_COUNT] = tx_cpl_tlp_eop;
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assign tx_cpl_tlp_ready = mux_in_tlp_ready[1 +: 1];
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assign mux_in_tlp_data[TLP_DATA_WIDTH*2 +: TLP_DATA_WIDTH] = 0;
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assign mux_in_tlp_strb[TLP_STRB_WIDTH*2 +: TLP_STRB_WIDTH] = 0;
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assign mux_in_tlp_hdr[TLP_SEG_COUNT*TLP_HDR_WIDTH*2 +: TLP_SEG_COUNT*TLP_HDR_WIDTH] = tx_rd_req_tlp_hdr;
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assign mux_in_tlp_seq[TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH*2 +: TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH] = tx_rd_req_tlp_seq;
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assign mux_in_tlp_valid[TLP_SEG_COUNT*2 +: TLP_SEG_COUNT] = tx_rd_req_tlp_valid;
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assign mux_in_tlp_sop[TLP_SEG_COUNT*2 +: TLP_SEG_COUNT] = {TLP_SEG_COUNT{1'b1}};
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assign mux_in_tlp_eop[TLP_SEG_COUNT*2 +: TLP_SEG_COUNT] = {TLP_SEG_COUNT{1'b1}};
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assign tx_rd_req_tlp_ready = mux_in_tlp_ready[2 +: 1];
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assign mux_in_tlp_data[TLP_DATA_WIDTH*3 +: TLP_DATA_WIDTH] = tx_wr_req_tlp_data;
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assign mux_in_tlp_strb[TLP_STRB_WIDTH*3 +: TLP_STRB_WIDTH] = tx_wr_req_tlp_strb;
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assign mux_in_tlp_hdr[TLP_SEG_COUNT*TLP_HDR_WIDTH*3 +: TLP_SEG_COUNT*TLP_HDR_WIDTH] = tx_wr_req_tlp_hdr;
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assign mux_in_tlp_seq[TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH*3 +: TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH] = tx_wr_req_tlp_seq;
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assign mux_in_tlp_valid[TLP_SEG_COUNT*3 +: TLP_SEG_COUNT] = tx_wr_req_tlp_valid;
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assign mux_in_tlp_sop[TLP_SEG_COUNT*3 +: TLP_SEG_COUNT] = tx_wr_req_tlp_sop;
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assign mux_in_tlp_eop[TLP_SEG_COUNT*3 +: TLP_SEG_COUNT] = tx_wr_req_tlp_eop;
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assign tx_wr_req_tlp_ready = mux_in_tlp_ready[3 +: 1];
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assign m_axis_rd_req_tx_seq_num = mux_out_sel_tlp_seq[INT_TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH*2 +: INT_TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH];
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assign m_axis_rd_req_tx_seq_num_valid = mux_out_sel_tlp_seq_valid[INT_TLP_SEG_COUNT*2 +: INT_TLP_SEG_COUNT];
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assign m_axis_wr_req_tx_seq_num = mux_out_sel_tlp_seq[INT_TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH*3 +: INT_TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH];
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assign m_axis_wr_req_tx_seq_num_valid = mux_out_sel_tlp_seq_valid[INT_TLP_SEG_COUNT*3 +: INT_TLP_SEG_COUNT];
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assign tx_st_data = tx_st_data_reg;
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assign tx_st_sop = tx_st_sop_reg;
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assign tx_st_eop = tx_st_eop_reg;
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assign tx_st_valid = tx_st_valid_reg;
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assign tx_st_err = 0;
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assign tx_st_hdr = tx_st_hdr_reg;
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assign tx_st_tlp_prfx = 0;
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pcie_tlp_fifo_mux #(
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.PORTS(PORTS),
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.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
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.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
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.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
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.SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
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.IN_TLP_SEG_COUNT(TLP_SEG_COUNT),
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.OUT_TLP_SEG_COUNT(INT_TLP_SEG_COUNT),
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.ARB_TYPE_ROUND_ROBIN(0),
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.ARB_LSB_HIGH_PRIORITY(1),
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.FIFO_DEPTH((1024/4)*2)
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)
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pcie_tlp_fifo_mux_inst (
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.clk(clk),
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.rst(rst),
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/*
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* TLP input
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*/
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.in_tlp_data(mux_in_tlp_data),
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.in_tlp_strb(mux_in_tlp_strb),
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.in_tlp_hdr(mux_in_tlp_hdr),
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.in_tlp_seq(mux_in_tlp_seq),
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.in_tlp_bar_id(0),
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.in_tlp_func_num(0),
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.in_tlp_error(0),
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.in_tlp_valid(mux_in_tlp_valid),
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.in_tlp_sop(mux_in_tlp_sop),
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.in_tlp_eop(mux_in_tlp_eop),
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.in_tlp_ready(mux_in_tlp_ready),
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/*
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* TLP output
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*/
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.out_tlp_data(mux_out_tlp_data),
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.out_tlp_strb(mux_out_tlp_strb),
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.out_tlp_hdr(mux_out_tlp_hdr),
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.out_tlp_seq(),
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.out_tlp_bar_id(),
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.out_tlp_func_num(),
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.out_tlp_error(),
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.out_tlp_valid(mux_out_tlp_valid),
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.out_tlp_sop(mux_out_tlp_sop),
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.out_tlp_eop(mux_out_tlp_eop),
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.out_tlp_ready(mux_out_tlp_ready_cmb),
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/*
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* Control
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*/
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.pause(0),
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/*
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* Status
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*/
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.sel_tlp_seq(mux_out_sel_tlp_seq),
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.sel_tlp_seq_valid(mux_out_sel_tlp_seq_valid),
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.fifo_half_full(),
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.fifo_watermark()
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);
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always @* begin
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mux_out_tlp_ready_cmb = 1'b0;
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tx_st_data_next = 0;
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tx_st_sop_next = 0;
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tx_st_eop_next = 0;
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tx_st_valid_next = 0;
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tx_st_hdr_next = 0;
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if (tx_st_ready_delay_reg[1]) begin
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mux_out_tlp_ready_cmb = 1'b1;
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tx_st_data_next = mux_out_tlp_data;
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tx_st_valid_next = mux_out_tlp_valid;
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tx_st_sop_next = mux_out_tlp_sop;
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tx_st_eop_next = mux_out_tlp_eop;
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tx_st_hdr_next = mux_out_tlp_hdr;
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end
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end
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always @(posedge clk) begin
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tx_st_data_reg <= tx_st_data_next;
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tx_st_sop_reg <= tx_st_sop_next;
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tx_st_eop_reg <= tx_st_eop_next;
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tx_st_valid_reg <= tx_st_valid_next;
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tx_st_hdr_reg <= tx_st_hdr_next;
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tx_st_ready_delay_reg <= {tx_st_ready_delay_reg, tx_st_ready};
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if (rst) begin
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tx_st_valid_reg <= 0;
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tx_st_ready_delay_reg <= 0;
|
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end
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end
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endmodule
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`resetall
|