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78 lines
2.0 KiB
Verilog
78 lines
2.0 KiB
Verilog
/*
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Copyright (c) 2016-2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Generic source synchronous SDR output
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*/
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module ssio_sdr_out #
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(
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// target ("SIM", "GENERIC", "XILINX", "ALTERA")
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parameter TARGET = "GENERIC",
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// IODDR style ("IODDR", "IODDR2")
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// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
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// Use IODDR2 for Spartan-6
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parameter IODDR_STYLE = "IODDR2",
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// Width of register in bits
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parameter WIDTH = 1
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)
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(
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input wire clk,
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input wire [WIDTH-1:0] input_d,
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output wire output_clk,
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output wire [WIDTH-1:0] output_q
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);
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oddr #(
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.TARGET(TARGET),
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.IODDR_STYLE(IODDR_STYLE),
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.WIDTH(1)
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)
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clk_oddr_inst (
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.clk(clk),
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.d1(1'b0),
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.d2(1'b1),
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.q(output_clk)
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);
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(* IOB = "TRUE" *)
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reg [WIDTH-1:0] output_q_reg = {WIDTH{1'b0}};
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assign output_q = output_q_reg;
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always @(posedge clk) begin
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output_q_reg <= input_d;
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end
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endmodule
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`resetall
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