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255 lines
7.5 KiB
Verilog
255 lines
7.5 KiB
Verilog
/*
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Copyright (c) 2014-2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* Testbench for ip_mux
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*/
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module test_ip_mux_64_4;
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// Parameters
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parameter S_COUNT = 4;
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parameter DATA_WIDTH = 64;
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parameter KEEP_ENABLE = (DATA_WIDTH>8);
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parameter KEEP_WIDTH = (DATA_WIDTH/8);
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parameter ID_ENABLE = 1;
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parameter ID_WIDTH = 8;
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parameter DEST_ENABLE = 1;
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parameter DEST_WIDTH = 8;
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parameter USER_ENABLE = 1;
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parameter USER_WIDTH = 1;
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// Inputs
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reg clk = 0;
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reg rst = 0;
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reg [7:0] current_test = 0;
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reg [S_COUNT-1:0] s_ip_hdr_valid = 0;
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reg [S_COUNT*48-1:0] s_eth_dest_mac = 0;
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reg [S_COUNT*48-1:0] s_eth_src_mac = 0;
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reg [S_COUNT*16-1:0] s_eth_type = 0;
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reg [S_COUNT*4-1:0] s_ip_version = 0;
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reg [S_COUNT*4-1:0] s_ip_ihl = 0;
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reg [S_COUNT*6-1:0] s_ip_dscp = 0;
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reg [S_COUNT*2-1:0] s_ip_ecn = 0;
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reg [S_COUNT*16-1:0] s_ip_length = 0;
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reg [S_COUNT*16-1:0] s_ip_identification = 0;
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reg [S_COUNT*3-1:0] s_ip_flags = 0;
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reg [S_COUNT*13-1:0] s_ip_fragment_offset = 0;
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reg [S_COUNT*8-1:0] s_ip_ttl = 0;
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reg [S_COUNT*8-1:0] s_ip_protocol = 0;
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reg [S_COUNT*16-1:0] s_ip_header_checksum = 0;
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reg [S_COUNT*32-1:0] s_ip_source_ip = 0;
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reg [S_COUNT*32-1:0] s_ip_dest_ip = 0;
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reg [S_COUNT*DATA_WIDTH-1:0] s_ip_payload_axis_tdata = 0;
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reg [S_COUNT*KEEP_WIDTH-1:0] s_ip_payload_axis_tkeep = 0;
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reg [S_COUNT-1:0] s_ip_payload_axis_tvalid = 0;
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reg [S_COUNT-1:0] s_ip_payload_axis_tlast = 0;
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reg [S_COUNT*ID_WIDTH-1:0] s_ip_payload_axis_tid = 0;
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reg [S_COUNT*DEST_WIDTH-1:0] s_ip_payload_axis_tdest = 0;
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reg [S_COUNT*USER_WIDTH-1:0] s_ip_payload_axis_tuser = 0;
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reg m_ip_hdr_ready = 0;
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reg m_ip_payload_axis_tready = 0;
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reg enable = 0;
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reg [1:0] select = 0;
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// Outputs
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wire [S_COUNT-1:0] s_ip_hdr_ready;
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wire [S_COUNT-1:0] s_ip_payload_axis_tready;
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wire m_ip_hdr_valid;
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wire [47:0] m_eth_dest_mac;
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wire [47:0] m_eth_src_mac;
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wire [15:0] m_eth_type;
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wire [3:0] m_ip_version;
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wire [3:0] m_ip_ihl;
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wire [5:0] m_ip_dscp;
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wire [1:0] m_ip_ecn;
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wire [15:0] m_ip_length;
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wire [15:0] m_ip_identification;
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wire [2:0] m_ip_flags;
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wire [12:0] m_ip_fragment_offset;
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wire [7:0] m_ip_ttl;
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wire [7:0] m_ip_protocol;
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wire [15:0] m_ip_header_checksum;
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wire [31:0] m_ip_source_ip;
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wire [31:0] m_ip_dest_ip;
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wire [DATA_WIDTH-1:0] m_ip_payload_axis_tdata;
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wire [KEEP_WIDTH-1:0] m_ip_payload_axis_tkeep;
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wire m_ip_payload_axis_tvalid;
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wire m_ip_payload_axis_tlast;
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wire [ID_WIDTH-1:0] m_ip_payload_axis_tid;
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wire [DEST_WIDTH-1:0] m_ip_payload_axis_tdest;
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wire [USER_WIDTH-1:0] m_ip_payload_axis_tuser;
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initial begin
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// myhdl integration
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$from_myhdl(
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clk,
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rst,
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current_test,
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s_ip_hdr_valid,
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s_eth_dest_mac,
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s_eth_src_mac,
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s_eth_type,
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s_ip_version,
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s_ip_ihl,
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s_ip_dscp,
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s_ip_ecn,
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s_ip_length,
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s_ip_identification,
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s_ip_flags,
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s_ip_fragment_offset,
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s_ip_ttl,
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s_ip_protocol,
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s_ip_header_checksum,
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s_ip_source_ip,
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s_ip_dest_ip,
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s_ip_payload_axis_tdata,
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s_ip_payload_axis_tkeep,
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s_ip_payload_axis_tvalid,
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s_ip_payload_axis_tlast,
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s_ip_payload_axis_tid,
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s_ip_payload_axis_tdest,
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s_ip_payload_axis_tuser,
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m_ip_hdr_ready,
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m_ip_payload_axis_tready,
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enable,
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select
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);
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$to_myhdl(
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s_ip_hdr_ready,
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s_ip_payload_axis_tready,
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m_ip_hdr_valid,
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m_eth_dest_mac,
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m_eth_src_mac,
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m_eth_type,
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m_ip_version,
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m_ip_ihl,
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m_ip_dscp,
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m_ip_ecn,
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m_ip_length,
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m_ip_identification,
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m_ip_flags,
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m_ip_fragment_offset,
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m_ip_ttl,
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m_ip_protocol,
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m_ip_header_checksum,
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m_ip_source_ip,
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m_ip_dest_ip,
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m_ip_payload_axis_tdata,
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m_ip_payload_axis_tkeep,
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m_ip_payload_axis_tvalid,
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m_ip_payload_axis_tlast,
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m_ip_payload_axis_tid,
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m_ip_payload_axis_tdest,
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m_ip_payload_axis_tuser
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);
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// dump file
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$dumpfile("test_ip_mux_64_4.lxt");
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$dumpvars(0, test_ip_mux_64_4);
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end
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ip_mux #(
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.S_COUNT(S_COUNT),
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.DATA_WIDTH(DATA_WIDTH),
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.KEEP_ENABLE(KEEP_ENABLE),
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.KEEP_WIDTH(KEEP_WIDTH),
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.ID_ENABLE(ID_ENABLE),
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.ID_WIDTH(ID_WIDTH),
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.DEST_ENABLE(DEST_ENABLE),
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.DEST_WIDTH(DEST_WIDTH),
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.USER_ENABLE(USER_ENABLE),
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.USER_WIDTH(USER_WIDTH)
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)
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UUT (
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.clk(clk),
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.rst(rst),
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// IP frame inputs
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.s_ip_hdr_valid(s_ip_hdr_valid),
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.s_ip_hdr_ready(s_ip_hdr_ready),
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.s_eth_dest_mac(s_eth_dest_mac),
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.s_eth_src_mac(s_eth_src_mac),
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.s_eth_type(s_eth_type),
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.s_ip_version(s_ip_version),
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.s_ip_ihl(s_ip_ihl),
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.s_ip_dscp(s_ip_dscp),
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.s_ip_ecn(s_ip_ecn),
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.s_ip_length(s_ip_length),
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.s_ip_identification(s_ip_identification),
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.s_ip_flags(s_ip_flags),
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.s_ip_fragment_offset(s_ip_fragment_offset),
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.s_ip_ttl(s_ip_ttl),
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.s_ip_protocol(s_ip_protocol),
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.s_ip_header_checksum(s_ip_header_checksum),
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.s_ip_source_ip(s_ip_source_ip),
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.s_ip_dest_ip(s_ip_dest_ip),
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.s_ip_payload_axis_tdata(s_ip_payload_axis_tdata),
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.s_ip_payload_axis_tkeep(s_ip_payload_axis_tkeep),
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.s_ip_payload_axis_tvalid(s_ip_payload_axis_tvalid),
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.s_ip_payload_axis_tready(s_ip_payload_axis_tready),
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.s_ip_payload_axis_tlast(s_ip_payload_axis_tlast),
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.s_ip_payload_axis_tid(s_ip_payload_axis_tid),
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.s_ip_payload_axis_tdest(s_ip_payload_axis_tdest),
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.s_ip_payload_axis_tuser(s_ip_payload_axis_tuser),
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// IP frame output
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.m_ip_hdr_valid(m_ip_hdr_valid),
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.m_ip_hdr_ready(m_ip_hdr_ready),
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.m_eth_dest_mac(m_eth_dest_mac),
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.m_eth_src_mac(m_eth_src_mac),
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.m_eth_type(m_eth_type),
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.m_ip_version(m_ip_version),
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.m_ip_ihl(m_ip_ihl),
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.m_ip_dscp(m_ip_dscp),
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.m_ip_ecn(m_ip_ecn),
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.m_ip_length(m_ip_length),
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.m_ip_identification(m_ip_identification),
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.m_ip_flags(m_ip_flags),
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.m_ip_fragment_offset(m_ip_fragment_offset),
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.m_ip_ttl(m_ip_ttl),
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.m_ip_protocol(m_ip_protocol),
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.m_ip_header_checksum(m_ip_header_checksum),
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.m_ip_source_ip(m_ip_source_ip),
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.m_ip_dest_ip(m_ip_dest_ip),
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.m_ip_payload_axis_tdata(m_ip_payload_axis_tdata),
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.m_ip_payload_axis_tkeep(m_ip_payload_axis_tkeep),
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.m_ip_payload_axis_tvalid(m_ip_payload_axis_tvalid),
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.m_ip_payload_axis_tready(m_ip_payload_axis_tready),
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.m_ip_payload_axis_tlast(m_ip_payload_axis_tlast),
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.m_ip_payload_axis_tid(m_ip_payload_axis_tid),
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.m_ip_payload_axis_tdest(m_ip_payload_axis_tdest),
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.m_ip_payload_axis_tuser(m_ip_payload_axis_tuser),
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// Control
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.enable(enable),
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.select(select)
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);
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endmodule
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