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corundum/fpga/mqnic/ZCU106/fpga_zynqmp
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Joachim Foerster 5700aba9a0 ZCU106/fpga_zynqmp/ps/petalinux/: dts: Add custom device tree node for mqnic device 
Currently consists of 4 parts:
- Removing stub nodes generated by Xilinx device tree generator.
- Adding a custom, manually edited node (needs manual adjustment in case PS
  settings are changed!)
  NOTE: In the future this node might be reduced or removed all together after
  having added a plugin for Xilinx' device tree generator
  (https://github.com/Xilinx/device-tree-xlnx.git), which properly automatically
  generates such a node.
- Adding eeprom nodes for the SFP module I2C buses.
- Disabling the node for the USER MGT SI570 (U56) chip to make Linux NOT touch
  this chip on startup. See lengthy comment.

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Signed-off-by: Andreas Braun <andreas.braun@missinglinkelectronics.com>
2022-04-07 18:41:05 +02:00
..
common
ZCU106/: Add design based on ZynqMP PS as host system, Vivado v2021.1
2022-03-31 17:22:27 +02:00
fpga
ZCU106/fpga_zynqmp: Fix maximum burst length for AXI Master
2022-03-31 17:24:16 +02:00
ip
ZCU106/fpga_zynqmp: Reduce number of IRQs to number of CPU cores
2022-03-31 17:22:27 +02:00
ps/petalinux
ZCU106/fpga_zynqmp/ps/petalinux/: dts: Add custom device tree node for mqnic device
2022-04-07 18:41:05 +02:00
rtl
ZCU106/fpga_zynqmp: Support parameter EVENT_QUEUE_INDEX_WIDTH, reduce Events queues to number of CPU cores
2022-03-31 17:24:16 +02:00
app
ZCU106/: Add design based on ZynqMP PS as host system, Vivado v2021.1
2022-03-31 17:22:27 +02:00
fpga.xdc
ZCU106/: Add design based on ZynqMP PS as host system, Vivado v2021.1
2022-03-31 17:22:27 +02:00
lib
ZCU106/: Add design based on ZynqMP PS as host system, Vivado v2021.1
2022-03-31 17:22:27 +02:00
Makefile
ZCU106/: Add design based on ZynqMP PS as host system, Vivado v2021.1
2022-03-31 17:22:27 +02:00
README.md
ZCU106/: Add design based on ZynqMP PS as host system, Vivado v2021.1
2022-03-31 17:22:27 +02:00

README.md

Corundum mqnic for ZCU106 using ZynqMP PS as host system

Introduction

This design targets the Xilinx ZCU106 FPGA board. The host system of the NIC is the Zynq US+ MPSoC.

FPGA: xczu7ev-ffvc1156-2-e PHY: 10G BASE-R PHY IP core and internal GTH transceiver

How to build

Run make to build. Ensure that the Xilinx Vivado toolchain components are in PATH.