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corundum/fpga/common
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Alex Forencich 95af2136b1 fpga/common: Increase event FIFO size 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-04-14 01:03:19 -07:00
..
rtl
fpga/common: Increase event FIFO size
2023-04-14 01:03:19 -07:00
syn/vivado
fpga/common: Update port timing constraints to not mark ASYNC_REG on the first flip flop in the status sync chains for better placement flexibility
2023-04-06 14:34:22 -07:00
tb
Add RX indirection table
2023-04-10 15:05:32 -07:00
lib
Add symlink
2019-08-11 00:33:22 -07:00