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120 lines
3.1 KiB
Verilog
120 lines
3.1 KiB
Verilog
/*
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Copyright (c) 2016-2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* Generic source synchronous DDR input
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*/
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module ssio_ddr_in_diff #
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(
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// target ("SIM", "GENERIC", "XILINX", "ALTERA")
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parameter TARGET = "GENERIC",
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// IODDR style ("IODDR", "IODDR2")
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// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
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// Use IODDR2 for Spartan-6
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parameter IODDR_STYLE = "IODDR2",
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// Clock input style ("BUFG", "BUFR", "BUFIO", "BUFIO2")
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// Use BUFR for Virtex-5, Virtex-6, 7-series
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// Use BUFG for Ultrascale
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// Use BUFIO2 for Spartan-6
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parameter CLOCK_INPUT_STYLE = "BUFIO2",
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// Width of register in bits
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parameter WIDTH = 1
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)
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(
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input wire input_clk_p,
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input wire input_clk_n,
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input wire [WIDTH-1:0] input_d_p,
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input wire [WIDTH-1:0] input_d_n,
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output wire output_clk,
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output wire [WIDTH-1:0] output_q1,
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output wire [WIDTH-1:0] output_q2
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);
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wire input_clk;
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wire [WIDTH-1:0] input_d;
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genvar n;
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generate
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if (TARGET == "XILINX") begin
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IBUFDS
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clk_ibufds_inst (
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.I(input_clk_p),
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.IB(input_clk_n),
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.O(input_clk)
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);
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for (n = 0; n < WIDTH; n = n + 1) begin
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IBUFDS
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data_ibufds_inst (
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.I(input_d_p[n]),
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.IB(input_d_n[n]),
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.O(input_d[n])
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);
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end
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end else if (TARGET == "ALTERA") begin
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ALT_INBUF_DIFF
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clk_inbuf_diff_inst (
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.i(input_clk_p),
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.ibar(input_clk_n),
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.o(input_clk)
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);
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for (n = 0; n < WIDTH; n = n + 1) begin
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ALT_INBUF_DIFF
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data_inbuf_diff_inst (
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.i(input_d_p[n]),
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.ibar(input_d_n[n]),
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.o(input_d[n])
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);
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end
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end else begin
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assign input_clk = input_clk_p;
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assign input_d = input_d_p;
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end
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endgenerate
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ssio_ddr_in #(
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.TARGET(TARGET),
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.IODDR_STYLE(IODDR_STYLE),
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.CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE),
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.WIDTH(WIDTH)
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)
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ssio_ddr_in_inst(
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.input_clk(input_clk),
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.input_d(input_d),
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.output_clk(output_clk),
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.output_q1(output_q1),
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.output_q2(output_q2)
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);
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endmodule
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