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https://github.com/corundum/corundum.git
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535 lines
15 KiB
Python
Executable File
535 lines
15 KiB
Python
Executable File
#!/usr/bin/env python
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"""
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Copyright (c) 2014-2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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"""
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from myhdl import *
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import os
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import axis_ep
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module = 'arp_cache'
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testbench = 'test_%s' % module
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srcs = []
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srcs.append("../rtl/%s.v" % module)
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srcs.append("../rtl/lfsr.v")
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srcs.append("%s.v" % testbench)
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src = ' '.join(srcs)
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build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
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def bench():
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# Inputs
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clk = Signal(bool(0))
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rst = Signal(bool(0))
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current_test = Signal(intbv(0)[8:])
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query_request_valid = Signal(bool(0))
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query_request_ip = Signal(intbv(0)[32:])
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query_response_ready = Signal(bool(0))
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write_request_valid = Signal(bool(0))
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write_request_ip = Signal(intbv(0)[32:])
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write_request_mac = Signal(intbv(0)[48:])
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clear_cache = Signal(bool(0))
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# Outputs
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query_request_ready = Signal(bool(0))
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query_response_valid = Signal(bool(0))
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query_response_error = Signal(bool(0))
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query_response_mac = Signal(intbv(0)[48:])
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write_request_ready = Signal(bool(0))
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# sources and sinks
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query_request_source_pause = Signal(bool(0))
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query_response_sink_pause = Signal(bool(0))
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write_request_source_pause = Signal(bool(0))
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query_request_source = axis_ep.AXIStreamSource()
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query_request_source_logic = query_request_source.create_logic(
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clk,
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rst,
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tdata=(query_request_ip,),
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tvalid=query_request_valid,
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tready=query_request_ready,
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pause=query_request_source_pause,
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name='query_request_source'
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)
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query_response_sink = axis_ep.AXIStreamSink()
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query_response_sink_logic = query_response_sink.create_logic(
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clk,
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rst,
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tdata=(query_response_mac,),
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tvalid=query_response_valid,
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tready=query_response_ready,
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tuser=query_response_error,
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pause=query_response_sink_pause,
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name='query_response_sink'
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)
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write_request_source = axis_ep.AXIStreamSource()
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write_request_source_logic = write_request_source.create_logic(
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clk,
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rst,
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tdata=(write_request_ip, write_request_mac),
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tvalid=write_request_valid,
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tready=write_request_ready,
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pause=write_request_source_pause,
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name='write_request_source'
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)
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# DUT
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if os.system(build_cmd):
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raise Exception("Error running build command")
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dut = Cosimulation(
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"vvp -m myhdl %s.vvp -lxt2" % testbench,
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clk=clk,
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rst=rst,
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current_test=current_test,
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query_request_valid=query_request_valid,
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query_request_ready=query_request_ready,
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query_request_ip=query_request_ip,
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query_response_valid=query_response_valid,
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query_response_ready=query_response_ready,
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query_response_error=query_response_error,
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query_response_mac=query_response_mac,
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write_request_valid=write_request_valid,
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write_request_ready=write_request_ready,
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write_request_ip=write_request_ip,
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write_request_mac=write_request_mac,
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clear_cache=clear_cache
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)
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@always(delay(4))
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def clkgen():
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clk.next = not clk
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@instance
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def check():
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yield delay(100)
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yield clk.posedge
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rst.next = 1
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yield clk.posedge
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rst.next = 0
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yield clk.posedge
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yield delay(100)
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yield clk.posedge
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yield clk.posedge
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print("test 1: write")
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current_test.next = 1
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yield clk.posedge
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write_request_source.send([(0xc0a80111, 0x0000c0a80111)])
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write_request_source.send([(0xc0a80112, 0x0000c0a80112)])
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yield delay(100)
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while not write_request_source.empty():
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yield clk.posedge
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yield delay(100)
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yield clk.posedge
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print("test 2: read")
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current_test.next = 2
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yield clk.posedge
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query_request_source.send([(0xc0a80111, )])
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query_request_source.send([(0xc0a80112, )])
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query_request_source.send([(0xc0a80113, )])
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while query_response_sink.empty():
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yield clk.posedge
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resp = query_response_sink.recv()
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assert resp.data[0][0] == 0x0000c0a80111
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assert not resp.user[0]
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while query_response_sink.empty():
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yield clk.posedge
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resp = query_response_sink.recv()
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assert resp.data[0][0] == 0x0000c0a80112
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assert not resp.user[0]
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# not in cache; was not written
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while query_response_sink.empty():
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yield clk.posedge
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resp = query_response_sink.recv()
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assert resp.user[0]
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yield delay(100)
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raise StopSimulation
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yield clk.posedge
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print("test 3: write more")
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current_test.next = 3
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yield clk.posedge
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write_request_source.send([(0xc0a80121, 0x0000c0a80121)])
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write_request_source.send([(0xc0a80122, 0x0000c0a80122)])
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# overwrites 0xc0a80121 due to LRU
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write_request_source.send([(0xc0a80123, 0x0000c0a80123)])
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while not write_request_source.empty():
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yield clk.posedge
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yield delay(100)
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yield clk.posedge
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print("test 4: read more")
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current_test.next = 4
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yield clk.posedge
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query_request_source.send([(0xc0a80111, )])
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while query_response_sink.empty():
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yield clk.posedge
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resp = query_response_sink.recv()
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assert resp.data[0][0] == 0x0000c0a80111
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assert not resp.user[0]
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yield clk.posedge
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query_request_source.send([(0xc0a80112, )])
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while query_response_sink.empty():
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yield clk.posedge
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resp = query_response_sink.recv()
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assert resp.data[0][0] == 0x0000c0a80112
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assert not resp.user[0]
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# not in cache; was overwritten
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yield clk.posedge
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query_request_source.send([(0xc0a80121, )])
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while query_response_sink.empty():
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yield clk.posedge
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resp = query_response_sink.recv()
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assert resp.user[0]
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yield clk.posedge
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query_request_source.send([(0xc0a80122, )])
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while query_response_sink.empty():
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yield clk.posedge
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resp = query_response_sink.recv()
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assert resp.data[0][0] == 0x0000c0a80122
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assert not resp.user[0]
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yield clk.posedge
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query_request_source.send([(0xc0a80123, )])
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while query_response_sink.empty():
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yield clk.posedge
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resp = query_response_sink.recv()
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assert resp.data[0][0] == 0x0000c0a80123
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assert not resp.user[0]
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# LRU reset by previous operation
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yield delay(100)
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raise StopSimulation
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yield clk.posedge
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print("test 5: LRU test")
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current_test.next = 5
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# read to set LRU bit
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yield clk.posedge
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query_request_valid.next = True
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query_request_ip.next = 0xc0a80111
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yield clk.posedge
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query_request_valid.next = False
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yield query_response_valid.posedge
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assert not bool(query_response_error)
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assert int(query_response_mac) == 0x0000c0a80111
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yield clk.posedge
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write_request_valid.next = True
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write_request_ip.next = 0xc0a80131
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write_request_mac.next = 0x0000c0a80131
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yield clk.posedge
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write_request_valid.next = False
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yield write_complete.posedge
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yield clk.posedge
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yield clk.posedge
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write_request_valid.next = True
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write_request_ip.next = 0xc0a80132
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write_request_mac.next = 0x0000c0a80132
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yield clk.posedge
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write_request_valid.next = False
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yield write_complete.posedge
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yield clk.posedge
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yield clk.posedge
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write_request_valid.next = True
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write_request_ip.next = 0xc0a80133
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write_request_mac.next = 0x0000c0a80133
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yield clk.posedge
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write_request_valid.next = False
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yield write_complete.posedge
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yield clk.posedge
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# read values
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yield clk.posedge
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query_request_valid.next = True
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query_request_ip.next = 0xc0a80111
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yield clk.posedge
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query_request_valid.next = False
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yield query_response_valid.posedge
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assert not bool(query_response_error)
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assert int(query_response_mac) == 0x0000c0a80111
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yield clk.posedge
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query_request_valid.next = True
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query_request_ip.next = 0xc0a80112
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yield clk.posedge
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query_request_valid.next = False
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yield query_response_valid.posedge
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assert bool(query_response_error)
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yield clk.posedge
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query_request_valid.next = True
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query_request_ip.next = 0xc0a80121
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yield clk.posedge
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query_request_valid.next = False
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yield query_response_valid.posedge
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assert bool(query_response_error)
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yield clk.posedge
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query_request_valid.next = True
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query_request_ip.next = 0xc0a80122
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yield clk.posedge
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query_request_valid.next = False
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yield query_response_valid.posedge
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assert bool(query_response_error)
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yield clk.posedge
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query_request_valid.next = True
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query_request_ip.next = 0xc0a80123
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yield clk.posedge
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query_request_valid.next = False
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yield query_response_valid.posedge
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assert bool(query_response_error)
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yield clk.posedge
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query_request_valid.next = True
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query_request_ip.next = 0xc0a80131
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yield clk.posedge
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query_request_valid.next = False
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yield query_response_valid.posedge
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assert not bool(query_response_error)
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assert int(query_response_mac) == 0x0000c0a80131
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yield clk.posedge
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query_request_valid.next = True
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query_request_ip.next = 0xc0a80132
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yield clk.posedge
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query_request_valid.next = False
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yield query_response_valid.posedge
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assert not bool(query_response_error)
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assert int(query_response_mac) == 0x0000c0a80132
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yield clk.posedge
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query_request_valid.next = True
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query_request_ip.next = 0xc0a80133
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yield clk.posedge
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query_request_valid.next = False
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yield query_response_valid.posedge
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assert not bool(query_response_error)
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assert int(query_response_mac) == 0x0000c0a80133
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# LRU reset by previous operation
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yield delay(100)
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yield clk.posedge
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print("test 6: Test overwrite")
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current_test.next = 6
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yield clk.posedge
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write_request_valid.next = True
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write_request_ip.next = 0xc0a80133
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write_request_mac.next = 0x0000c0a80164
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yield clk.posedge
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write_request_valid.next = False
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yield write_complete.posedge
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yield clk.posedge
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# read values
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yield clk.posedge
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query_request_valid.next = True
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query_request_ip.next = 0xc0a80111
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yield clk.posedge
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query_request_valid.next = False
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yield query_response_valid.posedge
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assert not bool(query_response_error)
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assert int(query_response_mac) == 0x0000c0a80111
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yield clk.posedge
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query_request_valid.next = True
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query_request_ip.next = 0xc0a80112
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yield clk.posedge
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query_request_valid.next = False
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yield query_response_valid.posedge
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assert bool(query_response_error)
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yield clk.posedge
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query_request_valid.next = True
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query_request_ip.next = 0xc0a80121
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yield clk.posedge
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query_request_valid.next = False
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yield query_response_valid.posedge
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assert bool(query_response_error)
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yield clk.posedge
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query_request_valid.next = True
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query_request_ip.next = 0xc0a80122
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yield clk.posedge
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query_request_valid.next = False
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yield query_response_valid.posedge
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assert bool(query_response_error)
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yield clk.posedge
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query_request_valid.next = True
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query_request_ip.next = 0xc0a80123
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yield clk.posedge
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query_request_valid.next = False
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yield query_response_valid.posedge
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assert bool(query_response_error)
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yield clk.posedge
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query_request_valid.next = True
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query_request_ip.next = 0xc0a80131
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yield clk.posedge
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query_request_valid.next = False
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yield query_response_valid.posedge
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assert not bool(query_response_error)
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assert int(query_response_mac) == 0x0000c0a80131
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yield clk.posedge
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query_request_valid.next = True
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query_request_ip.next = 0xc0a80132
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yield clk.posedge
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query_request_valid.next = False
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yield query_response_valid.posedge
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assert not bool(query_response_error)
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assert int(query_response_mac) == 0x0000c0a80132
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yield clk.posedge
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query_request_valid.next = True
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query_request_ip.next = 0xc0a80133
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yield clk.posedge
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query_request_valid.next = False
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yield query_response_valid.posedge
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assert not bool(query_response_error)
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assert int(query_response_mac) == 0x0000c0a80164
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# LRU reset by previous operation
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yield delay(100)
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yield clk.posedge
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print("test 7: clear cache")
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current_test.next = 7
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yield clk.posedge
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clear_cache.next = True
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yield clk.posedge
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clear_cache.next = False
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yield delay(100)
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yield clk.posedge
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query_request_valid.next = True
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query_request_ip.next = 0xc0a80111
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yield clk.posedge
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query_request_valid.next = False
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yield query_response_valid.posedge
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assert bool(query_response_error)
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yield delay(100)
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raise StopSimulation
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return instances()
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def test_bench():
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os.chdir(os.path.dirname(os.path.abspath(__file__)))
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sim = Simulation(bench())
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sim.run()
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if __name__ == '__main__':
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print("Running test...")
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test_bench()
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