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2087 lines
112 KiB
C
2087 lines
112 KiB
C
/*
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Copyright 2022, The Regents of the University of California.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
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IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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The views and conclusions contained in the software and documentation are those
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of the authors and should not be interpreted as representing official policies,
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either expressed or implied, of The Regents of the University of California.
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*/
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#ifndef GTHE3_REGS_H
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#define GTHE3_REGS_H
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#include <limits.h>
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#ifndef BIT_MASK
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#define BIT_MASK(h, l) \
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((~0UL << ((l) & (sizeof(1UL)*CHAR_BIT-1))) & \
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(~0UL >> (((-(h)-1) & (sizeof(1UL)*CHAR_BIT-1)))))
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#endif
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// common registers
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#define GTHE3_COM_QPLL0_CFG0_ADDR 0x0008
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#define GTHE3_COM_QPLL0_CFG0_MSB 15
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#define GTHE3_COM_QPLL0_CFG0_LSB 0
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#define GTHE3_COM_QPLL0_CFG0_MASK BIT_MASK(GTHE3_COM_QPLL0_CFG0_MSB, GTHE3_COM_QPLL0_CFG0_LSB)
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#define GTHE3_COM_COMMON_CFG0_ADDR 0x0009
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#define GTHE3_COM_COMMON_CFG0_MSB 15
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#define GTHE3_COM_COMMON_CFG0_LSB 0
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#define GTHE3_COM_COMMON_CFG0_MASK BIT_MASK(GTHE3_COM_COMMON_CFG0_MSB, GTHE3_COM_COMMON_CFG0_LSB)
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#define GTHE3_COM_RSVD_ATTR0_ADDR 0x000B
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#define GTHE3_COM_RSVD_ATTR0_MSB 15
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#define GTHE3_COM_RSVD_ATTR0_LSB 0
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#define GTHE3_COM_RSVD_ATTR0_MASK BIT_MASK(GTHE3_COM_RSVD_ATTR0_MSB, GTHE3_COM_RSVD_ATTR0_LSB)
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#define GTHE3_COM_QPLL0_CFG1_ADDR 0x0010
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#define GTHE3_COM_QPLL0_CFG1_MSB 15
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#define GTHE3_COM_QPLL0_CFG1_LSB 0
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#define GTHE3_COM_QPLL0_CFG1_MASK BIT_MASK(GTHE3_COM_QPLL0_CFG1_MSB, GTHE3_COM_QPLL0_CFG1_LSB)
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#define GTHE3_COM_QPLL0_CFG2_ADDR 0x0011
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#define GTHE3_COM_QPLL0_CFG2_MSB 15
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#define GTHE3_COM_QPLL0_CFG2_LSB 0
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#define GTHE3_COM_QPLL0_CFG2_MASK BIT_MASK(GTHE3_COM_QPLL0_CFG2_MSB, GTHE3_COM_QPLL0_CFG2_LSB)
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#define GTHE3_COM_QPLL0_LOCK_CFG_ADDR 0x0012
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#define GTHE3_COM_QPLL0_LOCK_CFG_MSB 15
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#define GTHE3_COM_QPLL0_LOCK_CFG_LSB 0
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#define GTHE3_COM_QPLL0_LOCK_CFG_MASK BIT_MASK(GTHE3_COM_QPLL0_LOCK_CFG_MSB, GTHE3_COM_QPLL0_LOCK_CFG_LSB)
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#define GTHE3_COM_QPLL0_INIT_CFG0_ADDR 0x0013
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#define GTHE3_COM_QPLL0_INIT_CFG0_MSB 15
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#define GTHE3_COM_QPLL0_INIT_CFG0_LSB 0
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#define GTHE3_COM_QPLL0_INIT_CFG0_MASK BIT_MASK(GTHE3_COM_QPLL0_INIT_CFG0_MSB, GTHE3_COM_QPLL0_INIT_CFG0_LSB)
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#define GTHE3_COM_QPLL0_INIT_CFG1_ADDR 0x0014
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#define GTHE3_COM_QPLL0_INIT_CFG1_MSB 15
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#define GTHE3_COM_QPLL0_INIT_CFG1_LSB 8
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#define GTHE3_COM_QPLL0_INIT_CFG1_MASK BIT_MASK(GTHE3_COM_QPLL0_INIT_CFG1_MSB, GTHE3_COM_QPLL0_INIT_CFG1_LSB)
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#define GTHE3_COM_QPLL0_FBDIV_ADDR 0x0014
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#define GTHE3_COM_QPLL0_FBDIV_MSB 7
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#define GTHE3_COM_QPLL0_FBDIV_LSB 0
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#define GTHE3_COM_QPLL0_FBDIV_MASK BIT_MASK(GTHE3_COM_QPLL0_FBDIV_MSB, GTHE3_COM_QPLL0_FBDIV_LSB)
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#define GTHE3_COM_QPLL0_CFG3_ADDR 0x0015
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#define GTHE3_COM_QPLL0_CFG3_MSB 15
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#define GTHE3_COM_QPLL0_CFG3_LSB 0
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#define GTHE3_COM_QPLL0_CFG3_MASK BIT_MASK(GTHE3_COM_QPLL0_CFG3_MSB, GTHE3_COM_QPLL0_CFG3_LSB)
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#define GTHE3_COM_QPLL0_CP_ADDR 0x0016
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#define GTHE3_COM_QPLL0_CP_MSB 9
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#define GTHE3_COM_QPLL0_CP_LSB 0
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#define GTHE3_COM_QPLL0_CP_MASK BIT_MASK(GTHE3_COM_QPLL0_CP_MSB, GTHE3_COM_QPLL0_CP_LSB)
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#define GTHE3_COM_QPLL0_REFCLK_DIV_ADDR 0x0018
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#define GTHE3_COM_QPLL0_REFCLK_DIV_MSB 11
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#define GTHE3_COM_QPLL0_REFCLK_DIV_LSB 7
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#define GTHE3_COM_QPLL0_REFCLK_DIV_MASK BIT_MASK(GTHE3_COM_QPLL0_REFCLK_DIV_MSB, GTHE3_COM_QPLL0_REFCLK_DIV_LSB)
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#define GTHE3_COM_QPLL0_REFCLK_DIV_1 16
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#define GTHE3_COM_QPLL0_REFCLK_DIV_2 0
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#define GTHE3_COM_QPLL0_REFCLK_DIV_3 1
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#define GTHE3_COM_QPLL0_REFCLK_DIV_4 2
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#define GTHE3_COM_QPLL0_REFCLK_DIV_5 3
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#define GTHE3_COM_QPLL0_REFCLK_DIV_6 5
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#define GTHE3_COM_QPLL0_REFCLK_DIV_8 6
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#define GTHE3_COM_QPLL0_REFCLK_DIV_10 7
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#define GTHE3_COM_QPLL0_REFCLK_DIV_12 13
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#define GTHE3_COM_QPLL0_REFCLK_DIV_16 14
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#define GTHE3_COM_QPLL0_REFCLK_DIV_20 15
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#define GTHE3_COM_QPLL0_LPF_ADDR 0x0019
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#define GTHE3_COM_QPLL0_LPF_MSB 9
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#define GTHE3_COM_QPLL0_LPF_LSB 0
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#define GTHE3_COM_QPLL0_LPF_MASK BIT_MASK(GTHE3_COM_QPLL0_LPF_MSB, GTHE3_COM_QPLL0_LPF_LSB)
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#define GTHE3_COM_QPLL0_CFG1_G3_ADDR 0x001A
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#define GTHE3_COM_QPLL0_CFG1_G3_MSB 15
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#define GTHE3_COM_QPLL0_CFG1_G3_LSB 0
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#define GTHE3_COM_QPLL0_CFG1_G3_MASK BIT_MASK(GTHE3_COM_QPLL0_CFG1_G3_MSB, GTHE3_COM_QPLL0_CFG1_G3_LSB)
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#define GTHE3_COM_QPLL0_CFG2_G3_ADDR 0x001B
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#define GTHE3_COM_QPLL0_CFG2_G3_MSB 15
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#define GTHE3_COM_QPLL0_CFG2_G3_LSB 0
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#define GTHE3_COM_QPLL0_CFG2_G3_MASK BIT_MASK(GTHE3_COM_QPLL0_CFG2_G3_MSB, GTHE3_COM_QPLL0_CFG2_G3_LSB)
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#define GTHE3_COM_QPLL0_LPF_G3_ADDR 0x001C
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#define GTHE3_COM_QPLL0_LPF_G3_MSB 9
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#define GTHE3_COM_QPLL0_LPF_G3_LSB 0
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#define GTHE3_COM_QPLL0_LPF_G3_MASK BIT_MASK(GTHE3_COM_QPLL0_LPF_G3_MSB, GTHE3_COM_QPLL0_LPF_G3_LSB)
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#define GTHE3_COM_QPLL0_LOCK_CFG_G3_ADDR 0x001D
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#define GTHE3_COM_QPLL0_LOCK_CFG_G3_MSB 15
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#define GTHE3_COM_QPLL0_LOCK_CFG_G3_LSB 0
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#define GTHE3_COM_QPLL0_LOCK_CFG_G3_MASK BIT_MASK(GTHE3_COM_QPLL0_LOCK_CFG_G3_MSB, GTHE3_COM_QPLL0_LOCK_CFG_G3_LSB)
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#define GTHE3_COM_RSVD_ATTR1_ADDR 0x001E
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#define GTHE3_COM_RSVD_ATTR1_MSB 15
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#define GTHE3_COM_RSVD_ATTR1_LSB 0
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#define GTHE3_COM_RSVD_ATTR1_MASK BIT_MASK(GTHE3_COM_RSVD_ATTR1_MSB, GTHE3_COM_RSVD_ATTR1_LSB)
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#define GTHE3_COM_QPLL0_FBDIV_G3_ADDR 0x001F
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#define GTHE3_COM_QPLL0_FBDIV_G3_MSB 15
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#define GTHE3_COM_QPLL0_FBDIV_G3_LSB 8
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#define GTHE3_COM_QPLL0_FBDIV_G3_MASK BIT_MASK(GTHE3_COM_QPLL0_FBDIV_G3_MSB, GTHE3_COM_QPLL0_FBDIV_G3_LSB)
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#define GTHE3_COM_RXRECCLKOUT0_SEL_ADDR 0x001F
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#define GTHE3_COM_RXRECCLKOUT0_SEL_MSB 1
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#define GTHE3_COM_RXRECCLKOUT0_SEL_LSB 0
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#define GTHE3_COM_RXRECCLKOUT0_SEL_MASK BIT_MASK(GTHE3_COM_RXRECCLKOUT0_SEL_MSB, GTHE3_COM_RXRECCLKOUT0_SEL_LSB)
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#define GTHE3_COM_QPLL0_SDM_CFG0_ADDR 0x0020
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#define GTHE3_COM_QPLL0_SDM_CFG0_MSB 15
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#define GTHE3_COM_QPLL0_SDM_CFG0_LSB 0
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#define GTHE3_COM_QPLL0_SDM_CFG0_MASK BIT_MASK(GTHE3_COM_QPLL0_SDM_CFG0_MSB, GTHE3_COM_QPLL0_SDM_CFG0_LSB)
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#define GTHE3_COM_QPLL0_SDM_CFG1_ADDR 0x0021
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#define GTHE3_COM_QPLL0_SDM_CFG1_MSB 15
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#define GTHE3_COM_QPLL0_SDM_CFG1_LSB 0
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#define GTHE3_COM_QPLL0_SDM_CFG1_MASK BIT_MASK(GTHE3_COM_QPLL0_SDM_CFG1_MSB, GTHE3_COM_QPLL0_SDM_CFG1_LSB)
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#define GTHE3_COM_SDM0INITSEED0_0_ADDR 0x0022
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#define GTHE3_COM_SDM0INITSEED0_0_MSB 15
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#define GTHE3_COM_SDM0INITSEED0_0_LSB 0
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#define GTHE3_COM_SDM0INITSEED0_0_MASK BIT_MASK(GTHE3_COM_SDM0INITSEED0_0_MSB, GTHE3_COM_SDM0INITSEED0_0_LSB)
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#define GTHE3_COM_SDM0INITSEED0_1_ADDR 0x0023
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#define GTHE3_COM_SDM0INITSEED0_1_MSB 8
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#define GTHE3_COM_SDM0INITSEED0_1_LSB 0
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#define GTHE3_COM_SDM0INITSEED0_1_MASK BIT_MASK(GTHE3_COM_SDM0INITSEED0_1_MSB, GTHE3_COM_SDM0INITSEED0_1_LSB)
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#define GTHE3_COM_QPLL0_SDM_CFG2_ADDR 0x0024
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#define GTHE3_COM_QPLL0_SDM_CFG2_MSB 15
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#define GTHE3_COM_QPLL0_SDM_CFG2_LSB 0
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#define GTHE3_COM_QPLL0_SDM_CFG2_MASK BIT_MASK(GTHE3_COM_QPLL0_SDM_CFG2_MSB, GTHE3_COM_QPLL0_SDM_CFG2_LSB)
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#define GTHE3_COM_QPLL0_CP_G3_ADDR 0x0025
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#define GTHE3_COM_QPLL0_CP_G3_MSB 9
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#define GTHE3_COM_QPLL0_CP_G3_LSB 0
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#define GTHE3_COM_QPLL0_CP_G3_MASK BIT_MASK(GTHE3_COM_QPLL0_CP_G3_MSB, GTHE3_COM_QPLL0_CP_G3_LSB)
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#define GTHE3_COM_SDM0DATA1_0_ADDR 0x0028
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#define GTHE3_COM_SDM0DATA1_0_MSB 15
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#define GTHE3_COM_SDM0DATA1_0_LSB 0
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#define GTHE3_COM_SDM0DATA1_0_MASK BIT_MASK(GTHE3_COM_SDM0DATA1_0_MSB, GTHE3_COM_SDM0DATA1_0_LSB)
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#define GTHE3_COM_SDM0_WIDTH_PIN_SEL_ADDR 0x0029
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#define GTHE3_COM_SDM0_WIDTH_PIN_SEL_MSB 10
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#define GTHE3_COM_SDM0_WIDTH_PIN_SEL_LSB 10
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#define GTHE3_COM_SDM0_WIDTH_PIN_SEL_MASK BIT_MASK(GTHE3_COM_SDM0_WIDTH_PIN_SEL_MSB, GTHE3_COM_SDM0_WIDTH_PIN_SEL_LSB)
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#define GTHE3_COM_SDM0_DATA_PIN_SEL_ADDR 0x0029
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#define GTHE3_COM_SDM0_DATA_PIN_SEL_MSB 9
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#define GTHE3_COM_SDM0_DATA_PIN_SEL_LSB 9
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#define GTHE3_COM_SDM0_DATA_PIN_SEL_MASK BIT_MASK(GTHE3_COM_SDM0_DATA_PIN_SEL_MSB, GTHE3_COM_SDM0_DATA_PIN_SEL_LSB)
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#define GTHE3_COM_SDM0DATA1_1_ADDR 0x0029
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#define GTHE3_COM_SDM0DATA1_1_MSB 8
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#define GTHE3_COM_SDM0DATA1_1_LSB 0
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#define GTHE3_COM_SDM0DATA1_1_MASK BIT_MASK(GTHE3_COM_SDM0DATA1_1_MSB, GTHE3_COM_SDM0DATA1_1_LSB)
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#define GTHE3_COM_QPLL0_CFG4_ADDR 0x0030
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#define GTHE3_COM_QPLL0_CFG4_MSB 15
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#define GTHE3_COM_QPLL0_CFG4_LSB 0
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#define GTHE3_COM_QPLL0_CFG4_MASK BIT_MASK(GTHE3_COM_QPLL0_CFG4_MSB, GTHE3_COM_QPLL0_CFG4_LSB)
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#define GTHE3_COM_BIAS_CFG0_ADDR 0x0081
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#define GTHE3_COM_BIAS_CFG0_MSB 15
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#define GTHE3_COM_BIAS_CFG0_LSB 0
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#define GTHE3_COM_BIAS_CFG0_MASK BIT_MASK(GTHE3_COM_BIAS_CFG0_MSB, GTHE3_COM_BIAS_CFG0_LSB)
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#define GTHE3_COM_BIAS_CFG1_ADDR 0x0082
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#define GTHE3_COM_BIAS_CFG1_MSB 15
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#define GTHE3_COM_BIAS_CFG1_LSB 0
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#define GTHE3_COM_BIAS_CFG1_MASK BIT_MASK(GTHE3_COM_BIAS_CFG1_MSB, GTHE3_COM_BIAS_CFG1_LSB)
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#define GTHE3_COM_BIAS_CFG2_ADDR 0x0083
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#define GTHE3_COM_BIAS_CFG2_MSB 15
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#define GTHE3_COM_BIAS_CFG2_LSB 0
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#define GTHE3_COM_BIAS_CFG2_MASK BIT_MASK(GTHE3_COM_BIAS_CFG2_MSB, GTHE3_COM_BIAS_CFG2_LSB)
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#define GTHE3_COM_BIAS_CFG3_ADDR 0x0084
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#define GTHE3_COM_BIAS_CFG3_MSB 15
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#define GTHE3_COM_BIAS_CFG3_LSB 0
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#define GTHE3_COM_BIAS_CFG3_MASK BIT_MASK(GTHE3_COM_BIAS_CFG3_MSB, GTHE3_COM_BIAS_CFG3_LSB)
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#define GTHE3_COM_BIAS_CFG_RSVD_ADDR 0x0085
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#define GTHE3_COM_BIAS_CFG_RSVD_MSB 9
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#define GTHE3_COM_BIAS_CFG_RSVD_LSB 0
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#define GTHE3_COM_BIAS_CFG_RSVD_MASK BIT_MASK(GTHE3_COM_BIAS_CFG_RSVD_MSB, GTHE3_COM_BIAS_CFG_RSVD_LSB)
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#define GTHE3_COM_BIAS_CFG4_ADDR 0x0086
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#define GTHE3_COM_BIAS_CFG4_MSB 15
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#define GTHE3_COM_BIAS_CFG4_LSB 0
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#define GTHE3_COM_BIAS_CFG4_MASK BIT_MASK(GTHE3_COM_BIAS_CFG4_MSB, GTHE3_COM_BIAS_CFG4_LSB)
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#define GTHE3_COM_QPLL1_CFG0_ADDR 0x0088
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#define GTHE3_COM_QPLL1_CFG0_MSB 15
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#define GTHE3_COM_QPLL1_CFG0_LSB 0
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#define GTHE3_COM_QPLL1_CFG0_MASK BIT_MASK(GTHE3_COM_QPLL1_CFG0_MSB, GTHE3_COM_QPLL1_CFG0_LSB)
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#define GTHE3_COM_COMMON_CFG1_ADDR 0x0089
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#define GTHE3_COM_COMMON_CFG1_MSB 15
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#define GTHE3_COM_COMMON_CFG1_LSB 0
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#define GTHE3_COM_COMMON_CFG1_MASK BIT_MASK(GTHE3_COM_COMMON_CFG1_MSB, GTHE3_COM_COMMON_CFG1_LSB)
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#define GTHE3_COM_POR_CFG_ADDR 0x008B
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#define GTHE3_COM_POR_CFG_MSB 15
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#define GTHE3_COM_POR_CFG_LSB 0
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#define GTHE3_COM_POR_CFG_MASK BIT_MASK(GTHE3_COM_POR_CFG_MSB, GTHE3_COM_POR_CFG_LSB)
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#define GTHE3_COM_QPLL1_CFG1_ADDR 0x0090
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#define GTHE3_COM_QPLL1_CFG1_MSB 15
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#define GTHE3_COM_QPLL1_CFG1_LSB 0
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#define GTHE3_COM_QPLL1_CFG1_MASK BIT_MASK(GTHE3_COM_QPLL1_CFG1_MSB, GTHE3_COM_QPLL1_CFG1_LSB)
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#define GTHE3_COM_QPLL1_CFG2_ADDR 0x0091
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#define GTHE3_COM_QPLL1_CFG2_MSB 15
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#define GTHE3_COM_QPLL1_CFG2_LSB 0
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#define GTHE3_COM_QPLL1_CFG2_MASK BIT_MASK(GTHE3_COM_QPLL1_CFG2_MSB, GTHE3_COM_QPLL1_CFG2_LSB)
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#define GTHE3_COM_QPLL1_LOCK_CFG_ADDR 0x0092
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#define GTHE3_COM_QPLL1_LOCK_CFG_MSB 15
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#define GTHE3_COM_QPLL1_LOCK_CFG_LSB 0
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#define GTHE3_COM_QPLL1_LOCK_CFG_MASK BIT_MASK(GTHE3_COM_QPLL1_LOCK_CFG_MSB, GTHE3_COM_QPLL1_LOCK_CFG_LSB)
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#define GTHE3_COM_QPLL1_INIT_CFG0_ADDR 0x0093
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#define GTHE3_COM_QPLL1_INIT_CFG0_MSB 15
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#define GTHE3_COM_QPLL1_INIT_CFG0_LSB 0
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#define GTHE3_COM_QPLL1_INIT_CFG0_MASK BIT_MASK(GTHE3_COM_QPLL1_INIT_CFG0_MSB, GTHE3_COM_QPLL1_INIT_CFG0_LSB)
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#define GTHE3_COM_QPLL1_INIT_CFG1_ADDR 0x0094
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#define GTHE3_COM_QPLL1_INIT_CFG1_MSB 15
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#define GTHE3_COM_QPLL1_INIT_CFG1_LSB 8
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#define GTHE3_COM_QPLL1_INIT_CFG1_MASK BIT_MASK(GTHE3_COM_QPLL1_INIT_CFG1_MSB, GTHE3_COM_QPLL1_INIT_CFG1_LSB)
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#define GTHE3_COM_QPLL1_FBDIV_ADDR 0x0094
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#define GTHE3_COM_QPLL1_FBDIV_MSB 7
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#define GTHE3_COM_QPLL1_FBDIV_LSB 0
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#define GTHE3_COM_QPLL1_FBDIV_MASK BIT_MASK(GTHE3_COM_QPLL1_FBDIV_MSB, GTHE3_COM_QPLL1_FBDIV_LSB)
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#define GTHE3_COM_QPLL1_CFG3_ADDR 0x0095
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#define GTHE3_COM_QPLL1_CFG3_MSB 15
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#define GTHE3_COM_QPLL1_CFG3_LSB 0
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#define GTHE3_COM_QPLL1_CFG3_MASK BIT_MASK(GTHE3_COM_QPLL1_CFG3_MSB, GTHE3_COM_QPLL1_CFG3_LSB)
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#define GTHE3_COM_QPLL1_CP_ADDR 0x0096
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#define GTHE3_COM_QPLL1_CP_MSB 9
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#define GTHE3_COM_QPLL1_CP_LSB 0
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#define GTHE3_COM_QPLL1_CP_MASK BIT_MASK(GTHE3_COM_QPLL1_CP_MSB, GTHE3_COM_QPLL1_CP_LSB)
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#define GTHE3_COM_SARC_SEL_ADDR 0x0098
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#define GTHE3_COM_SARC_SEL_MSB 13
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#define GTHE3_COM_SARC_SEL_LSB 13
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#define GTHE3_COM_SARC_SEL_MASK BIT_MASK(GTHE3_COM_SARC_SEL_MSB, GTHE3_COM_SARC_SEL_LSB)
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#define GTHE3_COM_SARC_EN_ADDR 0x0098
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#define GTHE3_COM_SARC_EN_MSB 12
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#define GTHE3_COM_SARC_EN_LSB 12
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#define GTHE3_COM_SARC_EN_MASK BIT_MASK(GTHE3_COM_SARC_EN_MSB, GTHE3_COM_SARC_EN_LSB)
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#define GTHE3_COM_QPLL1_REFCLK_DIV_ADDR 0x0098
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#define GTHE3_COM_QPLL1_REFCLK_DIV_MSB 11
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#define GTHE3_COM_QPLL1_REFCLK_DIV_LSB 7
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#define GTHE3_COM_QPLL1_REFCLK_DIV_MASK BIT_MASK(GTHE3_COM_QPLL1_REFCLK_DIV_MSB, GTHE3_COM_QPLL1_REFCLK_DIV_LSB)
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#define GTHE3_COM_QPLL1_REFCLK_DIV_1 16
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#define GTHE3_COM_QPLL1_REFCLK_DIV_2 0
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#define GTHE3_COM_QPLL1_REFCLK_DIV_3 1
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#define GTHE3_COM_QPLL1_REFCLK_DIV_4 2
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#define GTHE3_COM_QPLL1_REFCLK_DIV_5 3
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#define GTHE3_COM_QPLL1_REFCLK_DIV_6 5
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#define GTHE3_COM_QPLL1_REFCLK_DIV_8 6
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#define GTHE3_COM_QPLL1_REFCLK_DIV_10 7
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#define GTHE3_COM_QPLL1_REFCLK_DIV_12 13
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#define GTHE3_COM_QPLL1_REFCLK_DIV_16 14
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#define GTHE3_COM_QPLL1_REFCLK_DIV_20 15
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#define GTHE3_COM_QPLL1_LPF_ADDR 0x0099
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#define GTHE3_COM_QPLL1_LPF_MSB 9
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#define GTHE3_COM_QPLL1_LPF_LSB 0
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#define GTHE3_COM_QPLL1_LPF_MASK BIT_MASK(GTHE3_COM_QPLL1_LPF_MSB, GTHE3_COM_QPLL1_LPF_LSB)
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#define GTHE3_COM_QPLL1_CFG1_G3_ADDR 0x009A
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#define GTHE3_COM_QPLL1_CFG1_G3_MSB 15
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#define GTHE3_COM_QPLL1_CFG1_G3_LSB 0
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#define GTHE3_COM_QPLL1_CFG1_G3_MASK BIT_MASK(GTHE3_COM_QPLL1_CFG1_G3_MSB, GTHE3_COM_QPLL1_CFG1_G3_LSB)
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#define GTHE3_COM_QPLL1_CFG2_G3_ADDR 0x009B
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#define GTHE3_COM_QPLL1_CFG2_G3_MSB 15
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#define GTHE3_COM_QPLL1_CFG2_G3_LSB 0
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#define GTHE3_COM_QPLL1_CFG2_G3_MASK BIT_MASK(GTHE3_COM_QPLL1_CFG2_G3_MSB, GTHE3_COM_QPLL1_CFG2_G3_LSB)
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#define GTHE3_COM_QPLL1_LPF_G3_ADDR 0x009C
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#define GTHE3_COM_QPLL1_LPF_G3_MSB 9
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#define GTHE3_COM_QPLL1_LPF_G3_LSB 0
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#define GTHE3_COM_QPLL1_LPF_G3_MASK BIT_MASK(GTHE3_COM_QPLL1_LPF_G3_MSB, GTHE3_COM_QPLL1_LPF_G3_LSB)
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#define GTHE3_COM_QPLL1_LOCK_CFG_G3_ADDR 0x009D
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#define GTHE3_COM_QPLL1_LOCK_CFG_G3_MSB 15
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#define GTHE3_COM_QPLL1_LOCK_CFG_G3_LSB 0
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#define GTHE3_COM_QPLL1_LOCK_CFG_G3_MASK BIT_MASK(GTHE3_COM_QPLL1_LOCK_CFG_G3_MSB, GTHE3_COM_QPLL1_LOCK_CFG_G3_LSB)
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#define GTHE3_COM_RSVD_ATTR2_ADDR 0x009E
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#define GTHE3_COM_RSVD_ATTR2_MSB 15
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#define GTHE3_COM_RSVD_ATTR2_LSB 0
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#define GTHE3_COM_RSVD_ATTR2_MASK BIT_MASK(GTHE3_COM_RSVD_ATTR2_MSB, GTHE3_COM_RSVD_ATTR2_LSB)
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#define GTHE3_COM_QPLL1_FBDIV_G3_ADDR 0x009F
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#define GTHE3_COM_QPLL1_FBDIV_G3_MSB 15
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#define GTHE3_COM_QPLL1_FBDIV_G3_LSB 8
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#define GTHE3_COM_QPLL1_FBDIV_G3_MASK BIT_MASK(GTHE3_COM_QPLL1_FBDIV_G3_MSB, GTHE3_COM_QPLL1_FBDIV_G3_LSB)
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#define GTHE3_COM_RXRECCLKOUT1_SEL_ADDR 0x009F
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#define GTHE3_COM_RXRECCLKOUT1_SEL_MSB 1
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#define GTHE3_COM_RXRECCLKOUT1_SEL_LSB 0
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#define GTHE3_COM_RXRECCLKOUT1_SEL_MASK BIT_MASK(GTHE3_COM_RXRECCLKOUT1_SEL_MSB, GTHE3_COM_RXRECCLKOUT1_SEL_LSB)
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#define GTHE3_COM_QPLL1_SDM_CFG0_ADDR 0x00A0
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#define GTHE3_COM_QPLL1_SDM_CFG0_MSB 15
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#define GTHE3_COM_QPLL1_SDM_CFG0_LSB 0
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#define GTHE3_COM_QPLL1_SDM_CFG0_MASK BIT_MASK(GTHE3_COM_QPLL1_SDM_CFG0_MSB, GTHE3_COM_QPLL1_SDM_CFG0_LSB)
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#define GTHE3_COM_QPLL1_SDM_CFG1_ADDR 0x00A1
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#define GTHE3_COM_QPLL1_SDM_CFG1_MSB 15
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#define GTHE3_COM_QPLL1_SDM_CFG1_LSB 0
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#define GTHE3_COM_QPLL1_SDM_CFG1_MASK BIT_MASK(GTHE3_COM_QPLL1_SDM_CFG1_MSB, GTHE3_COM_QPLL1_SDM_CFG1_LSB)
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#define GTHE3_COM_SDM1INITSEED0_0_ADDR 0x00A2
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#define GTHE3_COM_SDM1INITSEED0_0_MSB 15
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#define GTHE3_COM_SDM1INITSEED0_0_LSB 0
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#define GTHE3_COM_SDM1INITSEED0_0_MASK BIT_MASK(GTHE3_COM_SDM1INITSEED0_0_MSB, GTHE3_COM_SDM1INITSEED0_0_LSB)
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#define GTHE3_COM_SDM1INITSEED0_1_ADDR 0x00A3
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#define GTHE3_COM_SDM1INITSEED0_1_MSB 8
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#define GTHE3_COM_SDM1INITSEED0_1_LSB 0
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#define GTHE3_COM_SDM1INITSEED0_1_MASK BIT_MASK(GTHE3_COM_SDM1INITSEED0_1_MSB, GTHE3_COM_SDM1INITSEED0_1_LSB)
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#define GTHE3_COM_QPLL1_SDM_CFG2_ADDR 0x00A4
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#define GTHE3_COM_QPLL1_SDM_CFG2_MSB 15
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#define GTHE3_COM_QPLL1_SDM_CFG2_LSB 0
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#define GTHE3_COM_QPLL1_SDM_CFG2_MASK BIT_MASK(GTHE3_COM_QPLL1_SDM_CFG2_MSB, GTHE3_COM_QPLL1_SDM_CFG2_LSB)
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#define GTHE3_COM_QPLL1_CP_G3_ADDR 0x00A5
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#define GTHE3_COM_QPLL1_CP_G3_MSB 9
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#define GTHE3_COM_QPLL1_CP_G3_LSB 0
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#define GTHE3_COM_QPLL1_CP_G3_MASK BIT_MASK(GTHE3_COM_QPLL1_CP_G3_MSB, GTHE3_COM_QPLL1_CP_G3_LSB)
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#define GTHE3_COM_SDM1DATA1_0_ADDR 0x00A8
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#define GTHE3_COM_SDM1DATA1_0_MSB 15
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#define GTHE3_COM_SDM1DATA1_0_LSB 0
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#define GTHE3_COM_SDM1DATA1_0_MASK BIT_MASK(GTHE3_COM_SDM1DATA1_0_MSB, GTHE3_COM_SDM1DATA1_0_LSB)
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#define GTHE3_COM_SDM1_WIDTH_PIN_SEL_ADDR 0x00A9
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#define GTHE3_COM_SDM1_WIDTH_PIN_SEL_MSB 10
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#define GTHE3_COM_SDM1_WIDTH_PIN_SEL_LSB 10
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#define GTHE3_COM_SDM1_WIDTH_PIN_SEL_MASK BIT_MASK(GTHE3_COM_SDM1_WIDTH_PIN_SEL_MSB, GTHE3_COM_SDM1_WIDTH_PIN_SEL_LSB)
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#define GTHE3_COM_SDM1_DATA_PIN_SEL_ADDR 0x00A9
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#define GTHE3_COM_SDM1_DATA_PIN_SEL_MSB 9
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#define GTHE3_COM_SDM1_DATA_PIN_SEL_LSB 9
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#define GTHE3_COM_SDM1_DATA_PIN_SEL_MASK BIT_MASK(GTHE3_COM_SDM1_DATA_PIN_SEL_MSB, GTHE3_COM_SDM1_DATA_PIN_SEL_LSB)
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#define GTHE3_COM_SDM1DATA1_1_ADDR 0x00A9
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#define GTHE3_COM_SDM1DATA1_1_MSB 8
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#define GTHE3_COM_SDM1DATA1_1_LSB 0
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#define GTHE3_COM_SDM1DATA1_1_MASK BIT_MASK(GTHE3_COM_SDM1DATA1_1_MSB, GTHE3_COM_SDM1DATA1_1_LSB)
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#define GTHE3_COM_RSVD_ATTR3_ADDR 0x00AD
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#define GTHE3_COM_RSVD_ATTR3_MSB 15
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#define GTHE3_COM_RSVD_ATTR3_LSB 0
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#define GTHE3_COM_RSVD_ATTR3_MASK BIT_MASK(GTHE3_COM_RSVD_ATTR3_MSB, GTHE3_COM_RSVD_ATTR3_LSB)
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#define GTHE3_COM_QPLL1_CFG4_ADDR 0x00B0
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#define GTHE3_COM_QPLL1_CFG4_MSB 15
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#define GTHE3_COM_QPLL1_CFG4_LSB 0
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#define GTHE3_COM_QPLL1_CFG4_MASK BIT_MASK(GTHE3_COM_QPLL1_CFG4_MSB, GTHE3_COM_QPLL1_CFG4_LSB)
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// channel registers
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#define GTHE3_CH_CDR_SWAP_MODE_EN_ADDR 0x0002
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#define GTHE3_CH_CDR_SWAP_MODE_EN_MSB 0
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#define GTHE3_CH_CDR_SWAP_MODE_EN_LSB 0
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#define GTHE3_CH_CDR_SWAP_MODE_EN_MASK BIT_MASK(GTHE3_CH_CDR_SWAP_MODE_EN_MSB, GTHE3_CH_CDR_SWAP_MODE_EN_LSB)
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#define GTHE3_CH_RXBUFRESET_TIME_ADDR 0x0003
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#define GTHE3_CH_RXBUFRESET_TIME_MSB 15
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#define GTHE3_CH_RXBUFRESET_TIME_LSB 11
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#define GTHE3_CH_RXBUFRESET_TIME_MASK BIT_MASK(GTHE3_CH_RXBUFRESET_TIME_MSB, GTHE3_CH_RXBUFRESET_TIME_LSB)
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#define GTHE3_CH_EYE_SCAN_SWAP_EN_ADDR 0x0003
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#define GTHE3_CH_EYE_SCAN_SWAP_EN_MSB 9
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#define GTHE3_CH_EYE_SCAN_SWAP_EN_LSB 9
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#define GTHE3_CH_EYE_SCAN_SWAP_EN_MASK BIT_MASK(GTHE3_CH_EYE_SCAN_SWAP_EN_MSB, GTHE3_CH_EYE_SCAN_SWAP_EN_LSB)
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#define GTHE3_CH_RX_DATA_WIDTH_ADDR 0x0003
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#define GTHE3_CH_RX_DATA_WIDTH_MSB 8
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#define GTHE3_CH_RX_DATA_WIDTH_LSB 5
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#define GTHE3_CH_RX_DATA_WIDTH_MASK BIT_MASK(GTHE3_CH_RX_DATA_WIDTH_MSB, GTHE3_CH_RX_DATA_WIDTH_LSB)
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#define GTHE3_CH_RX_DATA_WIDTH_16 2
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#define GTHE3_CH_RX_DATA_WIDTH_20 3
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#define GTHE3_CH_RX_DATA_WIDTH_32 4
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#define GTHE3_CH_RX_DATA_WIDTH_40 5
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#define GTHE3_CH_RX_DATA_WIDTH_64 6
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#define GTHE3_CH_RX_DATA_WIDTH_80 7
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#define GTHE3_CH_RX_DATA_WIDTH_128 8
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#define GTHE3_CH_RX_DATA_WIDTH_160 9
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#define GTHE3_CH_RXCDRFREQRESET_TIME_ADDR 0x0003
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#define GTHE3_CH_RXCDRFREQRESET_TIME_MSB 4
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#define GTHE3_CH_RXCDRFREQRESET_TIME_LSB 0
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#define GTHE3_CH_RXCDRFREQRESET_TIME_MASK BIT_MASK(GTHE3_CH_RXCDRFREQRESET_TIME_MSB, GTHE3_CH_RXCDRFREQRESET_TIME_LSB)
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#define GTHE3_CH_RXCDRPHRESET_TIME_ADDR 0x0004
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#define GTHE3_CH_RXCDRPHRESET_TIME_MSB 15
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#define GTHE3_CH_RXCDRPHRESET_TIME_LSB 11
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#define GTHE3_CH_RXCDRPHRESET_TIME_MASK BIT_MASK(GTHE3_CH_RXCDRPHRESET_TIME_MSB, GTHE3_CH_RXCDRPHRESET_TIME_LSB)
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#define GTHE3_CH_PCI3_RX_ELECIDLE_H2L_DISABLE_ADDR 0x0004
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#define GTHE3_CH_PCI3_RX_ELECIDLE_H2L_DISABLE_MSB 10
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#define GTHE3_CH_PCI3_RX_ELECIDLE_H2L_DISABLE_LSB 8
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#define GTHE3_CH_PCI3_RX_ELECIDLE_H2L_DISABLE_MASK BIT_MASK(GTHE3_CH_PCI3_RX_ELECIDLE_H2L_DISABLE_MSB, GTHE3_CH_PCI3_RX_ELECIDLE_H2L_DISABLE_LSB)
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#define GTHE3_CH_RXDFELPMRESET_TIME_ADDR 0x0004
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#define GTHE3_CH_RXDFELPMRESET_TIME_MSB 7
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#define GTHE3_CH_RXDFELPMRESET_TIME_LSB 1
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#define GTHE3_CH_RXDFELPMRESET_TIME_MASK BIT_MASK(GTHE3_CH_RXDFELPMRESET_TIME_MSB, GTHE3_CH_RXDFELPMRESET_TIME_LSB)
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#define GTHE3_CH_RX_FABINT_USRCLK_FLOP_ADDR 0x0004
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#define GTHE3_CH_RX_FABINT_USRCLK_FLOP_MSB 0
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#define GTHE3_CH_RX_FABINT_USRCLK_FLOP_LSB 0
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#define GTHE3_CH_RX_FABINT_USRCLK_FLOP_MASK BIT_MASK(GTHE3_CH_RX_FABINT_USRCLK_FLOP_MSB, GTHE3_CH_RX_FABINT_USRCLK_FLOP_LSB)
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#define GTHE3_CH_RXPMARESET_TIME_ADDR 0x0005
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#define GTHE3_CH_RXPMARESET_TIME_MSB 15
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#define GTHE3_CH_RXPMARESET_TIME_LSB 11
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#define GTHE3_CH_RXPMARESET_TIME_MASK BIT_MASK(GTHE3_CH_RXPMARESET_TIME_MSB, GTHE3_CH_RXPMARESET_TIME_LSB)
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#define GTHE3_CH_PCI3_RX_ELECIDLE_LP4_DISABLE_ADDR 0x0005
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#define GTHE3_CH_PCI3_RX_ELECIDLE_LP4_DISABLE_MSB 10
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#define GTHE3_CH_PCI3_RX_ELECIDLE_LP4_DISABLE_LSB 10
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#define GTHE3_CH_PCI3_RX_ELECIDLE_LP4_DISABLE_MASK BIT_MASK(GTHE3_CH_PCI3_RX_ELECIDLE_LP4_DISABLE_MSB, GTHE3_CH_PCI3_RX_ELECIDLE_LP4_DISABLE_LSB)
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#define GTHE3_CH_PCI3_RX_ELECIDLE_EI2_ENABLE_ADDR 0x0005
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#define GTHE3_CH_PCI3_RX_ELECIDLE_EI2_ENABLE_MSB 9
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#define GTHE3_CH_PCI3_RX_ELECIDLE_EI2_ENABLE_LSB 9
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#define GTHE3_CH_PCI3_RX_ELECIDLE_EI2_ENABLE_MASK BIT_MASK(GTHE3_CH_PCI3_RX_ELECIDLE_EI2_ENABLE_MSB, GTHE3_CH_PCI3_RX_ELECIDLE_EI2_ENABLE_LSB)
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#define GTHE3_CH_PCI3_RX_FIFO_DISABLE_ADDR 0x0005
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#define GTHE3_CH_PCI3_RX_FIFO_DISABLE_MSB 8
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#define GTHE3_CH_PCI3_RX_FIFO_DISABLE_LSB 8
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#define GTHE3_CH_PCI3_RX_FIFO_DISABLE_MASK BIT_MASK(GTHE3_CH_PCI3_RX_FIFO_DISABLE_MSB, GTHE3_CH_PCI3_RX_FIFO_DISABLE_LSB)
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#define GTHE3_CH_RXPCSRESET_TIME_ADDR 0x0005
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#define GTHE3_CH_RXPCSRESET_TIME_MSB 7
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#define GTHE3_CH_RXPCSRESET_TIME_LSB 3
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#define GTHE3_CH_RXPCSRESET_TIME_MASK BIT_MASK(GTHE3_CH_RXPCSRESET_TIME_MSB, GTHE3_CH_RXPCSRESET_TIME_LSB)
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#define GTHE3_CH_RXELECIDLE_CFG_ADDR 0x0005
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#define GTHE3_CH_RXELECIDLE_CFG_MSB 2
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#define GTHE3_CH_RXELECIDLE_CFG_LSB 0
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#define GTHE3_CH_RXELECIDLE_CFG_MASK BIT_MASK(GTHE3_CH_RXELECIDLE_CFG_MSB, GTHE3_CH_RXELECIDLE_CFG_LSB)
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#define GTHE3_CH_RXELECIDLE_CFG_SIGCFG_1 0
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#define GTHE3_CH_RXELECIDLE_CFG_SIGCFG_2 1
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#define GTHE3_CH_RXELECIDLE_CFG_SIGCFG_3 2
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#define GTHE3_CH_RXELECIDLE_CFG_SIGCFG_4 3
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#define GTHE3_CH_RXELECIDLE_CFG_SIGCFG_6 4
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#define GTHE3_CH_RXELECIDLE_CFG_SIGCFG_8 5
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#define GTHE3_CH_RXELECIDLE_CFG_SIGCFG_12 6
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#define GTHE3_CH_RXELECIDLE_CFG_SIGCFG_16 7
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#define GTHE3_CH_RXDFE_HB_CFG1_ADDR 0x0006
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#define GTHE3_CH_RXDFE_HB_CFG1_MSB 15
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#define GTHE3_CH_RXDFE_HB_CFG1_LSB 0
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#define GTHE3_CH_RXDFE_HB_CFG1_MASK BIT_MASK(GTHE3_CH_RXDFE_HB_CFG1_MSB, GTHE3_CH_RXDFE_HB_CFG1_LSB)
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#define GTHE3_CH_TXPMARESET_TIME_ADDR 0x0009
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#define GTHE3_CH_TXPMARESET_TIME_MSB 15
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#define GTHE3_CH_TXPMARESET_TIME_LSB 11
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#define GTHE3_CH_TXPMARESET_TIME_MASK BIT_MASK(GTHE3_CH_TXPMARESET_TIME_MSB, GTHE3_CH_TXPMARESET_TIME_LSB)
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#define GTHE3_CH_RX_PMA_POWER_SAVE_ADDR 0x0009
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#define GTHE3_CH_RX_PMA_POWER_SAVE_MSB 10
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#define GTHE3_CH_RX_PMA_POWER_SAVE_LSB 10
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#define GTHE3_CH_RX_PMA_POWER_SAVE_MASK BIT_MASK(GTHE3_CH_RX_PMA_POWER_SAVE_MSB, GTHE3_CH_RX_PMA_POWER_SAVE_LSB)
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#define GTHE3_CH_TX_PMA_POWER_SAVE_ADDR 0x0009
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#define GTHE3_CH_TX_PMA_POWER_SAVE_MSB 9
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#define GTHE3_CH_TX_PMA_POWER_SAVE_LSB 9
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#define GTHE3_CH_TX_PMA_POWER_SAVE_MASK BIT_MASK(GTHE3_CH_TX_PMA_POWER_SAVE_MSB, GTHE3_CH_TX_PMA_POWER_SAVE_LSB)
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#define GTHE3_CH_TXPCSRESET_TIME_ADDR 0x0009
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#define GTHE3_CH_TXPCSRESET_TIME_MSB 7
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#define GTHE3_CH_TXPCSRESET_TIME_LSB 3
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#define GTHE3_CH_TXPCSRESET_TIME_MASK BIT_MASK(GTHE3_CH_TXPCSRESET_TIME_MSB, GTHE3_CH_TXPCSRESET_TIME_LSB)
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#define GTHE3_CH_WB_MODE_ADDR 0x000B
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#define GTHE3_CH_WB_MODE_MSB 15
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#define GTHE3_CH_WB_MODE_LSB 14
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#define GTHE3_CH_WB_MODE_MASK BIT_MASK(GTHE3_CH_WB_MODE_MSB, GTHE3_CH_WB_MODE_LSB)
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#define GTHE3_CH_RXPMACLK_SEL_ADDR 0x000B
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#define GTHE3_CH_RXPMACLK_SEL_MSB 9
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#define GTHE3_CH_RXPMACLK_SEL_LSB 8
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#define GTHE3_CH_RXPMACLK_SEL_MASK BIT_MASK(GTHE3_CH_RXPMACLK_SEL_MSB, GTHE3_CH_RXPMACLK_SEL_LSB)
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#define GTHE3_CH_RXPMACLK_SEL_DATA 0
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#define GTHE3_CH_RXPMACLK_SEL_EYESCAN 1
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#define GTHE3_CH_RXPMACLK_SEL_CROSSING 2
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#define GTHE3_CH_TX_FABINT_USRCLK_FLOP_ADDR 0x000B
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#define GTHE3_CH_TX_FABINT_USRCLK_FLOP_MSB 4
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#define GTHE3_CH_TX_FABINT_USRCLK_FLOP_LSB 4
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#define GTHE3_CH_TX_FABINT_USRCLK_FLOP_MASK BIT_MASK(GTHE3_CH_TX_FABINT_USRCLK_FLOP_MSB, GTHE3_CH_TX_FABINT_USRCLK_FLOP_LSB)
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#define GTHE3_CH_TX_PROGCLK_SEL_ADDR 0x000C
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#define GTHE3_CH_TX_PROGCLK_SEL_MSB 11
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#define GTHE3_CH_TX_PROGCLK_SEL_LSB 10
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#define GTHE3_CH_TX_PROGCLK_SEL_MASK BIT_MASK(GTHE3_CH_TX_PROGCLK_SEL_MSB, GTHE3_CH_TX_PROGCLK_SEL_LSB)
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#define GTHE3_CH_TX_PROGCLK_SEL_POSTPI 0
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#define GTHE3_CH_TX_PROGCLK_SEL_PREPI 1
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#define GTHE3_CH_TX_PROGCLK_SEL_CPLL 2
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#define GTHE3_CH_RXISCANRESET_TIME_ADDR 0x000C
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#define GTHE3_CH_RXISCANRESET_TIME_MSB 9
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#define GTHE3_CH_RXISCANRESET_TIME_LSB 5
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#define GTHE3_CH_RXISCANRESET_TIME_MASK BIT_MASK(GTHE3_CH_RXISCANRESET_TIME_MSB, GTHE3_CH_RXISCANRESET_TIME_LSB)
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#define GTHE3_CH_RXCDR_CFG0_ADDR 0x000E
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#define GTHE3_CH_RXCDR_CFG0_MSB 15
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#define GTHE3_CH_RXCDR_CFG0_LSB 0
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#define GTHE3_CH_RXCDR_CFG0_MASK BIT_MASK(GTHE3_CH_RXCDR_CFG0_MSB, GTHE3_CH_RXCDR_CFG0_LSB)
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#define GTHE3_CH_RXCDR_CFG1_ADDR 0x000F
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#define GTHE3_CH_RXCDR_CFG1_MSB 15
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#define GTHE3_CH_RXCDR_CFG1_LSB 0
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#define GTHE3_CH_RXCDR_CFG1_MASK BIT_MASK(GTHE3_CH_RXCDR_CFG1_MSB, GTHE3_CH_RXCDR_CFG1_LSB)
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#define GTHE3_CH_RXCDR_CFG2_ADDR 0x0010
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#define GTHE3_CH_RXCDR_CFG2_MSB 15
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#define GTHE3_CH_RXCDR_CFG2_LSB 0
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#define GTHE3_CH_RXCDR_CFG2_MASK BIT_MASK(GTHE3_CH_RXCDR_CFG2_MSB, GTHE3_CH_RXCDR_CFG2_LSB)
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#define GTHE3_CH_RXCDR_CFG3_ADDR 0x0011
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#define GTHE3_CH_RXCDR_CFG3_MSB 15
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#define GTHE3_CH_RXCDR_CFG3_LSB 0
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#define GTHE3_CH_RXCDR_CFG3_MASK BIT_MASK(GTHE3_CH_RXCDR_CFG3_MSB, GTHE3_CH_RXCDR_CFG3_LSB)
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#define GTHE3_CH_RXCDR_CFG4_ADDR 0x0012
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#define GTHE3_CH_RXCDR_CFG4_MSB 15
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#define GTHE3_CH_RXCDR_CFG4_LSB 0
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#define GTHE3_CH_RXCDR_CFG4_MASK BIT_MASK(GTHE3_CH_RXCDR_CFG4_MSB, GTHE3_CH_RXCDR_CFG4_LSB)
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#define GTHE3_CH_RXCDR_LOCK_CFG0_ADDR 0x0013
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#define GTHE3_CH_RXCDR_LOCK_CFG0_MSB 15
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#define GTHE3_CH_RXCDR_LOCK_CFG0_LSB 0
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#define GTHE3_CH_RXCDR_LOCK_CFG0_MASK BIT_MASK(GTHE3_CH_RXCDR_LOCK_CFG0_MSB, GTHE3_CH_RXCDR_LOCK_CFG0_LSB)
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#define GTHE3_CH_CHAN_BOND_MAX_SKEW_ADDR 0x0014
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#define GTHE3_CH_CHAN_BOND_MAX_SKEW_MSB 15
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#define GTHE3_CH_CHAN_BOND_MAX_SKEW_LSB 12
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#define GTHE3_CH_CHAN_BOND_MAX_SKEW_MASK BIT_MASK(GTHE3_CH_CHAN_BOND_MAX_SKEW_MSB, GTHE3_CH_CHAN_BOND_MAX_SKEW_LSB)
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#define GTHE3_CH_CHAN_BOND_SEQ_LEN_ADDR 0x0014
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#define GTHE3_CH_CHAN_BOND_SEQ_LEN_MSB 11
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#define GTHE3_CH_CHAN_BOND_SEQ_LEN_LSB 10
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#define GTHE3_CH_CHAN_BOND_SEQ_LEN_MASK BIT_MASK(GTHE3_CH_CHAN_BOND_SEQ_LEN_MSB, GTHE3_CH_CHAN_BOND_SEQ_LEN_LSB)
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#define GTHE3_CH_CHAN_BOND_SEQ_LEN_1 0
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#define GTHE3_CH_CHAN_BOND_SEQ_LEN_2 1
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#define GTHE3_CH_CHAN_BOND_SEQ_LEN_3 2
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#define GTHE3_CH_CHAN_BOND_SEQ_LEN_4 3
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#define GTHE3_CH_CHAN_BOND_SEQ_1_1_ADDR 0x0014
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#define GTHE3_CH_CHAN_BOND_SEQ_1_1_MSB 9
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#define GTHE3_CH_CHAN_BOND_SEQ_1_1_LSB 0
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#define GTHE3_CH_CHAN_BOND_SEQ_1_1_MASK BIT_MASK(GTHE3_CH_CHAN_BOND_SEQ_1_1_MSB, GTHE3_CH_CHAN_BOND_SEQ_1_1_LSB)
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#define GTHE3_CH_PCI3_RX_ELECIDLE_HI_COUNT_ADDR 0x0015
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#define GTHE3_CH_PCI3_RX_ELECIDLE_HI_COUNT_MSB 15
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#define GTHE3_CH_PCI3_RX_ELECIDLE_HI_COUNT_LSB 10
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#define GTHE3_CH_PCI3_RX_ELECIDLE_HI_COUNT_MASK BIT_MASK(GTHE3_CH_PCI3_RX_ELECIDLE_HI_COUNT_MSB, GTHE3_CH_PCI3_RX_ELECIDLE_HI_COUNT_LSB)
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#define GTHE3_CH_CHAN_BOND_SEQ_1_3_ADDR 0x0015
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#define GTHE3_CH_CHAN_BOND_SEQ_1_3_MSB 9
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#define GTHE3_CH_CHAN_BOND_SEQ_1_3_LSB 0
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#define GTHE3_CH_CHAN_BOND_SEQ_1_3_MASK BIT_MASK(GTHE3_CH_CHAN_BOND_SEQ_1_3_MSB, GTHE3_CH_CHAN_BOND_SEQ_1_3_LSB)
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#define GTHE3_CH_PCI3_RX_ELECIDLE_H2L_COUNT_ADDR 0x0016
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#define GTHE3_CH_PCI3_RX_ELECIDLE_H2L_COUNT_MSB 15
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#define GTHE3_CH_PCI3_RX_ELECIDLE_H2L_COUNT_LSB 10
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#define GTHE3_CH_PCI3_RX_ELECIDLE_H2L_COUNT_MASK BIT_MASK(GTHE3_CH_PCI3_RX_ELECIDLE_H2L_COUNT_MSB, GTHE3_CH_PCI3_RX_ELECIDLE_H2L_COUNT_LSB)
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#define GTHE3_CH_CHAN_BOND_SEQ_1_4_ADDR 0x0016
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#define GTHE3_CH_CHAN_BOND_SEQ_1_4_MSB 9
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#define GTHE3_CH_CHAN_BOND_SEQ_1_4_LSB 0
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#define GTHE3_CH_CHAN_BOND_SEQ_1_4_MASK BIT_MASK(GTHE3_CH_CHAN_BOND_SEQ_1_4_MSB, GTHE3_CH_CHAN_BOND_SEQ_1_4_LSB)
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#define GTHE3_CH_RX_BUFFER_CFG_ADDR 0x0017
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#define GTHE3_CH_RX_BUFFER_CFG_MSB 15
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#define GTHE3_CH_RX_BUFFER_CFG_LSB 10
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#define GTHE3_CH_RX_BUFFER_CFG_MASK BIT_MASK(GTHE3_CH_RX_BUFFER_CFG_MSB, GTHE3_CH_RX_BUFFER_CFG_LSB)
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#define GTHE3_CH_RX_DEFER_RESET_BUF_EN_ADDR 0x0017
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#define GTHE3_CH_RX_DEFER_RESET_BUF_EN_MSB 9
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#define GTHE3_CH_RX_DEFER_RESET_BUF_EN_LSB 9
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#define GTHE3_CH_RX_DEFER_RESET_BUF_EN_MASK BIT_MASK(GTHE3_CH_RX_DEFER_RESET_BUF_EN_MSB, GTHE3_CH_RX_DEFER_RESET_BUF_EN_LSB)
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#define GTHE3_CH_OOBDIVCTL0_ADDR 0x0017
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#define GTHE3_CH_OOBDIVCTL0_MSB 8
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#define GTHE3_CH_OOBDIVCTL0_LSB 7
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#define GTHE3_CH_OOBDIVCTL0_MASK BIT_MASK(GTHE3_CH_OOBDIVCTL0_MSB, GTHE3_CH_OOBDIVCTL0_LSB)
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#define GTHE3_CH_PCI3_AUTO_REALIGN_ADDR 0x0017
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#define GTHE3_CH_PCI3_AUTO_REALIGN_MSB 6
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#define GTHE3_CH_PCI3_AUTO_REALIGN_LSB 5
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#define GTHE3_CH_PCI3_AUTO_REALIGN_MASK BIT_MASK(GTHE3_CH_PCI3_AUTO_REALIGN_MSB, GTHE3_CH_PCI3_AUTO_REALIGN_LSB)
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#define GTHE3_CH_PCI3_AUTO_REALIGN_FRST_SMPL 0
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#define GTHE3_CH_PCI3_AUTO_REALIGN_OVR_8_BLK 1
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#define GTHE3_CH_PCI3_AUTO_REALIGN_OVR_64_BLK 2
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#define GTHE3_CH_PCI3_AUTO_REALIGN_OVR_1K_BLK 3
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#define GTHE3_CH_PCI3_PIPE_RX_ELECIDLE_ADDR 0x0017
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#define GTHE3_CH_PCI3_PIPE_RX_ELECIDLE_MSB 4
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#define GTHE3_CH_PCI3_PIPE_RX_ELECIDLE_LSB 4
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#define GTHE3_CH_PCI3_PIPE_RX_ELECIDLE_MASK BIT_MASK(GTHE3_CH_PCI3_PIPE_RX_ELECIDLE_MSB, GTHE3_CH_PCI3_PIPE_RX_ELECIDLE_LSB)
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#define GTHE3_CH_CHAN_BOND_SEQ_1_ENABLE_ADDR 0x0018
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#define GTHE3_CH_CHAN_BOND_SEQ_1_ENABLE_MSB 15
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#define GTHE3_CH_CHAN_BOND_SEQ_1_ENABLE_LSB 12
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#define GTHE3_CH_CHAN_BOND_SEQ_1_ENABLE_MASK BIT_MASK(GTHE3_CH_CHAN_BOND_SEQ_1_ENABLE_MSB, GTHE3_CH_CHAN_BOND_SEQ_1_ENABLE_LSB)
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#define GTHE3_CH_PCI3_RX_ASYNC_EBUF_BYPASS_ADDR 0x0018
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#define GTHE3_CH_PCI3_RX_ASYNC_EBUF_BYPASS_MSB 11
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#define GTHE3_CH_PCI3_RX_ASYNC_EBUF_BYPASS_LSB 10
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#define GTHE3_CH_PCI3_RX_ASYNC_EBUF_BYPASS_MASK BIT_MASK(GTHE3_CH_PCI3_RX_ASYNC_EBUF_BYPASS_MSB, GTHE3_CH_PCI3_RX_ASYNC_EBUF_BYPASS_LSB)
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#define GTHE3_CH_CHAN_BOND_SEQ_2_1_ADDR 0x0018
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#define GTHE3_CH_CHAN_BOND_SEQ_2_1_MSB 9
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#define GTHE3_CH_CHAN_BOND_SEQ_2_1_LSB 0
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#define GTHE3_CH_CHAN_BOND_SEQ_2_1_MASK BIT_MASK(GTHE3_CH_CHAN_BOND_SEQ_2_1_MSB, GTHE3_CH_CHAN_BOND_SEQ_2_1_LSB)
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#define GTHE3_CH_CHAN_BOND_SEQ_2_2_ADDR 0x0019
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#define GTHE3_CH_CHAN_BOND_SEQ_2_2_MSB 9
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#define GTHE3_CH_CHAN_BOND_SEQ_2_2_LSB 0
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#define GTHE3_CH_CHAN_BOND_SEQ_2_2_MASK BIT_MASK(GTHE3_CH_CHAN_BOND_SEQ_2_2_MSB, GTHE3_CH_CHAN_BOND_SEQ_2_2_LSB)
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#define GTHE3_CH_CHAN_BOND_SEQ_2_3_ADDR 0x001A
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#define GTHE3_CH_CHAN_BOND_SEQ_2_3_MSB 9
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#define GTHE3_CH_CHAN_BOND_SEQ_2_3_LSB 0
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#define GTHE3_CH_CHAN_BOND_SEQ_2_3_MASK BIT_MASK(GTHE3_CH_CHAN_BOND_SEQ_2_3_MSB, GTHE3_CH_CHAN_BOND_SEQ_2_3_LSB)
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#define GTHE3_CH_CHAN_BOND_SEQ_2_4_ADDR 0x001B
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#define GTHE3_CH_CHAN_BOND_SEQ_2_4_MSB 9
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#define GTHE3_CH_CHAN_BOND_SEQ_2_4_LSB 0
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#define GTHE3_CH_CHAN_BOND_SEQ_2_4_MASK BIT_MASK(GTHE3_CH_CHAN_BOND_SEQ_2_4_MSB, GTHE3_CH_CHAN_BOND_SEQ_2_4_LSB)
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#define GTHE3_CH_CHAN_BOND_SEQ_2_ENABLE_ADDR 0x001C
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#define GTHE3_CH_CHAN_BOND_SEQ_2_ENABLE_MSB 15
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#define GTHE3_CH_CHAN_BOND_SEQ_2_ENABLE_LSB 12
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#define GTHE3_CH_CHAN_BOND_SEQ_2_ENABLE_MASK BIT_MASK(GTHE3_CH_CHAN_BOND_SEQ_2_ENABLE_MSB, GTHE3_CH_CHAN_BOND_SEQ_2_ENABLE_LSB)
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#define GTHE3_CH_CHAN_BOND_SEQ_2_USE_ADDR 0x001C
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#define GTHE3_CH_CHAN_BOND_SEQ_2_USE_MSB 11
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#define GTHE3_CH_CHAN_BOND_SEQ_2_USE_LSB 11
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#define GTHE3_CH_CHAN_BOND_SEQ_2_USE_MASK BIT_MASK(GTHE3_CH_CHAN_BOND_SEQ_2_USE_MSB, GTHE3_CH_CHAN_BOND_SEQ_2_USE_LSB)
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#define GTHE3_CH_CLK_COR_KEEP_IDLE_ADDR 0x001C
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#define GTHE3_CH_CLK_COR_KEEP_IDLE_MSB 6
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#define GTHE3_CH_CLK_COR_KEEP_IDLE_LSB 6
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#define GTHE3_CH_CLK_COR_KEEP_IDLE_MASK BIT_MASK(GTHE3_CH_CLK_COR_KEEP_IDLE_MSB, GTHE3_CH_CLK_COR_KEEP_IDLE_LSB)
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#define GTHE3_CH_CLK_COR_MIN_LAT_ADDR 0x001C
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#define GTHE3_CH_CLK_COR_MIN_LAT_MSB 5
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#define GTHE3_CH_CLK_COR_MIN_LAT_LSB 0
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#define GTHE3_CH_CLK_COR_MIN_LAT_MASK BIT_MASK(GTHE3_CH_CLK_COR_MIN_LAT_MSB, GTHE3_CH_CLK_COR_MIN_LAT_LSB)
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#define GTHE3_CH_CLK_COR_MAX_LAT_ADDR 0x001D
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#define GTHE3_CH_CLK_COR_MAX_LAT_MSB 15
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#define GTHE3_CH_CLK_COR_MAX_LAT_LSB 10
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#define GTHE3_CH_CLK_COR_MAX_LAT_MASK BIT_MASK(GTHE3_CH_CLK_COR_MAX_LAT_MSB, GTHE3_CH_CLK_COR_MAX_LAT_LSB)
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#define GTHE3_CH_CLK_COR_PRECEDENCE_ADDR 0x001D
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#define GTHE3_CH_CLK_COR_PRECEDENCE_MSB 9
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#define GTHE3_CH_CLK_COR_PRECEDENCE_LSB 9
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#define GTHE3_CH_CLK_COR_PRECEDENCE_MASK BIT_MASK(GTHE3_CH_CLK_COR_PRECEDENCE_MSB, GTHE3_CH_CLK_COR_PRECEDENCE_LSB)
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#define GTHE3_CH_CLK_COR_REPEAT_WAIT_ADDR 0x001D
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#define GTHE3_CH_CLK_COR_REPEAT_WAIT_MSB 8
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#define GTHE3_CH_CLK_COR_REPEAT_WAIT_LSB 4
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#define GTHE3_CH_CLK_COR_REPEAT_WAIT_MASK BIT_MASK(GTHE3_CH_CLK_COR_REPEAT_WAIT_MSB, GTHE3_CH_CLK_COR_REPEAT_WAIT_LSB)
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#define GTHE3_CH_CLK_COR_SEQ_LEN_ADDR 0x001D
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#define GTHE3_CH_CLK_COR_SEQ_LEN_MSB 3
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#define GTHE3_CH_CLK_COR_SEQ_LEN_LSB 2
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#define GTHE3_CH_CLK_COR_SEQ_LEN_MASK BIT_MASK(GTHE3_CH_CLK_COR_SEQ_LEN_MSB, GTHE3_CH_CLK_COR_SEQ_LEN_LSB)
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#define GTHE3_CH_CLK_COR_SEQ_LEN_1 0
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#define GTHE3_CH_CLK_COR_SEQ_LEN_2 1
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#define GTHE3_CH_CLK_COR_SEQ_LEN_3 2
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#define GTHE3_CH_CLK_COR_SEQ_LEN_4 3
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#define GTHE3_CH_CHAN_BOND_KEEP_ALIGN_ADDR 0x001D
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#define GTHE3_CH_CHAN_BOND_KEEP_ALIGN_MSB 0
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#define GTHE3_CH_CHAN_BOND_KEEP_ALIGN_LSB 0
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#define GTHE3_CH_CHAN_BOND_KEEP_ALIGN_MASK BIT_MASK(GTHE3_CH_CHAN_BOND_KEEP_ALIGN_MSB, GTHE3_CH_CHAN_BOND_KEEP_ALIGN_LSB)
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#define GTHE3_CH_CLK_COR_SEQ_1_1_ADDR 0x001E
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#define GTHE3_CH_CLK_COR_SEQ_1_1_MSB 9
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#define GTHE3_CH_CLK_COR_SEQ_1_1_LSB 0
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#define GTHE3_CH_CLK_COR_SEQ_1_1_MASK BIT_MASK(GTHE3_CH_CLK_COR_SEQ_1_1_MSB, GTHE3_CH_CLK_COR_SEQ_1_1_LSB)
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#define GTHE3_CH_CLK_COR_SEQ_1_2_ADDR 0x001F
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#define GTHE3_CH_CLK_COR_SEQ_1_2_MSB 9
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#define GTHE3_CH_CLK_COR_SEQ_1_2_LSB 0
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#define GTHE3_CH_CLK_COR_SEQ_1_2_MASK BIT_MASK(GTHE3_CH_CLK_COR_SEQ_1_2_MSB, GTHE3_CH_CLK_COR_SEQ_1_2_LSB)
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#define GTHE3_CH_CLK_COR_SEQ_1_3_ADDR 0x0020
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#define GTHE3_CH_CLK_COR_SEQ_1_3_MSB 9
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#define GTHE3_CH_CLK_COR_SEQ_1_3_LSB 0
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#define GTHE3_CH_CLK_COR_SEQ_1_3_MASK BIT_MASK(GTHE3_CH_CLK_COR_SEQ_1_3_MSB, GTHE3_CH_CLK_COR_SEQ_1_3_LSB)
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#define GTHE3_CH_CLK_COR_SEQ_1_4_ADDR 0x0021
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#define GTHE3_CH_CLK_COR_SEQ_1_4_MSB 9
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#define GTHE3_CH_CLK_COR_SEQ_1_4_LSB 0
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#define GTHE3_CH_CLK_COR_SEQ_1_4_MASK BIT_MASK(GTHE3_CH_CLK_COR_SEQ_1_4_MSB, GTHE3_CH_CLK_COR_SEQ_1_4_LSB)
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#define GTHE3_CH_CLK_COR_SEQ_1_ENABLE_ADDR 0x0022
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#define GTHE3_CH_CLK_COR_SEQ_1_ENABLE_MSB 15
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#define GTHE3_CH_CLK_COR_SEQ_1_ENABLE_LSB 12
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#define GTHE3_CH_CLK_COR_SEQ_1_ENABLE_MASK BIT_MASK(GTHE3_CH_CLK_COR_SEQ_1_ENABLE_MSB, GTHE3_CH_CLK_COR_SEQ_1_ENABLE_LSB)
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#define GTHE3_CH_CLK_COR_SEQ_2_1_ADDR 0x0022
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#define GTHE3_CH_CLK_COR_SEQ_2_1_MSB 9
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#define GTHE3_CH_CLK_COR_SEQ_2_1_LSB 0
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#define GTHE3_CH_CLK_COR_SEQ_2_1_MASK BIT_MASK(GTHE3_CH_CLK_COR_SEQ_2_1_MSB, GTHE3_CH_CLK_COR_SEQ_2_1_LSB)
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#define GTHE3_CH_CLK_COR_SEQ_2_2_ADDR 0x0023
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#define GTHE3_CH_CLK_COR_SEQ_2_2_MSB 9
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#define GTHE3_CH_CLK_COR_SEQ_2_2_LSB 0
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#define GTHE3_CH_CLK_COR_SEQ_2_2_MASK BIT_MASK(GTHE3_CH_CLK_COR_SEQ_2_2_MSB, GTHE3_CH_CLK_COR_SEQ_2_2_LSB)
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#define GTHE3_CH_CLK_COR_SEQ_2_ENABLE_ADDR 0x0024
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#define GTHE3_CH_CLK_COR_SEQ_2_ENABLE_MSB 15
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#define GTHE3_CH_CLK_COR_SEQ_2_ENABLE_LSB 12
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#define GTHE3_CH_CLK_COR_SEQ_2_ENABLE_MASK BIT_MASK(GTHE3_CH_CLK_COR_SEQ_2_ENABLE_MSB, GTHE3_CH_CLK_COR_SEQ_2_ENABLE_LSB)
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#define GTHE3_CH_CLK_COR_SEQ_2_USE_ADDR 0x0024
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#define GTHE3_CH_CLK_COR_SEQ_2_USE_MSB 11
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#define GTHE3_CH_CLK_COR_SEQ_2_USE_LSB 11
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#define GTHE3_CH_CLK_COR_SEQ_2_USE_MASK BIT_MASK(GTHE3_CH_CLK_COR_SEQ_2_USE_MSB, GTHE3_CH_CLK_COR_SEQ_2_USE_LSB)
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#define GTHE3_CH_CLK_CORRECT_USE_ADDR 0x0024
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#define GTHE3_CH_CLK_CORRECT_USE_MSB 10
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#define GTHE3_CH_CLK_CORRECT_USE_LSB 10
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#define GTHE3_CH_CLK_CORRECT_USE_MASK BIT_MASK(GTHE3_CH_CLK_CORRECT_USE_MSB, GTHE3_CH_CLK_CORRECT_USE_LSB)
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#define GTHE3_CH_CLK_COR_SEQ_2_3_ADDR 0x0024
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#define GTHE3_CH_CLK_COR_SEQ_2_3_MSB 9
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#define GTHE3_CH_CLK_COR_SEQ_2_3_LSB 0
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#define GTHE3_CH_CLK_COR_SEQ_2_3_MASK BIT_MASK(GTHE3_CH_CLK_COR_SEQ_2_3_MSB, GTHE3_CH_CLK_COR_SEQ_2_3_LSB)
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#define GTHE3_CH_CLK_COR_SEQ_2_4_ADDR 0x0025
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#define GTHE3_CH_CLK_COR_SEQ_2_4_MSB 9
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#define GTHE3_CH_CLK_COR_SEQ_2_4_LSB 0
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#define GTHE3_CH_CLK_COR_SEQ_2_4_MASK BIT_MASK(GTHE3_CH_CLK_COR_SEQ_2_4_MSB, GTHE3_CH_CLK_COR_SEQ_2_4_LSB)
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#define GTHE3_CH_RXDFE_HE_CFG0_ADDR 0x0026
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#define GTHE3_CH_RXDFE_HE_CFG0_MSB 15
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#define GTHE3_CH_RXDFE_HE_CFG0_LSB 0
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#define GTHE3_CH_RXDFE_HE_CFG0_MASK BIT_MASK(GTHE3_CH_RXDFE_HE_CFG0_MSB, GTHE3_CH_RXDFE_HE_CFG0_LSB)
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#define GTHE3_CH_ALIGN_COMMA_WORD_ADDR 0x0027
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#define GTHE3_CH_ALIGN_COMMA_WORD_MSB 15
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#define GTHE3_CH_ALIGN_COMMA_WORD_LSB 13
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#define GTHE3_CH_ALIGN_COMMA_WORD_MASK BIT_MASK(GTHE3_CH_ALIGN_COMMA_WORD_MSB, GTHE3_CH_ALIGN_COMMA_WORD_LSB)
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#define GTHE3_CH_ALIGN_COMMA_DOUBLE_ADDR 0x0027
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#define GTHE3_CH_ALIGN_COMMA_DOUBLE_MSB 12
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#define GTHE3_CH_ALIGN_COMMA_DOUBLE_LSB 12
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#define GTHE3_CH_ALIGN_COMMA_DOUBLE_MASK BIT_MASK(GTHE3_CH_ALIGN_COMMA_DOUBLE_MSB, GTHE3_CH_ALIGN_COMMA_DOUBLE_LSB)
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#define GTHE3_CH_SHOW_REALIGN_COMMA_ADDR 0x0027
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#define GTHE3_CH_SHOW_REALIGN_COMMA_MSB 11
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#define GTHE3_CH_SHOW_REALIGN_COMMA_LSB 11
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#define GTHE3_CH_SHOW_REALIGN_COMMA_MASK BIT_MASK(GTHE3_CH_SHOW_REALIGN_COMMA_MSB, GTHE3_CH_SHOW_REALIGN_COMMA_LSB)
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#define GTHE3_CH_ALIGN_COMMA_ENABLE_ADDR 0x0027
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#define GTHE3_CH_ALIGN_COMMA_ENABLE_MSB 9
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#define GTHE3_CH_ALIGN_COMMA_ENABLE_LSB 0
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#define GTHE3_CH_ALIGN_COMMA_ENABLE_MASK BIT_MASK(GTHE3_CH_ALIGN_COMMA_ENABLE_MSB, GTHE3_CH_ALIGN_COMMA_ENABLE_LSB)
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#define GTHE3_CH_CPLL_FBDIV_ADDR 0x0028
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#define GTHE3_CH_CPLL_FBDIV_MSB 15
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#define GTHE3_CH_CPLL_FBDIV_LSB 8
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#define GTHE3_CH_CPLL_FBDIV_MASK BIT_MASK(GTHE3_CH_CPLL_FBDIV_MSB, GTHE3_CH_CPLL_FBDIV_LSB)
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#define GTHE3_CH_CPLL_FBDIV_1 16
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#define GTHE3_CH_CPLL_FBDIV_2 0
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#define GTHE3_CH_CPLL_FBDIV_3 1
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#define GTHE3_CH_CPLL_FBDIV_4 2
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#define GTHE3_CH_CPLL_FBDIV_5 3
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#define GTHE3_CH_CPLL_FBDIV_6 5
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#define GTHE3_CH_CPLL_FBDIV_8 6
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#define GTHE3_CH_CPLL_FBDIV_10 7
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#define GTHE3_CH_CPLL_FBDIV_12 13
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#define GTHE3_CH_CPLL_FBDIV_16 14
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#define GTHE3_CH_CPLL_FBDIV_20 15
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#define GTHE3_CH_CPLL_FBDIV_45_ADDR 0x0028
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#define GTHE3_CH_CPLL_FBDIV_45_MSB 7
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#define GTHE3_CH_CPLL_FBDIV_45_LSB 7
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#define GTHE3_CH_CPLL_FBDIV_45_MASK BIT_MASK(GTHE3_CH_CPLL_FBDIV_45_MSB, GTHE3_CH_CPLL_FBDIV_45_LSB)
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#define GTHE3_CH_CPLL_FBDIV_45_4 0
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#define GTHE3_CH_CPLL_FBDIV_45_5 1
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#define GTHE3_CH_TXDRVBIAS_N_ADDR 0x0028
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#define GTHE3_CH_TXDRVBIAS_N_MSB 3
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#define GTHE3_CH_TXDRVBIAS_N_LSB 0
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#define GTHE3_CH_TXDRVBIAS_N_MASK BIT_MASK(GTHE3_CH_TXDRVBIAS_N_MSB, GTHE3_CH_TXDRVBIAS_N_LSB)
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#define GTHE3_CH_CPLL_LOCK_CFG_ADDR 0x0029
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#define GTHE3_CH_CPLL_LOCK_CFG_MSB 15
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#define GTHE3_CH_CPLL_LOCK_CFG_LSB 0
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#define GTHE3_CH_CPLL_LOCK_CFG_MASK BIT_MASK(GTHE3_CH_CPLL_LOCK_CFG_MSB, GTHE3_CH_CPLL_LOCK_CFG_LSB)
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#define GTHE3_CH_CPLL_REFCLK_DIV_ADDR 0x002A
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#define GTHE3_CH_CPLL_REFCLK_DIV_MSB 15
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#define GTHE3_CH_CPLL_REFCLK_DIV_LSB 11
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#define GTHE3_CH_CPLL_REFCLK_DIV_MASK BIT_MASK(GTHE3_CH_CPLL_REFCLK_DIV_MSB, GTHE3_CH_CPLL_REFCLK_DIV_LSB)
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#define GTHE3_CH_CPLL_REFCLK_DIV_1 16
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#define GTHE3_CH_CPLL_REFCLK_DIV_2 0
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#define GTHE3_CH_CPLL_REFCLK_DIV_3 1
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#define GTHE3_CH_CPLL_REFCLK_DIV_4 2
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#define GTHE3_CH_CPLL_REFCLK_DIV_5 3
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#define GTHE3_CH_CPLL_REFCLK_DIV_6 5
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#define GTHE3_CH_CPLL_REFCLK_DIV_8 6
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#define GTHE3_CH_CPLL_REFCLK_DIV_10 7
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#define GTHE3_CH_CPLL_REFCLK_DIV_12 13
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#define GTHE3_CH_CPLL_REFCLK_DIV_16 14
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#define GTHE3_CH_CPLL_REFCLK_DIV_20 15
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#define GTHE3_CH_SATA_CPLL_CFG_ADDR 0x002A
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#define GTHE3_CH_SATA_CPLL_CFG_MSB 6
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#define GTHE3_CH_SATA_CPLL_CFG_LSB 5
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#define GTHE3_CH_SATA_CPLL_CFG_MASK BIT_MASK(GTHE3_CH_SATA_CPLL_CFG_MSB, GTHE3_CH_SATA_CPLL_CFG_LSB)
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#define GTHE3_CH_SATA_CPLL_CFG_VCO_3000MHZ 0
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#define GTHE3_CH_SATA_CPLL_CFG_VCO_1500MHZ 1
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#define GTHE3_CH_SATA_CPLL_CFG_VCO_750MHZ 2
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#define GTHE3_CH_TXDRVBIAS_P_ADDR 0x002A
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#define GTHE3_CH_TXDRVBIAS_P_MSB 3
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#define GTHE3_CH_TXDRVBIAS_P_LSB 0
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#define GTHE3_CH_TXDRVBIAS_P_MASK BIT_MASK(GTHE3_CH_TXDRVBIAS_P_MSB, GTHE3_CH_TXDRVBIAS_P_LSB)
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#define GTHE3_CH_CPLL_INIT_CFG0_ADDR 0x002B
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#define GTHE3_CH_CPLL_INIT_CFG0_MSB 15
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#define GTHE3_CH_CPLL_INIT_CFG0_LSB 0
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#define GTHE3_CH_CPLL_INIT_CFG0_MASK BIT_MASK(GTHE3_CH_CPLL_INIT_CFG0_MSB, GTHE3_CH_CPLL_INIT_CFG0_LSB)
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#define GTHE3_CH_DEC_PCOMMA_DETECT_ADDR 0x002C
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#define GTHE3_CH_DEC_PCOMMA_DETECT_MSB 15
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#define GTHE3_CH_DEC_PCOMMA_DETECT_LSB 15
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#define GTHE3_CH_DEC_PCOMMA_DETECT_MASK BIT_MASK(GTHE3_CH_DEC_PCOMMA_DETECT_MSB, GTHE3_CH_DEC_PCOMMA_DETECT_LSB)
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#define GTHE3_CH_TX_DIVRESET_TIME_ADDR 0x002C
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#define GTHE3_CH_TX_DIVRESET_TIME_MSB 11
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#define GTHE3_CH_TX_DIVRESET_TIME_LSB 7
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#define GTHE3_CH_TX_DIVRESET_TIME_MASK BIT_MASK(GTHE3_CH_TX_DIVRESET_TIME_MSB, GTHE3_CH_TX_DIVRESET_TIME_LSB)
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#define GTHE3_CH_RX_DIVRESET_TIME_ADDR 0x002C
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#define GTHE3_CH_RX_DIVRESET_TIME_MSB 6
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#define GTHE3_CH_RX_DIVRESET_TIME_LSB 2
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#define GTHE3_CH_RX_DIVRESET_TIME_MASK BIT_MASK(GTHE3_CH_RX_DIVRESET_TIME_MSB, GTHE3_CH_RX_DIVRESET_TIME_LSB)
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#define GTHE3_CH_A_TXPROGDIVRESET_ADDR 0x002C
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#define GTHE3_CH_A_TXPROGDIVRESET_MSB 1
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#define GTHE3_CH_A_TXPROGDIVRESET_LSB 1
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#define GTHE3_CH_A_TXPROGDIVRESET_MASK BIT_MASK(GTHE3_CH_A_TXPROGDIVRESET_MSB, GTHE3_CH_A_TXPROGDIVRESET_LSB)
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#define GTHE3_CH_A_RXPROGDIVRESET_ADDR 0x002C
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#define GTHE3_CH_A_RXPROGDIVRESET_MSB 0
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#define GTHE3_CH_A_RXPROGDIVRESET_LSB 0
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#define GTHE3_CH_A_RXPROGDIVRESET_MASK BIT_MASK(GTHE3_CH_A_RXPROGDIVRESET_MSB, GTHE3_CH_A_RXPROGDIVRESET_LSB)
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#define GTHE3_CH_RXCDR_LOCK_CFG1_ADDR 0x002D
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#define GTHE3_CH_RXCDR_LOCK_CFG1_MSB 15
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#define GTHE3_CH_RXCDR_LOCK_CFG1_LSB 0
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#define GTHE3_CH_RXCDR_LOCK_CFG1_MASK BIT_MASK(GTHE3_CH_RXCDR_LOCK_CFG1_MSB, GTHE3_CH_RXCDR_LOCK_CFG1_LSB)
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#define GTHE3_CH_RXCFOK_CFG1_ADDR 0x002E
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#define GTHE3_CH_RXCFOK_CFG1_MSB 15
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#define GTHE3_CH_RXCFOK_CFG1_LSB 0
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#define GTHE3_CH_RXCFOK_CFG1_MASK BIT_MASK(GTHE3_CH_RXCFOK_CFG1_MSB, GTHE3_CH_RXCFOK_CFG1_LSB)
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#define GTHE3_CH_RXDFE_H2_CFG0_ADDR 0x002F
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#define GTHE3_CH_RXDFE_H2_CFG0_MSB 15
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#define GTHE3_CH_RXDFE_H2_CFG0_LSB 0
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#define GTHE3_CH_RXDFE_H2_CFG0_MASK BIT_MASK(GTHE3_CH_RXDFE_H2_CFG0_MSB, GTHE3_CH_RXDFE_H2_CFG0_LSB)
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#define GTHE3_CH_RXDFE_H2_CFG1_ADDR 0x0030
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#define GTHE3_CH_RXDFE_H2_CFG1_MSB 15
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#define GTHE3_CH_RXDFE_H2_CFG1_LSB 0
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#define GTHE3_CH_RXDFE_H2_CFG1_MASK BIT_MASK(GTHE3_CH_RXDFE_H2_CFG1_MSB, GTHE3_CH_RXDFE_H2_CFG1_LSB)
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#define GTHE3_CH_RXCFOK_CFG2_ADDR 0x0031
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#define GTHE3_CH_RXCFOK_CFG2_MSB 15
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#define GTHE3_CH_RXCFOK_CFG2_LSB 0
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#define GTHE3_CH_RXCFOK_CFG2_MASK BIT_MASK(GTHE3_CH_RXCFOK_CFG2_MSB, GTHE3_CH_RXCFOK_CFG2_LSB)
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#define GTHE3_CH_RXLPM_CFG_ADDR 0x0032
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#define GTHE3_CH_RXLPM_CFG_MSB 15
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#define GTHE3_CH_RXLPM_CFG_LSB 0
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#define GTHE3_CH_RXLPM_CFG_MASK BIT_MASK(GTHE3_CH_RXLPM_CFG_MSB, GTHE3_CH_RXLPM_CFG_LSB)
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#define GTHE3_CH_RXLPM_KH_CFG0_ADDR 0x0033
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#define GTHE3_CH_RXLPM_KH_CFG0_MSB 15
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#define GTHE3_CH_RXLPM_KH_CFG0_LSB 0
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#define GTHE3_CH_RXLPM_KH_CFG0_MASK BIT_MASK(GTHE3_CH_RXLPM_KH_CFG0_MSB, GTHE3_CH_RXLPM_KH_CFG0_LSB)
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#define GTHE3_CH_RXLPM_KH_CFG1_ADDR 0x0034
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#define GTHE3_CH_RXLPM_KH_CFG1_MSB 15
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#define GTHE3_CH_RXLPM_KH_CFG1_LSB 0
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#define GTHE3_CH_RXLPM_KH_CFG1_MASK BIT_MASK(GTHE3_CH_RXLPM_KH_CFG1_MSB, GTHE3_CH_RXLPM_KH_CFG1_LSB)
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#define GTHE3_CH_RXDFELPM_KL_CFG0_ADDR 0x0035
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#define GTHE3_CH_RXDFELPM_KL_CFG0_MSB 15
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#define GTHE3_CH_RXDFELPM_KL_CFG0_LSB 0
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#define GTHE3_CH_RXDFELPM_KL_CFG0_MASK BIT_MASK(GTHE3_CH_RXDFELPM_KL_CFG0_MSB, GTHE3_CH_RXDFELPM_KL_CFG0_LSB)
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#define GTHE3_CH_RXDFELPM_KL_CFG1_ADDR 0x0036
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#define GTHE3_CH_RXDFELPM_KL_CFG1_MSB 15
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#define GTHE3_CH_RXDFELPM_KL_CFG1_LSB 0
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#define GTHE3_CH_RXDFELPM_KL_CFG1_MASK BIT_MASK(GTHE3_CH_RXDFELPM_KL_CFG1_MSB, GTHE3_CH_RXDFELPM_KL_CFG1_LSB)
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#define GTHE3_CH_RXLPM_OS_CFG0_ADDR 0x0037
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#define GTHE3_CH_RXLPM_OS_CFG0_MSB 15
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#define GTHE3_CH_RXLPM_OS_CFG0_LSB 0
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#define GTHE3_CH_RXLPM_OS_CFG0_MASK BIT_MASK(GTHE3_CH_RXLPM_OS_CFG0_MSB, GTHE3_CH_RXLPM_OS_CFG0_LSB)
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#define GTHE3_CH_RXLPM_OS_CFG1_ADDR 0x0038
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#define GTHE3_CH_RXLPM_OS_CFG1_MSB 15
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#define GTHE3_CH_RXLPM_OS_CFG1_LSB 0
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#define GTHE3_CH_RXLPM_OS_CFG1_MASK BIT_MASK(GTHE3_CH_RXLPM_OS_CFG1_MSB, GTHE3_CH_RXLPM_OS_CFG1_LSB)
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#define GTHE3_CH_RXLPM_GC_CFG_ADDR 0x0039
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#define GTHE3_CH_RXLPM_GC_CFG_MSB 15
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#define GTHE3_CH_RXLPM_GC_CFG_LSB 0
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#define GTHE3_CH_RXLPM_GC_CFG_MASK BIT_MASK(GTHE3_CH_RXLPM_GC_CFG_MSB, GTHE3_CH_RXLPM_GC_CFG_LSB)
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#define GTHE3_CH_DMONITOR_CFG1_ADDR 0x003A
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#define GTHE3_CH_DMONITOR_CFG1_MSB 15
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#define GTHE3_CH_DMONITOR_CFG1_LSB 8
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#define GTHE3_CH_DMONITOR_CFG1_MASK BIT_MASK(GTHE3_CH_DMONITOR_CFG1_MSB, GTHE3_CH_DMONITOR_CFG1_LSB)
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#define GTHE3_CH_ES_CONTROL_ADDR 0x003C
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#define GTHE3_CH_ES_CONTROL_MSB 15
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#define GTHE3_CH_ES_CONTROL_LSB 10
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#define GTHE3_CH_ES_CONTROL_MASK BIT_MASK(GTHE3_CH_ES_CONTROL_MSB, GTHE3_CH_ES_CONTROL_LSB)
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#define GTHE3_CH_ES_ERRDET_EN_ADDR 0x003C
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#define GTHE3_CH_ES_ERRDET_EN_MSB 9
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#define GTHE3_CH_ES_ERRDET_EN_LSB 9
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#define GTHE3_CH_ES_ERRDET_EN_MASK BIT_MASK(GTHE3_CH_ES_ERRDET_EN_MSB, GTHE3_CH_ES_ERRDET_EN_LSB)
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#define GTHE3_CH_ES_EYE_SCAN_EN_ADDR 0x003C
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#define GTHE3_CH_ES_EYE_SCAN_EN_MSB 8
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#define GTHE3_CH_ES_EYE_SCAN_EN_LSB 8
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#define GTHE3_CH_ES_EYE_SCAN_EN_MASK BIT_MASK(GTHE3_CH_ES_EYE_SCAN_EN_MSB, GTHE3_CH_ES_EYE_SCAN_EN_LSB)
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#define GTHE3_CH_ES_PRESCALE_ADDR 0x003C
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#define GTHE3_CH_ES_PRESCALE_MSB 4
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#define GTHE3_CH_ES_PRESCALE_LSB 0
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#define GTHE3_CH_ES_PRESCALE_MASK BIT_MASK(GTHE3_CH_ES_PRESCALE_MSB, GTHE3_CH_ES_PRESCALE_LSB)
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#define GTHE3_CH_RXDFE_HC_CFG0_ADDR 0x003D
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#define GTHE3_CH_RXDFE_HC_CFG0_MSB 15
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#define GTHE3_CH_RXDFE_HC_CFG0_LSB 0
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#define GTHE3_CH_RXDFE_HC_CFG0_MASK BIT_MASK(GTHE3_CH_RXDFE_HC_CFG0_MSB, GTHE3_CH_RXDFE_HC_CFG0_LSB)
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#define GTHE3_CH_TX_PROGDIV_CFG_ADDR 0x003E
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#define GTHE3_CH_TX_PROGDIV_CFG_MSB 15
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#define GTHE3_CH_TX_PROGDIV_CFG_LSB 0
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#define GTHE3_CH_TX_PROGDIV_CFG_MASK BIT_MASK(GTHE3_CH_TX_PROGDIV_CFG_MSB, GTHE3_CH_TX_PROGDIV_CFG_LSB)
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#define GTHE3_CH_TX_PROGDIV_CFG_0 32768
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#define GTHE3_CH_TX_PROGDIV_CFG_4 57744
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#define GTHE3_CH_TX_PROGDIV_CFG_5 49648
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#define GTHE3_CH_TX_PROGDIV_CFG_8 57728
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#define GTHE3_CH_TX_PROGDIV_CFG_10 57760
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#define GTHE3_CH_TX_PROGDIV_CFG_16 57730
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#define GTHE3_CH_TX_PROGDIV_CFG_16P5 49672
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#define GTHE3_CH_TX_PROGDIV_CFG_20 57762
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#define GTHE3_CH_TX_PROGDIV_CFG_32 57734
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#define GTHE3_CH_TX_PROGDIV_CFG_33 49800
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#define GTHE3_CH_TX_PROGDIV_CFG_40 57766
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#define GTHE3_CH_TX_PROGDIV_CFG_64 57742
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#define GTHE3_CH_TX_PROGDIV_CFG_66 50056
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#define GTHE3_CH_TX_PROGDIV_CFG_80 57743
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#define GTHE3_CH_TX_PROGDIV_CFG_100 57775
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#define GTHE3_CH_ES_QUALIFIER0_ADDR 0x003F
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#define GTHE3_CH_ES_QUALIFIER0_MSB 15
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#define GTHE3_CH_ES_QUALIFIER0_LSB 0
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#define GTHE3_CH_ES_QUALIFIER0_MASK BIT_MASK(GTHE3_CH_ES_QUALIFIER0_MSB, GTHE3_CH_ES_QUALIFIER0_LSB)
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#define GTHE3_CH_ES_QUALIFIER1_ADDR 0x0040
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#define GTHE3_CH_ES_QUALIFIER1_MSB 15
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#define GTHE3_CH_ES_QUALIFIER1_LSB 0
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#define GTHE3_CH_ES_QUALIFIER1_MASK BIT_MASK(GTHE3_CH_ES_QUALIFIER1_MSB, GTHE3_CH_ES_QUALIFIER1_LSB)
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#define GTHE3_CH_ES_QUALIFIER2_ADDR 0x0041
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#define GTHE3_CH_ES_QUALIFIER2_MSB 15
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#define GTHE3_CH_ES_QUALIFIER2_LSB 0
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#define GTHE3_CH_ES_QUALIFIER2_MASK BIT_MASK(GTHE3_CH_ES_QUALIFIER2_MSB, GTHE3_CH_ES_QUALIFIER2_LSB)
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#define GTHE3_CH_ES_QUALIFIER3_ADDR 0x0042
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#define GTHE3_CH_ES_QUALIFIER3_MSB 15
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#define GTHE3_CH_ES_QUALIFIER3_LSB 0
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#define GTHE3_CH_ES_QUALIFIER3_MASK BIT_MASK(GTHE3_CH_ES_QUALIFIER3_MSB, GTHE3_CH_ES_QUALIFIER3_LSB)
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#define GTHE3_CH_ES_QUALIFIER4_ADDR 0x0043
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#define GTHE3_CH_ES_QUALIFIER4_MSB 15
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#define GTHE3_CH_ES_QUALIFIER4_LSB 0
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#define GTHE3_CH_ES_QUALIFIER4_MASK BIT_MASK(GTHE3_CH_ES_QUALIFIER4_MSB, GTHE3_CH_ES_QUALIFIER4_LSB)
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#define GTHE3_CH_ES_QUAL_MASK0_ADDR 0x0044
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#define GTHE3_CH_ES_QUAL_MASK0_MSB 15
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#define GTHE3_CH_ES_QUAL_MASK0_LSB 0
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#define GTHE3_CH_ES_QUAL_MASK0_MASK BIT_MASK(GTHE3_CH_ES_QUAL_MASK0_MSB, GTHE3_CH_ES_QUAL_MASK0_LSB)
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#define GTHE3_CH_ES_QUAL_MASK1_ADDR 0x0045
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#define GTHE3_CH_ES_QUAL_MASK1_MSB 15
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#define GTHE3_CH_ES_QUAL_MASK1_LSB 0
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#define GTHE3_CH_ES_QUAL_MASK1_MASK BIT_MASK(GTHE3_CH_ES_QUAL_MASK1_MSB, GTHE3_CH_ES_QUAL_MASK1_LSB)
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#define GTHE3_CH_ES_QUAL_MASK2_ADDR 0x0046
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#define GTHE3_CH_ES_QUAL_MASK2_MSB 15
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#define GTHE3_CH_ES_QUAL_MASK2_LSB 0
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#define GTHE3_CH_ES_QUAL_MASK2_MASK BIT_MASK(GTHE3_CH_ES_QUAL_MASK2_MSB, GTHE3_CH_ES_QUAL_MASK2_LSB)
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#define GTHE3_CH_ES_QUAL_MASK3_ADDR 0x0047
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#define GTHE3_CH_ES_QUAL_MASK3_MSB 15
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#define GTHE3_CH_ES_QUAL_MASK3_LSB 0
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#define GTHE3_CH_ES_QUAL_MASK3_MASK BIT_MASK(GTHE3_CH_ES_QUAL_MASK3_MSB, GTHE3_CH_ES_QUAL_MASK3_LSB)
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#define GTHE3_CH_ES_QUAL_MASK4_ADDR 0x0048
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#define GTHE3_CH_ES_QUAL_MASK4_MSB 15
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#define GTHE3_CH_ES_QUAL_MASK4_LSB 0
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#define GTHE3_CH_ES_QUAL_MASK4_MASK BIT_MASK(GTHE3_CH_ES_QUAL_MASK4_MSB, GTHE3_CH_ES_QUAL_MASK4_LSB)
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#define GTHE3_CH_ES_SDATA_MASK0_ADDR 0x0049
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#define GTHE3_CH_ES_SDATA_MASK0_MSB 15
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#define GTHE3_CH_ES_SDATA_MASK0_LSB 0
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#define GTHE3_CH_ES_SDATA_MASK0_MASK BIT_MASK(GTHE3_CH_ES_SDATA_MASK0_MSB, GTHE3_CH_ES_SDATA_MASK0_LSB)
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#define GTHE3_CH_ES_SDATA_MASK1_ADDR 0x004A
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#define GTHE3_CH_ES_SDATA_MASK1_MSB 15
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#define GTHE3_CH_ES_SDATA_MASK1_LSB 0
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#define GTHE3_CH_ES_SDATA_MASK1_MASK BIT_MASK(GTHE3_CH_ES_SDATA_MASK1_MSB, GTHE3_CH_ES_SDATA_MASK1_LSB)
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#define GTHE3_CH_ES_SDATA_MASK2_ADDR 0x004B
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#define GTHE3_CH_ES_SDATA_MASK2_MSB 15
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#define GTHE3_CH_ES_SDATA_MASK2_LSB 0
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#define GTHE3_CH_ES_SDATA_MASK2_MASK BIT_MASK(GTHE3_CH_ES_SDATA_MASK2_MSB, GTHE3_CH_ES_SDATA_MASK2_LSB)
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#define GTHE3_CH_ES_SDATA_MASK3_ADDR 0x004C
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#define GTHE3_CH_ES_SDATA_MASK3_MSB 15
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#define GTHE3_CH_ES_SDATA_MASK3_LSB 0
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#define GTHE3_CH_ES_SDATA_MASK3_MASK BIT_MASK(GTHE3_CH_ES_SDATA_MASK3_MSB, GTHE3_CH_ES_SDATA_MASK3_LSB)
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#define GTHE3_CH_ES_SDATA_MASK4_ADDR 0x004D
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#define GTHE3_CH_ES_SDATA_MASK4_MSB 15
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#define GTHE3_CH_ES_SDATA_MASK4_LSB 0
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#define GTHE3_CH_ES_SDATA_MASK4_MASK BIT_MASK(GTHE3_CH_ES_SDATA_MASK4_MSB, GTHE3_CH_ES_SDATA_MASK4_LSB)
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#define GTHE3_CH_FTS_LANE_DESKEW_EN_ADDR 0x004E
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#define GTHE3_CH_FTS_LANE_DESKEW_EN_MSB 4
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#define GTHE3_CH_FTS_LANE_DESKEW_EN_LSB 4
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#define GTHE3_CH_FTS_LANE_DESKEW_EN_MASK BIT_MASK(GTHE3_CH_FTS_LANE_DESKEW_EN_MSB, GTHE3_CH_FTS_LANE_DESKEW_EN_LSB)
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#define GTHE3_CH_FTS_DESKEW_SEQ_ENABLE_ADDR 0x004E
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#define GTHE3_CH_FTS_DESKEW_SEQ_ENABLE_MSB 3
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#define GTHE3_CH_FTS_DESKEW_SEQ_ENABLE_LSB 0
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#define GTHE3_CH_FTS_DESKEW_SEQ_ENABLE_MASK BIT_MASK(GTHE3_CH_FTS_DESKEW_SEQ_ENABLE_MSB, GTHE3_CH_FTS_DESKEW_SEQ_ENABLE_LSB)
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#define GTHE3_CH_ES_HORZ_OFFSET_ADDR 0x004F
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#define GTHE3_CH_ES_HORZ_OFFSET_MSB 15
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#define GTHE3_CH_ES_HORZ_OFFSET_LSB 4
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#define GTHE3_CH_ES_HORZ_OFFSET_MASK BIT_MASK(GTHE3_CH_ES_HORZ_OFFSET_MSB, GTHE3_CH_ES_HORZ_OFFSET_LSB)
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#define GTHE3_CH_FTS_LANE_DESKEW_CFG_ADDR 0x004F
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#define GTHE3_CH_FTS_LANE_DESKEW_CFG_MSB 3
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#define GTHE3_CH_FTS_LANE_DESKEW_CFG_LSB 0
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#define GTHE3_CH_FTS_LANE_DESKEW_CFG_MASK BIT_MASK(GTHE3_CH_FTS_LANE_DESKEW_CFG_MSB, GTHE3_CH_FTS_LANE_DESKEW_CFG_LSB)
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#define GTHE3_CH_RXDFE_HC_CFG1_ADDR 0x0050
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#define GTHE3_CH_RXDFE_HC_CFG1_MSB 15
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#define GTHE3_CH_RXDFE_HC_CFG1_LSB 0
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#define GTHE3_CH_RXDFE_HC_CFG1_MASK BIT_MASK(GTHE3_CH_RXDFE_HC_CFG1_MSB, GTHE3_CH_RXDFE_HC_CFG1_LSB)
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#define GTHE3_CH_ES_PMA_CFG_ADDR 0x0051
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#define GTHE3_CH_ES_PMA_CFG_MSB 9
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#define GTHE3_CH_ES_PMA_CFG_LSB 0
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#define GTHE3_CH_ES_PMA_CFG_MASK BIT_MASK(GTHE3_CH_ES_PMA_CFG_MSB, GTHE3_CH_ES_PMA_CFG_LSB)
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#define GTHE3_CH_RX_EN_HI_LR_ADDR 0x0052
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#define GTHE3_CH_RX_EN_HI_LR_MSB 10
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#define GTHE3_CH_RX_EN_HI_LR_LSB 10
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#define GTHE3_CH_RX_EN_HI_LR_MASK BIT_MASK(GTHE3_CH_RX_EN_HI_LR_MSB, GTHE3_CH_RX_EN_HI_LR_LSB)
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#define GTHE3_CH_RX_DFE_AGC_CFG1_ADDR 0x0052
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#define GTHE3_CH_RX_DFE_AGC_CFG1_MSB 4
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#define GTHE3_CH_RX_DFE_AGC_CFG1_LSB 2
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#define GTHE3_CH_RX_DFE_AGC_CFG1_MASK BIT_MASK(GTHE3_CH_RX_DFE_AGC_CFG1_MSB, GTHE3_CH_RX_DFE_AGC_CFG1_LSB)
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#define GTHE3_CH_RX_DFE_AGC_CFG0_ADDR 0x0052
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#define GTHE3_CH_RX_DFE_AGC_CFG0_MSB 1
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#define GTHE3_CH_RX_DFE_AGC_CFG0_LSB 0
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#define GTHE3_CH_RX_DFE_AGC_CFG0_MASK BIT_MASK(GTHE3_CH_RX_DFE_AGC_CFG0_MSB, GTHE3_CH_RX_DFE_AGC_CFG0_LSB)
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#define GTHE3_CH_RXDFE_CFG0_ADDR 0x0053
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#define GTHE3_CH_RXDFE_CFG0_MSB 15
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#define GTHE3_CH_RXDFE_CFG0_LSB 0
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#define GTHE3_CH_RXDFE_CFG0_MASK BIT_MASK(GTHE3_CH_RXDFE_CFG0_MSB, GTHE3_CH_RXDFE_CFG0_LSB)
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#define GTHE3_CH_RXDFE_CFG1_ADDR 0x0054
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#define GTHE3_CH_RXDFE_CFG1_MSB 15
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#define GTHE3_CH_RXDFE_CFG1_LSB 0
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#define GTHE3_CH_RXDFE_CFG1_MASK BIT_MASK(GTHE3_CH_RXDFE_CFG1_MSB, GTHE3_CH_RXDFE_CFG1_LSB)
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#define GTHE3_CH_LOCAL_MASTER_ADDR 0x0055
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#define GTHE3_CH_LOCAL_MASTER_MSB 13
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#define GTHE3_CH_LOCAL_MASTER_LSB 13
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#define GTHE3_CH_LOCAL_MASTER_MASK BIT_MASK(GTHE3_CH_LOCAL_MASTER_MSB, GTHE3_CH_LOCAL_MASTER_LSB)
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#define GTHE3_CH_PCS_PCIE_EN_ADDR 0x0055
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#define GTHE3_CH_PCS_PCIE_EN_MSB 12
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#define GTHE3_CH_PCS_PCIE_EN_LSB 12
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#define GTHE3_CH_PCS_PCIE_EN_MASK BIT_MASK(GTHE3_CH_PCS_PCIE_EN_MSB, GTHE3_CH_PCS_PCIE_EN_LSB)
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#define GTHE3_CH_ALIGN_MCOMMA_DET_ADDR 0x0055
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#define GTHE3_CH_ALIGN_MCOMMA_DET_MSB 10
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#define GTHE3_CH_ALIGN_MCOMMA_DET_LSB 10
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#define GTHE3_CH_ALIGN_MCOMMA_DET_MASK BIT_MASK(GTHE3_CH_ALIGN_MCOMMA_DET_MSB, GTHE3_CH_ALIGN_MCOMMA_DET_LSB)
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#define GTHE3_CH_ALIGN_MCOMMA_VALUE_ADDR 0x0055
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#define GTHE3_CH_ALIGN_MCOMMA_VALUE_MSB 9
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#define GTHE3_CH_ALIGN_MCOMMA_VALUE_LSB 0
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#define GTHE3_CH_ALIGN_MCOMMA_VALUE_MASK BIT_MASK(GTHE3_CH_ALIGN_MCOMMA_VALUE_MSB, GTHE3_CH_ALIGN_MCOMMA_VALUE_LSB)
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#define GTHE3_CH_ALIGN_PCOMMA_DET_ADDR 0x0056
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#define GTHE3_CH_ALIGN_PCOMMA_DET_MSB 10
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#define GTHE3_CH_ALIGN_PCOMMA_DET_LSB 10
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#define GTHE3_CH_ALIGN_PCOMMA_DET_MASK BIT_MASK(GTHE3_CH_ALIGN_PCOMMA_DET_MSB, GTHE3_CH_ALIGN_PCOMMA_DET_LSB)
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#define GTHE3_CH_ALIGN_PCOMMA_VALUE_ADDR 0x0056
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#define GTHE3_CH_ALIGN_PCOMMA_VALUE_MSB 9
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#define GTHE3_CH_ALIGN_PCOMMA_VALUE_LSB 0
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#define GTHE3_CH_ALIGN_PCOMMA_VALUE_MASK BIT_MASK(GTHE3_CH_ALIGN_PCOMMA_VALUE_MSB, GTHE3_CH_ALIGN_PCOMMA_VALUE_LSB)
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#define GTHE3_CH_TXDLY_LCFG_ADDR 0x0057
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#define GTHE3_CH_TXDLY_LCFG_MSB 15
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#define GTHE3_CH_TXDLY_LCFG_LSB 0
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#define GTHE3_CH_TXDLY_LCFG_MASK BIT_MASK(GTHE3_CH_TXDLY_LCFG_MSB, GTHE3_CH_TXDLY_LCFG_LSB)
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#define GTHE3_CH_RXDFE_OS_CFG0_ADDR 0x0058
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#define GTHE3_CH_RXDFE_OS_CFG0_MSB 15
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#define GTHE3_CH_RXDFE_OS_CFG0_LSB 0
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#define GTHE3_CH_RXDFE_OS_CFG0_MASK BIT_MASK(GTHE3_CH_RXDFE_OS_CFG0_MSB, GTHE3_CH_RXDFE_OS_CFG0_LSB)
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#define GTHE3_CH_RXPHDLY_CFG_ADDR 0x0059
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#define GTHE3_CH_RXPHDLY_CFG_MSB 15
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#define GTHE3_CH_RXPHDLY_CFG_LSB 0
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#define GTHE3_CH_RXPHDLY_CFG_MASK BIT_MASK(GTHE3_CH_RXPHDLY_CFG_MSB, GTHE3_CH_RXPHDLY_CFG_LSB)
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#define GTHE3_CH_RXDFE_OS_CFG1_ADDR 0x005A
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#define GTHE3_CH_RXDFE_OS_CFG1_MSB 15
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#define GTHE3_CH_RXDFE_OS_CFG1_LSB 0
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#define GTHE3_CH_RXDFE_OS_CFG1_MASK BIT_MASK(GTHE3_CH_RXDFE_OS_CFG1_MSB, GTHE3_CH_RXDFE_OS_CFG1_LSB)
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#define GTHE3_CH_RXDLY_CFG_ADDR 0x005B
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#define GTHE3_CH_RXDLY_CFG_MSB 15
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#define GTHE3_CH_RXDLY_CFG_LSB 0
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#define GTHE3_CH_RXDLY_CFG_MASK BIT_MASK(GTHE3_CH_RXDLY_CFG_MSB, GTHE3_CH_RXDLY_CFG_LSB)
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#define GTHE3_CH_RXDLY_LCFG_ADDR 0x005C
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#define GTHE3_CH_RXDLY_LCFG_MSB 15
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#define GTHE3_CH_RXDLY_LCFG_LSB 0
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#define GTHE3_CH_RXDLY_LCFG_MASK BIT_MASK(GTHE3_CH_RXDLY_LCFG_MSB, GTHE3_CH_RXDLY_LCFG_LSB)
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#define GTHE3_CH_RXDFE_HF_CFG0_ADDR 0x005D
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#define GTHE3_CH_RXDFE_HF_CFG0_MSB 15
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#define GTHE3_CH_RXDFE_HF_CFG0_LSB 0
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#define GTHE3_CH_RXDFE_HF_CFG0_MASK BIT_MASK(GTHE3_CH_RXDFE_HF_CFG0_MSB, GTHE3_CH_RXDFE_HF_CFG0_LSB)
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#define GTHE3_CH_RXDFE_HD_CFG0_ADDR 0x005E
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#define GTHE3_CH_RXDFE_HD_CFG0_MSB 15
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#define GTHE3_CH_RXDFE_HD_CFG0_LSB 0
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#define GTHE3_CH_RXDFE_HD_CFG0_MASK BIT_MASK(GTHE3_CH_RXDFE_HD_CFG0_MSB, GTHE3_CH_RXDFE_HD_CFG0_LSB)
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#define GTHE3_CH_RX_BIAS_CFG0_ADDR 0x005F
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#define GTHE3_CH_RX_BIAS_CFG0_MSB 15
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#define GTHE3_CH_RX_BIAS_CFG0_LSB 0
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#define GTHE3_CH_RX_BIAS_CFG0_MASK BIT_MASK(GTHE3_CH_RX_BIAS_CFG0_MSB, GTHE3_CH_RX_BIAS_CFG0_LSB)
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#define GTHE3_CH_PCS_RSVD0_ADDR 0x0060
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#define GTHE3_CH_PCS_RSVD0_MSB 15
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#define GTHE3_CH_PCS_RSVD0_LSB 0
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#define GTHE3_CH_PCS_RSVD0_MASK BIT_MASK(GTHE3_CH_PCS_RSVD0_MSB, GTHE3_CH_PCS_RSVD0_LSB)
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#define GTHE3_CH_RXPH_MONITOR_SEL_ADDR 0x0061
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#define GTHE3_CH_RXPH_MONITOR_SEL_MSB 15
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#define GTHE3_CH_RXPH_MONITOR_SEL_LSB 11
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#define GTHE3_CH_RXPH_MONITOR_SEL_MASK BIT_MASK(GTHE3_CH_RXPH_MONITOR_SEL_MSB, GTHE3_CH_RXPH_MONITOR_SEL_LSB)
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#define GTHE3_CH_RX_CM_BUF_PD_ADDR 0x0061
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#define GTHE3_CH_RX_CM_BUF_PD_MSB 10
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#define GTHE3_CH_RX_CM_BUF_PD_LSB 10
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#define GTHE3_CH_RX_CM_BUF_PD_MASK BIT_MASK(GTHE3_CH_RX_CM_BUF_PD_MSB, GTHE3_CH_RX_CM_BUF_PD_LSB)
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#define GTHE3_CH_RX_CM_BUF_CFG_ADDR 0x0061
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#define GTHE3_CH_RX_CM_BUF_CFG_MSB 9
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#define GTHE3_CH_RX_CM_BUF_CFG_LSB 6
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#define GTHE3_CH_RX_CM_BUF_CFG_MASK BIT_MASK(GTHE3_CH_RX_CM_BUF_CFG_MSB, GTHE3_CH_RX_CM_BUF_CFG_LSB)
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#define GTHE3_CH_RX_CM_TRIM_ADDR 0x0061
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#define GTHE3_CH_RX_CM_TRIM_MSB 5
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#define GTHE3_CH_RX_CM_TRIM_LSB 2
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#define GTHE3_CH_RX_CM_TRIM_MASK BIT_MASK(GTHE3_CH_RX_CM_TRIM_MSB, GTHE3_CH_RX_CM_TRIM_LSB)
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#define GTHE3_CH_RX_CM_SEL_ADDR 0x0061
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#define GTHE3_CH_RX_CM_SEL_MSB 1
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#define GTHE3_CH_RX_CM_SEL_LSB 0
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#define GTHE3_CH_RX_CM_SEL_MASK BIT_MASK(GTHE3_CH_RX_CM_SEL_MSB, GTHE3_CH_RX_CM_SEL_LSB)
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#define GTHE3_CH_RX_SUM_DFETAPREP_EN_ADDR 0x0062
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#define GTHE3_CH_RX_SUM_DFETAPREP_EN_MSB 14
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#define GTHE3_CH_RX_SUM_DFETAPREP_EN_LSB 14
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#define GTHE3_CH_RX_SUM_DFETAPREP_EN_MASK BIT_MASK(GTHE3_CH_RX_SUM_DFETAPREP_EN_MSB, GTHE3_CH_RX_SUM_DFETAPREP_EN_LSB)
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#define GTHE3_CH_RX_SUM_VCM_OVWR_ADDR 0x0062
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#define GTHE3_CH_RX_SUM_VCM_OVWR_MSB 13
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#define GTHE3_CH_RX_SUM_VCM_OVWR_LSB 13
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#define GTHE3_CH_RX_SUM_VCM_OVWR_MASK BIT_MASK(GTHE3_CH_RX_SUM_VCM_OVWR_MSB, GTHE3_CH_RX_SUM_VCM_OVWR_LSB)
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#define GTHE3_CH_RX_SUM_IREF_TUNE_ADDR 0x0062
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#define GTHE3_CH_RX_SUM_IREF_TUNE_MSB 12
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#define GTHE3_CH_RX_SUM_IREF_TUNE_LSB 9
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#define GTHE3_CH_RX_SUM_IREF_TUNE_MASK BIT_MASK(GTHE3_CH_RX_SUM_IREF_TUNE_MSB, GTHE3_CH_RX_SUM_IREF_TUNE_LSB)
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#define GTHE3_CH_RX_SUM_RES_CTRL_ADDR 0x0062
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#define GTHE3_CH_RX_SUM_RES_CTRL_MSB 8
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#define GTHE3_CH_RX_SUM_RES_CTRL_LSB 7
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#define GTHE3_CH_RX_SUM_RES_CTRL_MASK BIT_MASK(GTHE3_CH_RX_SUM_RES_CTRL_MSB, GTHE3_CH_RX_SUM_RES_CTRL_LSB)
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#define GTHE3_CH_RX_SUM_VCMTUNE_ADDR 0x0062
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#define GTHE3_CH_RX_SUM_VCMTUNE_MSB 6
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#define GTHE3_CH_RX_SUM_VCMTUNE_LSB 3
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#define GTHE3_CH_RX_SUM_VCMTUNE_MASK BIT_MASK(GTHE3_CH_RX_SUM_VCMTUNE_MSB, GTHE3_CH_RX_SUM_VCMTUNE_LSB)
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#define GTHE3_CH_RX_SUM_VREF_TUNE_ADDR 0x0062
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#define GTHE3_CH_RX_SUM_VREF_TUNE_MSB 2
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#define GTHE3_CH_RX_SUM_VREF_TUNE_LSB 0
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#define GTHE3_CH_RX_SUM_VREF_TUNE_MASK BIT_MASK(GTHE3_CH_RX_SUM_VREF_TUNE_MSB, GTHE3_CH_RX_SUM_VREF_TUNE_LSB)
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#define GTHE3_CH_CBCC_DATA_SOURCE_SEL_ADDR 0x0063
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#define GTHE3_CH_CBCC_DATA_SOURCE_SEL_MSB 15
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#define GTHE3_CH_CBCC_DATA_SOURCE_SEL_LSB 15
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#define GTHE3_CH_CBCC_DATA_SOURCE_SEL_MASK BIT_MASK(GTHE3_CH_CBCC_DATA_SOURCE_SEL_MSB, GTHE3_CH_CBCC_DATA_SOURCE_SEL_LSB)
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#define GTHE3_CH_CBCC_DATA_SOURCE_SEL_ENCODED 0
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#define GTHE3_CH_CBCC_DATA_SOURCE_SEL_DECODED 1
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#define GTHE3_CH_OOB_PWRUP_ADDR 0x0063
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#define GTHE3_CH_OOB_PWRUP_MSB 14
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#define GTHE3_CH_OOB_PWRUP_LSB 14
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#define GTHE3_CH_OOB_PWRUP_MASK BIT_MASK(GTHE3_CH_OOB_PWRUP_MSB, GTHE3_CH_OOB_PWRUP_LSB)
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#define GTHE3_CH_RXOOB_CFG_ADDR 0x0063
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#define GTHE3_CH_RXOOB_CFG_MSB 13
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#define GTHE3_CH_RXOOB_CFG_LSB 5
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#define GTHE3_CH_RXOOB_CFG_MASK BIT_MASK(GTHE3_CH_RXOOB_CFG_MSB, GTHE3_CH_RXOOB_CFG_LSB)
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#define GTHE3_CH_RXOUT_DIV_ADDR 0x0063
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#define GTHE3_CH_RXOUT_DIV_MSB 2
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#define GTHE3_CH_RXOUT_DIV_LSB 0
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#define GTHE3_CH_RXOUT_DIV_MASK BIT_MASK(GTHE3_CH_RXOUT_DIV_MSB, GTHE3_CH_RXOUT_DIV_LSB)
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#define GTHE3_CH_RXOUT_DIV_1 0
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#define GTHE3_CH_RXOUT_DIV_2 1
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#define GTHE3_CH_RXOUT_DIV_4 2
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#define GTHE3_CH_RXOUT_DIV_8 3
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#define GTHE3_CH_RXOUT_DIV_16 4
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#define GTHE3_CH_RX_SIG_VALID_DLY_ADDR 0x0064
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#define GTHE3_CH_RX_SIG_VALID_DLY_MSB 15
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#define GTHE3_CH_RX_SIG_VALID_DLY_LSB 11
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#define GTHE3_CH_RX_SIG_VALID_DLY_MASK BIT_MASK(GTHE3_CH_RX_SIG_VALID_DLY_MSB, GTHE3_CH_RX_SIG_VALID_DLY_LSB)
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#define GTHE3_CH_RXSLIDE_MODE_ADDR 0x0064
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#define GTHE3_CH_RXSLIDE_MODE_MSB 10
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#define GTHE3_CH_RXSLIDE_MODE_LSB 9
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#define GTHE3_CH_RXSLIDE_MODE_MASK BIT_MASK(GTHE3_CH_RXSLIDE_MODE_MSB, GTHE3_CH_RXSLIDE_MODE_LSB)
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#define GTHE3_CH_RXSLIDE_MODE_OFF 0
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#define GTHE3_CH_RXSLIDE_MODE_AUTO 1
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#define GTHE3_CH_RXSLIDE_MODE_PCS 2
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#define GTHE3_CH_RXSLIDE_MODE_PMA 3
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#define GTHE3_CH_RXPRBS_ERR_LOOPBACK_ADDR 0x0064
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#define GTHE3_CH_RXPRBS_ERR_LOOPBACK_MSB 8
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#define GTHE3_CH_RXPRBS_ERR_LOOPBACK_LSB 8
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#define GTHE3_CH_RXPRBS_ERR_LOOPBACK_MASK BIT_MASK(GTHE3_CH_RXPRBS_ERR_LOOPBACK_MSB, GTHE3_CH_RXPRBS_ERR_LOOPBACK_LSB)
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#define GTHE3_CH_RXSLIDE_AUTO_WAIT_ADDR 0x0064
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#define GTHE3_CH_RXSLIDE_AUTO_WAIT_MSB 7
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#define GTHE3_CH_RXSLIDE_AUTO_WAIT_LSB 4
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#define GTHE3_CH_RXSLIDE_AUTO_WAIT_MASK BIT_MASK(GTHE3_CH_RXSLIDE_AUTO_WAIT_MSB, GTHE3_CH_RXSLIDE_AUTO_WAIT_LSB)
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#define GTHE3_CH_RXBUF_EN_ADDR 0x0064
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#define GTHE3_CH_RXBUF_EN_MSB 3
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#define GTHE3_CH_RXBUF_EN_LSB 3
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#define GTHE3_CH_RXBUF_EN_MASK BIT_MASK(GTHE3_CH_RXBUF_EN_MSB, GTHE3_CH_RXBUF_EN_LSB)
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#define GTHE3_CH_RX_XCLK_SEL_ADDR 0x0064
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#define GTHE3_CH_RX_XCLK_SEL_MSB 2
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#define GTHE3_CH_RX_XCLK_SEL_LSB 1
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#define GTHE3_CH_RX_XCLK_SEL_MASK BIT_MASK(GTHE3_CH_RX_XCLK_SEL_MSB, GTHE3_CH_RX_XCLK_SEL_LSB)
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#define GTHE3_CH_RX_XCLK_SEL_RXDES 0
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#define GTHE3_CH_RX_XCLK_SEL_RXUSR 1
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#define GTHE3_CH_RX_XCLK_SEL_RXPMA 2
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#define GTHE3_CH_RXGEARBOX_EN_ADDR 0x0064
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#define GTHE3_CH_RXGEARBOX_EN_MSB 0
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#define GTHE3_CH_RXGEARBOX_EN_LSB 0
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#define GTHE3_CH_RXGEARBOX_EN_MASK BIT_MASK(GTHE3_CH_RXGEARBOX_EN_MSB, GTHE3_CH_RXGEARBOX_EN_LSB)
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#define GTHE3_CH_RXBUF_THRESH_OVFLW_ADDR 0x0065
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#define GTHE3_CH_RXBUF_THRESH_OVFLW_MSB 15
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#define GTHE3_CH_RXBUF_THRESH_OVFLW_LSB 10
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#define GTHE3_CH_RXBUF_THRESH_OVFLW_MASK BIT_MASK(GTHE3_CH_RXBUF_THRESH_OVFLW_MSB, GTHE3_CH_RXBUF_THRESH_OVFLW_LSB)
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#define GTHE3_CH_DMONITOR_CFG0_ADDR 0x0065
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#define GTHE3_CH_DMONITOR_CFG0_MSB 9
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#define GTHE3_CH_DMONITOR_CFG0_LSB 0
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#define GTHE3_CH_DMONITOR_CFG0_MASK BIT_MASK(GTHE3_CH_DMONITOR_CFG0_MSB, GTHE3_CH_DMONITOR_CFG0_LSB)
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#define GTHE3_CH_RXBUF_THRESH_OVRD_ADDR 0x0066
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#define GTHE3_CH_RXBUF_THRESH_OVRD_MSB 15
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#define GTHE3_CH_RXBUF_THRESH_OVRD_LSB 15
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#define GTHE3_CH_RXBUF_THRESH_OVRD_MASK BIT_MASK(GTHE3_CH_RXBUF_THRESH_OVRD_MSB, GTHE3_CH_RXBUF_THRESH_OVRD_LSB)
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#define GTHE3_CH_RXBUF_RESET_ON_COMMAALIGN_ADDR 0x0066
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#define GTHE3_CH_RXBUF_RESET_ON_COMMAALIGN_MSB 14
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#define GTHE3_CH_RXBUF_RESET_ON_COMMAALIGN_LSB 14
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#define GTHE3_CH_RXBUF_RESET_ON_COMMAALIGN_MASK BIT_MASK(GTHE3_CH_RXBUF_RESET_ON_COMMAALIGN_MSB, GTHE3_CH_RXBUF_RESET_ON_COMMAALIGN_LSB)
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#define GTHE3_CH_RXBUF_RESET_ON_RATE_CHANGE_ADDR 0x0066
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#define GTHE3_CH_RXBUF_RESET_ON_RATE_CHANGE_MSB 13
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#define GTHE3_CH_RXBUF_RESET_ON_RATE_CHANGE_LSB 13
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#define GTHE3_CH_RXBUF_RESET_ON_RATE_CHANGE_MASK BIT_MASK(GTHE3_CH_RXBUF_RESET_ON_RATE_CHANGE_MSB, GTHE3_CH_RXBUF_RESET_ON_RATE_CHANGE_LSB)
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#define GTHE3_CH_RXBUF_RESET_ON_CB_CHANGE_ADDR 0x0066
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#define GTHE3_CH_RXBUF_RESET_ON_CB_CHANGE_MSB 12
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#define GTHE3_CH_RXBUF_RESET_ON_CB_CHANGE_LSB 12
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#define GTHE3_CH_RXBUF_RESET_ON_CB_CHANGE_MASK BIT_MASK(GTHE3_CH_RXBUF_RESET_ON_CB_CHANGE_MSB, GTHE3_CH_RXBUF_RESET_ON_CB_CHANGE_LSB)
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#define GTHE3_CH_RXBUF_THRESH_UNDFLW_ADDR 0x0066
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#define GTHE3_CH_RXBUF_THRESH_UNDFLW_MSB 11
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#define GTHE3_CH_RXBUF_THRESH_UNDFLW_LSB 6
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#define GTHE3_CH_RXBUF_THRESH_UNDFLW_MASK BIT_MASK(GTHE3_CH_RXBUF_THRESH_UNDFLW_MSB, GTHE3_CH_RXBUF_THRESH_UNDFLW_LSB)
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#define GTHE3_CH_RX_CLKMUX_EN_ADDR 0x0066
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#define GTHE3_CH_RX_CLKMUX_EN_MSB 5
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#define GTHE3_CH_RX_CLKMUX_EN_LSB 5
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#define GTHE3_CH_RX_CLKMUX_EN_MASK BIT_MASK(GTHE3_CH_RX_CLKMUX_EN_MSB, GTHE3_CH_RX_CLKMUX_EN_LSB)
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#define GTHE3_CH_RX_DISPERR_SEQ_MATCH_ADDR 0x0066
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#define GTHE3_CH_RX_DISPERR_SEQ_MATCH_MSB 4
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#define GTHE3_CH_RX_DISPERR_SEQ_MATCH_LSB 4
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#define GTHE3_CH_RX_DISPERR_SEQ_MATCH_MASK BIT_MASK(GTHE3_CH_RX_DISPERR_SEQ_MATCH_MSB, GTHE3_CH_RX_DISPERR_SEQ_MATCH_LSB)
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#define GTHE3_CH_RXBUF_ADDR_MODE_ADDR 0x0066
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#define GTHE3_CH_RXBUF_ADDR_MODE_MSB 3
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#define GTHE3_CH_RXBUF_ADDR_MODE_LSB 3
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#define GTHE3_CH_RXBUF_ADDR_MODE_MASK BIT_MASK(GTHE3_CH_RXBUF_ADDR_MODE_MSB, GTHE3_CH_RXBUF_ADDR_MODE_LSB)
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#define GTHE3_CH_RX_WIDEMODE_CDR_ADDR 0x0066
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#define GTHE3_CH_RX_WIDEMODE_CDR_MSB 2
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#define GTHE3_CH_RX_WIDEMODE_CDR_LSB 2
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#define GTHE3_CH_RX_WIDEMODE_CDR_MASK BIT_MASK(GTHE3_CH_RX_WIDEMODE_CDR_MSB, GTHE3_CH_RX_WIDEMODE_CDR_LSB)
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#define GTHE3_CH_RX_INT_DATAWIDTH_ADDR 0x0066
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#define GTHE3_CH_RX_INT_DATAWIDTH_MSB 1
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#define GTHE3_CH_RX_INT_DATAWIDTH_LSB 0
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#define GTHE3_CH_RX_INT_DATAWIDTH_MASK BIT_MASK(GTHE3_CH_RX_INT_DATAWIDTH_MSB, GTHE3_CH_RX_INT_DATAWIDTH_LSB)
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#define GTHE3_CH_RXBUF_EIDLE_HI_CNT_ADDR 0x0067
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#define GTHE3_CH_RXBUF_EIDLE_HI_CNT_MSB 15
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#define GTHE3_CH_RXBUF_EIDLE_HI_CNT_LSB 12
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#define GTHE3_CH_RXBUF_EIDLE_HI_CNT_MASK BIT_MASK(GTHE3_CH_RXBUF_EIDLE_HI_CNT_MSB, GTHE3_CH_RXBUF_EIDLE_HI_CNT_LSB)
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#define GTHE3_CH_RXCDR_HOLD_DURING_EIDLE_ADDR 0x0067
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#define GTHE3_CH_RXCDR_HOLD_DURING_EIDLE_MSB 11
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#define GTHE3_CH_RXCDR_HOLD_DURING_EIDLE_LSB 11
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#define GTHE3_CH_RXCDR_HOLD_DURING_EIDLE_MASK BIT_MASK(GTHE3_CH_RXCDR_HOLD_DURING_EIDLE_MSB, GTHE3_CH_RXCDR_HOLD_DURING_EIDLE_LSB)
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#define GTHE3_CH_RX_DFE_LPM_HOLD_DURING_EIDLE_ADDR 0x0067
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#define GTHE3_CH_RX_DFE_LPM_HOLD_DURING_EIDLE_MSB 10
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#define GTHE3_CH_RX_DFE_LPM_HOLD_DURING_EIDLE_LSB 10
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#define GTHE3_CH_RX_DFE_LPM_HOLD_DURING_EIDLE_MASK BIT_MASK(GTHE3_CH_RX_DFE_LPM_HOLD_DURING_EIDLE_MSB, GTHE3_CH_RX_DFE_LPM_HOLD_DURING_EIDLE_LSB)
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#define GTHE3_CH_RXBUF_EIDLE_LO_CNT_ADDR 0x0067
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#define GTHE3_CH_RXBUF_EIDLE_LO_CNT_MSB 7
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#define GTHE3_CH_RXBUF_EIDLE_LO_CNT_LSB 4
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#define GTHE3_CH_RXBUF_EIDLE_LO_CNT_MASK BIT_MASK(GTHE3_CH_RXBUF_EIDLE_LO_CNT_MSB, GTHE3_CH_RXBUF_EIDLE_LO_CNT_LSB)
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#define GTHE3_CH_RXBUF_RESET_ON_EIDLE_ADDR 0x0067
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#define GTHE3_CH_RXBUF_RESET_ON_EIDLE_MSB 3
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#define GTHE3_CH_RXBUF_RESET_ON_EIDLE_LSB 3
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#define GTHE3_CH_RXBUF_RESET_ON_EIDLE_MASK BIT_MASK(GTHE3_CH_RXBUF_RESET_ON_EIDLE_MSB, GTHE3_CH_RXBUF_RESET_ON_EIDLE_LSB)
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#define GTHE3_CH_RXCDR_FR_RESET_ON_EIDLE_ADDR 0x0067
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#define GTHE3_CH_RXCDR_FR_RESET_ON_EIDLE_MSB 2
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#define GTHE3_CH_RXCDR_FR_RESET_ON_EIDLE_LSB 2
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#define GTHE3_CH_RXCDR_FR_RESET_ON_EIDLE_MASK BIT_MASK(GTHE3_CH_RXCDR_FR_RESET_ON_EIDLE_MSB, GTHE3_CH_RXCDR_FR_RESET_ON_EIDLE_LSB)
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#define GTHE3_CH_RXCDR_PH_RESET_ON_EIDLE_ADDR 0x0067
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#define GTHE3_CH_RXCDR_PH_RESET_ON_EIDLE_MSB 1
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#define GTHE3_CH_RXCDR_PH_RESET_ON_EIDLE_LSB 1
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#define GTHE3_CH_RXCDR_PH_RESET_ON_EIDLE_MASK BIT_MASK(GTHE3_CH_RXCDR_PH_RESET_ON_EIDLE_MSB, GTHE3_CH_RXCDR_PH_RESET_ON_EIDLE_LSB)
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#define GTHE3_CH_SATA_BURST_VAL_ADDR 0x0068
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#define GTHE3_CH_SATA_BURST_VAL_MSB 15
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#define GTHE3_CH_SATA_BURST_VAL_LSB 13
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#define GTHE3_CH_SATA_BURST_VAL_MASK BIT_MASK(GTHE3_CH_SATA_BURST_VAL_MSB, GTHE3_CH_SATA_BURST_VAL_LSB)
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#define GTHE3_CH_SATA_BURST_SEQ_LEN_ADDR 0x0068
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#define GTHE3_CH_SATA_BURST_SEQ_LEN_MSB 7
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#define GTHE3_CH_SATA_BURST_SEQ_LEN_LSB 4
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#define GTHE3_CH_SATA_BURST_SEQ_LEN_MASK BIT_MASK(GTHE3_CH_SATA_BURST_SEQ_LEN_MSB, GTHE3_CH_SATA_BURST_SEQ_LEN_LSB)
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#define GTHE3_CH_SATA_EIDLE_VAL_ADDR 0x0068
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#define GTHE3_CH_SATA_EIDLE_VAL_MSB 2
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#define GTHE3_CH_SATA_EIDLE_VAL_LSB 0
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#define GTHE3_CH_SATA_EIDLE_VAL_MASK BIT_MASK(GTHE3_CH_SATA_EIDLE_VAL_MSB, GTHE3_CH_SATA_EIDLE_VAL_LSB)
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#define GTHE3_CH_SATA_MIN_BURST_ADDR 0x0069
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#define GTHE3_CH_SATA_MIN_BURST_MSB 15
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#define GTHE3_CH_SATA_MIN_BURST_LSB 10
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#define GTHE3_CH_SATA_MIN_BURST_MASK BIT_MASK(GTHE3_CH_SATA_MIN_BURST_MSB, GTHE3_CH_SATA_MIN_BURST_LSB)
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#define GTHE3_CH_SAS_MIN_COM_ADDR 0x0069
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#define GTHE3_CH_SAS_MIN_COM_MSB 6
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#define GTHE3_CH_SAS_MIN_COM_LSB 1
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#define GTHE3_CH_SAS_MIN_COM_MASK BIT_MASK(GTHE3_CH_SAS_MIN_COM_MSB, GTHE3_CH_SAS_MIN_COM_LSB)
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#define GTHE3_CH_SATA_MIN_INIT_ADDR 0x006A
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#define GTHE3_CH_SATA_MIN_INIT_MSB 15
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#define GTHE3_CH_SATA_MIN_INIT_LSB 10
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#define GTHE3_CH_SATA_MIN_INIT_MASK BIT_MASK(GTHE3_CH_SATA_MIN_INIT_MSB, GTHE3_CH_SATA_MIN_INIT_LSB)
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#define GTHE3_CH_SATA_MIN_WAKE_ADDR 0x006A
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#define GTHE3_CH_SATA_MIN_WAKE_MSB 6
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#define GTHE3_CH_SATA_MIN_WAKE_LSB 1
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#define GTHE3_CH_SATA_MIN_WAKE_MASK BIT_MASK(GTHE3_CH_SATA_MIN_WAKE_MSB, GTHE3_CH_SATA_MIN_WAKE_LSB)
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#define GTHE3_CH_SATA_MAX_BURST_ADDR 0x006B
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#define GTHE3_CH_SATA_MAX_BURST_MSB 15
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#define GTHE3_CH_SATA_MAX_BURST_LSB 10
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#define GTHE3_CH_SATA_MAX_BURST_MASK BIT_MASK(GTHE3_CH_SATA_MAX_BURST_MSB, GTHE3_CH_SATA_MAX_BURST_LSB)
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#define GTHE3_CH_SAS_MAX_COM_ADDR 0x006B
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#define GTHE3_CH_SAS_MAX_COM_MSB 6
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#define GTHE3_CH_SAS_MAX_COM_LSB 0
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#define GTHE3_CH_SAS_MAX_COM_MASK BIT_MASK(GTHE3_CH_SAS_MAX_COM_MSB, GTHE3_CH_SAS_MAX_COM_LSB)
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#define GTHE3_CH_SATA_MAX_INIT_ADDR 0x006C
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#define GTHE3_CH_SATA_MAX_INIT_MSB 15
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#define GTHE3_CH_SATA_MAX_INIT_LSB 10
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#define GTHE3_CH_SATA_MAX_INIT_MASK BIT_MASK(GTHE3_CH_SATA_MAX_INIT_MSB, GTHE3_CH_SATA_MAX_INIT_LSB)
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#define GTHE3_CH_SATA_MAX_WAKE_ADDR 0x006C
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#define GTHE3_CH_SATA_MAX_WAKE_MSB 6
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#define GTHE3_CH_SATA_MAX_WAKE_LSB 1
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#define GTHE3_CH_SATA_MAX_WAKE_MASK BIT_MASK(GTHE3_CH_SATA_MAX_WAKE_MSB, GTHE3_CH_SATA_MAX_WAKE_LSB)
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#define GTHE3_CH_RX_CLK25_DIV_ADDR 0x006D
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#define GTHE3_CH_RX_CLK25_DIV_MSB 7
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#define GTHE3_CH_RX_CLK25_DIV_LSB 3
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#define GTHE3_CH_RX_CLK25_DIV_MASK BIT_MASK(GTHE3_CH_RX_CLK25_DIV_MSB, GTHE3_CH_RX_CLK25_DIV_LSB)
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#define GTHE3_CH_TXPHDLY_CFG0_ADDR 0x006E
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#define GTHE3_CH_TXPHDLY_CFG0_MSB 15
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#define GTHE3_CH_TXPHDLY_CFG0_LSB 0
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#define GTHE3_CH_TXPHDLY_CFG0_MASK BIT_MASK(GTHE3_CH_TXPHDLY_CFG0_MSB, GTHE3_CH_TXPHDLY_CFG0_LSB)
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#define GTHE3_CH_TXPHDLY_CFG1_ADDR 0x006F
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#define GTHE3_CH_TXPHDLY_CFG1_MSB 15
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#define GTHE3_CH_TXPHDLY_CFG1_LSB 0
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#define GTHE3_CH_TXPHDLY_CFG1_MASK BIT_MASK(GTHE3_CH_TXPHDLY_CFG1_MSB, GTHE3_CH_TXPHDLY_CFG1_LSB)
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#define GTHE3_CH_TXDLY_CFG_ADDR 0x0070
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#define GTHE3_CH_TXDLY_CFG_MSB 15
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#define GTHE3_CH_TXDLY_CFG_LSB 0
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#define GTHE3_CH_TXDLY_CFG_MASK BIT_MASK(GTHE3_CH_TXDLY_CFG_MSB, GTHE3_CH_TXDLY_CFG_LSB)
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#define GTHE3_CH_TXPH_MONITOR_SEL_ADDR 0x0071
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#define GTHE3_CH_TXPH_MONITOR_SEL_MSB 6
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#define GTHE3_CH_TXPH_MONITOR_SEL_LSB 2
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#define GTHE3_CH_TXPH_MONITOR_SEL_MASK BIT_MASK(GTHE3_CH_TXPH_MONITOR_SEL_MSB, GTHE3_CH_TXPH_MONITOR_SEL_LSB)
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#define GTHE3_CH_TAPDLY_SET_TX_ADDR 0x0071
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#define GTHE3_CH_TAPDLY_SET_TX_MSB 1
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#define GTHE3_CH_TAPDLY_SET_TX_LSB 0
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#define GTHE3_CH_TAPDLY_SET_TX_MASK BIT_MASK(GTHE3_CH_TAPDLY_SET_TX_MSB, GTHE3_CH_TAPDLY_SET_TX_LSB)
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#define GTHE3_CH_RXCDR_LOCK_CFG2_ADDR 0x0072
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#define GTHE3_CH_RXCDR_LOCK_CFG2_MSB 15
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#define GTHE3_CH_RXCDR_LOCK_CFG2_LSB 0
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#define GTHE3_CH_RXCDR_LOCK_CFG2_MASK BIT_MASK(GTHE3_CH_RXCDR_LOCK_CFG2_MSB, GTHE3_CH_RXCDR_LOCK_CFG2_LSB)
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#define GTHE3_CH_TXPH_CFG_ADDR 0x0073
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#define GTHE3_CH_TXPH_CFG_MSB 15
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#define GTHE3_CH_TXPH_CFG_LSB 0
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#define GTHE3_CH_TXPH_CFG_MASK BIT_MASK(GTHE3_CH_TXPH_CFG_MSB, GTHE3_CH_TXPH_CFG_LSB)
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#define GTHE3_CH_TERM_RCAL_CFG_ADDR 0x0074
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#define GTHE3_CH_TERM_RCAL_CFG_MSB 14
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#define GTHE3_CH_TERM_RCAL_CFG_LSB 0
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#define GTHE3_CH_TERM_RCAL_CFG_MASK BIT_MASK(GTHE3_CH_TERM_RCAL_CFG_MSB, GTHE3_CH_TERM_RCAL_CFG_LSB)
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#define GTHE3_CH_RXDFE_HF_CFG1_ADDR 0x0075
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#define GTHE3_CH_RXDFE_HF_CFG1_MSB 15
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#define GTHE3_CH_RXDFE_HF_CFG1_LSB 0
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#define GTHE3_CH_RXDFE_HF_CFG1_MASK BIT_MASK(GTHE3_CH_RXDFE_HF_CFG1_MSB, GTHE3_CH_RXDFE_HF_CFG1_LSB)
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#define GTHE3_CH_PD_TRANS_TIME_FROM_P2_ADDR 0x0076
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#define GTHE3_CH_PD_TRANS_TIME_FROM_P2_MSB 15
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#define GTHE3_CH_PD_TRANS_TIME_FROM_P2_LSB 4
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#define GTHE3_CH_PD_TRANS_TIME_FROM_P2_MASK BIT_MASK(GTHE3_CH_PD_TRANS_TIME_FROM_P2_MSB, GTHE3_CH_PD_TRANS_TIME_FROM_P2_LSB)
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#define GTHE3_CH_TERM_RCAL_OVRD_ADDR 0x0076
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#define GTHE3_CH_TERM_RCAL_OVRD_MSB 3
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#define GTHE3_CH_TERM_RCAL_OVRD_LSB 1
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#define GTHE3_CH_TERM_RCAL_OVRD_MASK BIT_MASK(GTHE3_CH_TERM_RCAL_OVRD_MSB, GTHE3_CH_TERM_RCAL_OVRD_LSB)
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#define GTHE3_CH_PD_TRANS_TIME_NONE_P2_ADDR 0x0077
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#define GTHE3_CH_PD_TRANS_TIME_NONE_P2_MSB 15
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#define GTHE3_CH_PD_TRANS_TIME_NONE_P2_LSB 8
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#define GTHE3_CH_PD_TRANS_TIME_NONE_P2_MASK BIT_MASK(GTHE3_CH_PD_TRANS_TIME_NONE_P2_MSB, GTHE3_CH_PD_TRANS_TIME_NONE_P2_LSB)
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#define GTHE3_CH_PD_TRANS_TIME_TO_P2_ADDR 0x0077
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#define GTHE3_CH_PD_TRANS_TIME_TO_P2_MSB 7
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#define GTHE3_CH_PD_TRANS_TIME_TO_P2_LSB 0
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#define GTHE3_CH_PD_TRANS_TIME_TO_P2_MASK BIT_MASK(GTHE3_CH_PD_TRANS_TIME_TO_P2_MSB, GTHE3_CH_PD_TRANS_TIME_TO_P2_LSB)
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#define GTHE3_CH_TRANS_TIME_RATE_ADDR 0x0078
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#define GTHE3_CH_TRANS_TIME_RATE_MSB 15
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#define GTHE3_CH_TRANS_TIME_RATE_LSB 8
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#define GTHE3_CH_TRANS_TIME_RATE_MASK BIT_MASK(GTHE3_CH_TRANS_TIME_RATE_MSB, GTHE3_CH_TRANS_TIME_RATE_LSB)
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#define GTHE3_CH_TST_RSV0_ADDR 0x0079
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#define GTHE3_CH_TST_RSV0_MSB 15
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#define GTHE3_CH_TST_RSV0_LSB 8
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#define GTHE3_CH_TST_RSV0_MASK BIT_MASK(GTHE3_CH_TST_RSV0_MSB, GTHE3_CH_TST_RSV0_LSB)
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#define GTHE3_CH_TST_RSV1_ADDR 0x0079
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#define GTHE3_CH_TST_RSV1_MSB 7
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#define GTHE3_CH_TST_RSV1_LSB 0
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#define GTHE3_CH_TST_RSV1_MASK BIT_MASK(GTHE3_CH_TST_RSV1_MSB, GTHE3_CH_TST_RSV1_LSB)
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#define GTHE3_CH_TX_CLK25_DIV_ADDR 0x007A
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#define GTHE3_CH_TX_CLK25_DIV_MSB 15
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#define GTHE3_CH_TX_CLK25_DIV_LSB 11
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#define GTHE3_CH_TX_CLK25_DIV_MASK BIT_MASK(GTHE3_CH_TX_CLK25_DIV_MSB, GTHE3_CH_TX_CLK25_DIV_LSB)
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#define GTHE3_CH_TX_XCLK_SEL_ADDR 0x007A
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#define GTHE3_CH_TX_XCLK_SEL_MSB 10
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#define GTHE3_CH_TX_XCLK_SEL_LSB 10
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#define GTHE3_CH_TX_XCLK_SEL_MASK BIT_MASK(GTHE3_CH_TX_XCLK_SEL_MSB, GTHE3_CH_TX_XCLK_SEL_LSB)
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#define GTHE3_CH_TX_XCLK_SEL_TXOUT 0
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#define GTHE3_CH_TX_XCLK_SEL_TXUSR 1
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#define GTHE3_CH_TX_DATA_WIDTH_ADDR 0x007A
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#define GTHE3_CH_TX_DATA_WIDTH_MSB 3
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#define GTHE3_CH_TX_DATA_WIDTH_LSB 0
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#define GTHE3_CH_TX_DATA_WIDTH_MASK BIT_MASK(GTHE3_CH_TX_DATA_WIDTH_MSB, GTHE3_CH_TX_DATA_WIDTH_LSB)
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#define GTHE3_CH_TX_DATA_WIDTH_16 2
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#define GTHE3_CH_TX_DATA_WIDTH_20 3
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#define GTHE3_CH_TX_DATA_WIDTH_32 4
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#define GTHE3_CH_TX_DATA_WIDTH_40 5
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#define GTHE3_CH_TX_DATA_WIDTH_64 6
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#define GTHE3_CH_TX_DATA_WIDTH_80 7
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#define GTHE3_CH_TX_DATA_WIDTH_128 8
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#define GTHE3_CH_TX_DATA_WIDTH_160 9
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#define GTHE3_CH_TX_DEEMPH0_ADDR 0x007B
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#define GTHE3_CH_TX_DEEMPH0_MSB 15
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#define GTHE3_CH_TX_DEEMPH0_LSB 10
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#define GTHE3_CH_TX_DEEMPH0_MASK BIT_MASK(GTHE3_CH_TX_DEEMPH0_MSB, GTHE3_CH_TX_DEEMPH0_LSB)
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#define GTHE3_CH_TX_DEEMPH1_ADDR 0x007B
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#define GTHE3_CH_TX_DEEMPH1_MSB 7
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#define GTHE3_CH_TX_DEEMPH1_LSB 2
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#define GTHE3_CH_TX_DEEMPH1_MASK BIT_MASK(GTHE3_CH_TX_DEEMPH1_MSB, GTHE3_CH_TX_DEEMPH1_LSB)
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#define GTHE3_CH_TX_MAINCURSOR_SEL_ADDR 0x007C
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#define GTHE3_CH_TX_MAINCURSOR_SEL_MSB 14
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#define GTHE3_CH_TX_MAINCURSOR_SEL_LSB 14
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#define GTHE3_CH_TX_MAINCURSOR_SEL_MASK BIT_MASK(GTHE3_CH_TX_MAINCURSOR_SEL_MSB, GTHE3_CH_TX_MAINCURSOR_SEL_LSB)
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#define GTHE3_CH_TXGEARBOX_EN_ADDR 0x007C
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#define GTHE3_CH_TXGEARBOX_EN_MSB 13
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#define GTHE3_CH_TXGEARBOX_EN_LSB 13
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#define GTHE3_CH_TXGEARBOX_EN_MASK BIT_MASK(GTHE3_CH_TXGEARBOX_EN_MSB, GTHE3_CH_TXGEARBOX_EN_LSB)
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#define GTHE3_CH_TXOUT_DIV_ADDR 0x007C
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#define GTHE3_CH_TXOUT_DIV_MSB 10
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#define GTHE3_CH_TXOUT_DIV_LSB 8
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#define GTHE3_CH_TXOUT_DIV_MASK BIT_MASK(GTHE3_CH_TXOUT_DIV_MSB, GTHE3_CH_TXOUT_DIV_LSB)
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#define GTHE3_CH_TXOUT_DIV_1 0
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#define GTHE3_CH_TXOUT_DIV_2 1
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#define GTHE3_CH_TXOUT_DIV_4 2
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#define GTHE3_CH_TXOUT_DIV_8 3
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#define GTHE3_CH_TXOUT_DIV_16 4
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#define GTHE3_CH_TXBUF_EN_ADDR 0x007C
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#define GTHE3_CH_TXBUF_EN_MSB 7
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#define GTHE3_CH_TXBUF_EN_LSB 7
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#define GTHE3_CH_TXBUF_EN_MASK BIT_MASK(GTHE3_CH_TXBUF_EN_MSB, GTHE3_CH_TXBUF_EN_LSB)
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#define GTHE3_CH_TXBUF_RESET_ON_RATE_CHANGE_ADDR 0x007C
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#define GTHE3_CH_TXBUF_RESET_ON_RATE_CHANGE_MSB 6
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#define GTHE3_CH_TXBUF_RESET_ON_RATE_CHANGE_LSB 6
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#define GTHE3_CH_TXBUF_RESET_ON_RATE_CHANGE_MASK BIT_MASK(GTHE3_CH_TXBUF_RESET_ON_RATE_CHANGE_MSB, GTHE3_CH_TXBUF_RESET_ON_RATE_CHANGE_LSB)
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#define GTHE3_CH_TX_RXDETECT_REF_ADDR 0x007C
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#define GTHE3_CH_TX_RXDETECT_REF_MSB 5
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#define GTHE3_CH_TX_RXDETECT_REF_LSB 3
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#define GTHE3_CH_TX_RXDETECT_REF_MASK BIT_MASK(GTHE3_CH_TX_RXDETECT_REF_MSB, GTHE3_CH_TX_RXDETECT_REF_LSB)
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#define GTHE3_CH_TXFIFO_ADDR_CFG_ADDR 0x007C
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#define GTHE3_CH_TXFIFO_ADDR_CFG_MSB 2
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#define GTHE3_CH_TXFIFO_ADDR_CFG_LSB 2
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#define GTHE3_CH_TXFIFO_ADDR_CFG_MASK BIT_MASK(GTHE3_CH_TXFIFO_ADDR_CFG_MSB, GTHE3_CH_TXFIFO_ADDR_CFG_LSB)
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#define GTHE3_CH_TXFIFO_ADDR_CFG_LOW 0
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#define GTHE3_CH_TXFIFO_ADDR_CFG_HIGH 1
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#define GTHE3_CH_TX_RXDETECT_CFG_ADDR 0x007D
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#define GTHE3_CH_TX_RXDETECT_CFG_MSB 15
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#define GTHE3_CH_TX_RXDETECT_CFG_LSB 2
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#define GTHE3_CH_TX_RXDETECT_CFG_MASK BIT_MASK(GTHE3_CH_TX_RXDETECT_CFG_MSB, GTHE3_CH_TX_RXDETECT_CFG_LSB)
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#define GTHE3_CH_TX_CLKMUX_EN_ADDR 0x007E
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#define GTHE3_CH_TX_CLKMUX_EN_MSB 15
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#define GTHE3_CH_TX_CLKMUX_EN_LSB 15
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#define GTHE3_CH_TX_CLKMUX_EN_MASK BIT_MASK(GTHE3_CH_TX_CLKMUX_EN_MSB, GTHE3_CH_TX_CLKMUX_EN_LSB)
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#define GTHE3_CH_TX_LOOPBACK_DRIVE_HIZ_ADDR 0x007E
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#define GTHE3_CH_TX_LOOPBACK_DRIVE_HIZ_MSB 14
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#define GTHE3_CH_TX_LOOPBACK_DRIVE_HIZ_LSB 14
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#define GTHE3_CH_TX_LOOPBACK_DRIVE_HIZ_MASK BIT_MASK(GTHE3_CH_TX_LOOPBACK_DRIVE_HIZ_MSB, GTHE3_CH_TX_LOOPBACK_DRIVE_HIZ_LSB)
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#define GTHE3_CH_TX_DRIVE_MODE_ADDR 0x007E
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#define GTHE3_CH_TX_DRIVE_MODE_MSB 12
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#define GTHE3_CH_TX_DRIVE_MODE_LSB 8
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#define GTHE3_CH_TX_DRIVE_MODE_MASK BIT_MASK(GTHE3_CH_TX_DRIVE_MODE_MSB, GTHE3_CH_TX_DRIVE_MODE_LSB)
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#define GTHE3_CH_TX_DRIVE_MODE_DIRECT 0
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#define GTHE3_CH_TX_DRIVE_MODE_PIPE 1
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#define GTHE3_CH_TX_DRIVE_MODE_PIPEGEN3 2
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#define GTHE3_CH_TX_EIDLE_ASSERT_DELAY_ADDR 0x007E
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#define GTHE3_CH_TX_EIDLE_ASSERT_DELAY_MSB 7
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#define GTHE3_CH_TX_EIDLE_ASSERT_DELAY_LSB 5
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#define GTHE3_CH_TX_EIDLE_ASSERT_DELAY_MASK BIT_MASK(GTHE3_CH_TX_EIDLE_ASSERT_DELAY_MSB, GTHE3_CH_TX_EIDLE_ASSERT_DELAY_LSB)
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#define GTHE3_CH_TX_EIDLE_DEASSERT_DELAY_ADDR 0x007E
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#define GTHE3_CH_TX_EIDLE_DEASSERT_DELAY_MSB 4
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#define GTHE3_CH_TX_EIDLE_DEASSERT_DELAY_LSB 2
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#define GTHE3_CH_TX_EIDLE_DEASSERT_DELAY_MASK BIT_MASK(GTHE3_CH_TX_EIDLE_DEASSERT_DELAY_MSB, GTHE3_CH_TX_EIDLE_DEASSERT_DELAY_LSB)
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#define GTHE3_CH_TX_MARGIN_FULL_0_ADDR 0x007F
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#define GTHE3_CH_TX_MARGIN_FULL_0_MSB 15
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#define GTHE3_CH_TX_MARGIN_FULL_0_LSB 9
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#define GTHE3_CH_TX_MARGIN_FULL_0_MASK BIT_MASK(GTHE3_CH_TX_MARGIN_FULL_0_MSB, GTHE3_CH_TX_MARGIN_FULL_0_LSB)
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#define GTHE3_CH_TX_MARGIN_FULL_1_ADDR 0x007F
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#define GTHE3_CH_TX_MARGIN_FULL_1_MSB 7
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#define GTHE3_CH_TX_MARGIN_FULL_1_LSB 1
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#define GTHE3_CH_TX_MARGIN_FULL_1_MASK BIT_MASK(GTHE3_CH_TX_MARGIN_FULL_1_MSB, GTHE3_CH_TX_MARGIN_FULL_1_LSB)
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#define GTHE3_CH_TX_MARGIN_FULL_2_ADDR 0x0080
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#define GTHE3_CH_TX_MARGIN_FULL_2_MSB 15
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#define GTHE3_CH_TX_MARGIN_FULL_2_LSB 9
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#define GTHE3_CH_TX_MARGIN_FULL_2_MASK BIT_MASK(GTHE3_CH_TX_MARGIN_FULL_2_MSB, GTHE3_CH_TX_MARGIN_FULL_2_LSB)
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#define GTHE3_CH_TX_MARGIN_FULL_3_ADDR 0x0080
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#define GTHE3_CH_TX_MARGIN_FULL_3_MSB 7
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#define GTHE3_CH_TX_MARGIN_FULL_3_LSB 1
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#define GTHE3_CH_TX_MARGIN_FULL_3_MASK BIT_MASK(GTHE3_CH_TX_MARGIN_FULL_3_MSB, GTHE3_CH_TX_MARGIN_FULL_3_LSB)
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#define GTHE3_CH_TX_MARGIN_FULL_4_ADDR 0x0081
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#define GTHE3_CH_TX_MARGIN_FULL_4_MSB 15
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#define GTHE3_CH_TX_MARGIN_FULL_4_LSB 9
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#define GTHE3_CH_TX_MARGIN_FULL_4_MASK BIT_MASK(GTHE3_CH_TX_MARGIN_FULL_4_MSB, GTHE3_CH_TX_MARGIN_FULL_4_LSB)
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#define GTHE3_CH_TX_MARGIN_LOW_0_ADDR 0x0081
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#define GTHE3_CH_TX_MARGIN_LOW_0_MSB 7
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#define GTHE3_CH_TX_MARGIN_LOW_0_LSB 1
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#define GTHE3_CH_TX_MARGIN_LOW_0_MASK BIT_MASK(GTHE3_CH_TX_MARGIN_LOW_0_MSB, GTHE3_CH_TX_MARGIN_LOW_0_LSB)
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#define GTHE3_CH_TX_MARGIN_LOW_1_ADDR 0x0082
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#define GTHE3_CH_TX_MARGIN_LOW_1_MSB 15
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#define GTHE3_CH_TX_MARGIN_LOW_1_LSB 9
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#define GTHE3_CH_TX_MARGIN_LOW_1_MASK BIT_MASK(GTHE3_CH_TX_MARGIN_LOW_1_MSB, GTHE3_CH_TX_MARGIN_LOW_1_LSB)
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#define GTHE3_CH_TX_MARGIN_LOW_2_ADDR 0x0082
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#define GTHE3_CH_TX_MARGIN_LOW_2_MSB 7
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#define GTHE3_CH_TX_MARGIN_LOW_2_LSB 1
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#define GTHE3_CH_TX_MARGIN_LOW_2_MASK BIT_MASK(GTHE3_CH_TX_MARGIN_LOW_2_MSB, GTHE3_CH_TX_MARGIN_LOW_2_LSB)
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#define GTHE3_CH_TX_MARGIN_LOW_3_ADDR 0x0083
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#define GTHE3_CH_TX_MARGIN_LOW_3_MSB 15
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#define GTHE3_CH_TX_MARGIN_LOW_3_LSB 9
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#define GTHE3_CH_TX_MARGIN_LOW_3_MASK BIT_MASK(GTHE3_CH_TX_MARGIN_LOW_3_MSB, GTHE3_CH_TX_MARGIN_LOW_3_LSB)
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#define GTHE3_CH_TX_MARGIN_LOW_4_ADDR 0x0083
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#define GTHE3_CH_TX_MARGIN_LOW_4_MSB 7
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#define GTHE3_CH_TX_MARGIN_LOW_4_LSB 1
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#define GTHE3_CH_TX_MARGIN_LOW_4_MASK BIT_MASK(GTHE3_CH_TX_MARGIN_LOW_4_MSB, GTHE3_CH_TX_MARGIN_LOW_4_LSB)
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#define GTHE3_CH_RXDFE_HD_CFG1_ADDR 0x0084
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#define GTHE3_CH_RXDFE_HD_CFG1_MSB 15
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#define GTHE3_CH_RXDFE_HD_CFG1_LSB 0
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#define GTHE3_CH_RXDFE_HD_CFG1_MASK BIT_MASK(GTHE3_CH_RXDFE_HD_CFG1_MSB, GTHE3_CH_RXDFE_HD_CFG1_LSB)
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#define GTHE3_CH_TX_QPI_STATUS_EN_ADDR 0x0085
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#define GTHE3_CH_TX_QPI_STATUS_EN_MSB 13
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#define GTHE3_CH_TX_QPI_STATUS_EN_LSB 13
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#define GTHE3_CH_TX_QPI_STATUS_EN_MASK BIT_MASK(GTHE3_CH_TX_QPI_STATUS_EN_MSB, GTHE3_CH_TX_QPI_STATUS_EN_LSB)
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#define GTHE3_CH_TX_INT_DATAWIDTH_ADDR 0x0085
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#define GTHE3_CH_TX_INT_DATAWIDTH_MSB 11
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#define GTHE3_CH_TX_INT_DATAWIDTH_LSB 10
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#define GTHE3_CH_TX_INT_DATAWIDTH_MASK BIT_MASK(GTHE3_CH_TX_INT_DATAWIDTH_MSB, GTHE3_CH_TX_INT_DATAWIDTH_LSB)
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#define GTHE3_CH_RXPRBS_LINKACQ_CNT_ADDR 0x0089
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#define GTHE3_CH_RXPRBS_LINKACQ_CNT_MSB 7
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#define GTHE3_CH_RXPRBS_LINKACQ_CNT_LSB 0
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#define GTHE3_CH_RXPRBS_LINKACQ_CNT_MASK BIT_MASK(GTHE3_CH_RXPRBS_LINKACQ_CNT_MSB, GTHE3_CH_RXPRBS_LINKACQ_CNT_LSB)
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#define GTHE3_CH_TX_PMADATA_OPT_ADDR 0x008A
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#define GTHE3_CH_TX_PMADATA_OPT_MSB 15
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#define GTHE3_CH_TX_PMADATA_OPT_LSB 15
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#define GTHE3_CH_TX_PMADATA_OPT_MASK BIT_MASK(GTHE3_CH_TX_PMADATA_OPT_MSB, GTHE3_CH_TX_PMADATA_OPT_LSB)
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#define GTHE3_CH_RXSYNC_OVRD_ADDR 0x008A
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#define GTHE3_CH_RXSYNC_OVRD_MSB 14
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#define GTHE3_CH_RXSYNC_OVRD_LSB 14
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#define GTHE3_CH_RXSYNC_OVRD_MASK BIT_MASK(GTHE3_CH_RXSYNC_OVRD_MSB, GTHE3_CH_RXSYNC_OVRD_LSB)
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#define GTHE3_CH_TXSYNC_OVRD_ADDR 0x008A
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#define GTHE3_CH_TXSYNC_OVRD_MSB 13
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#define GTHE3_CH_TXSYNC_OVRD_LSB 13
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#define GTHE3_CH_TXSYNC_OVRD_MASK BIT_MASK(GTHE3_CH_TXSYNC_OVRD_MSB, GTHE3_CH_TXSYNC_OVRD_LSB)
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#define GTHE3_CH_TX_IDLE_DATA_ZERO_ADDR 0x008A
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#define GTHE3_CH_TX_IDLE_DATA_ZERO_MSB 12
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#define GTHE3_CH_TX_IDLE_DATA_ZERO_LSB 12
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#define GTHE3_CH_TX_IDLE_DATA_ZERO_MASK BIT_MASK(GTHE3_CH_TX_IDLE_DATA_ZERO_MSB, GTHE3_CH_TX_IDLE_DATA_ZERO_LSB)
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#define GTHE3_CH_A_RXOSCALRESET_ADDR 0x008A
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#define GTHE3_CH_A_RXOSCALRESET_MSB 11
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#define GTHE3_CH_A_RXOSCALRESET_LSB 11
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#define GTHE3_CH_A_RXOSCALRESET_MASK BIT_MASK(GTHE3_CH_A_RXOSCALRESET_MSB, GTHE3_CH_A_RXOSCALRESET_LSB)
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#define GTHE3_CH_RXOOB_CLK_CFG_ADDR 0x008A
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#define GTHE3_CH_RXOOB_CLK_CFG_MSB 10
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#define GTHE3_CH_RXOOB_CLK_CFG_LSB 10
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#define GTHE3_CH_RXOOB_CLK_CFG_MASK BIT_MASK(GTHE3_CH_RXOOB_CLK_CFG_MSB, GTHE3_CH_RXOOB_CLK_CFG_LSB)
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#define GTHE3_CH_TXSYNC_SKIP_DA_ADDR 0x008A
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#define GTHE3_CH_TXSYNC_SKIP_DA_MSB 9
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#define GTHE3_CH_TXSYNC_SKIP_DA_LSB 9
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#define GTHE3_CH_TXSYNC_SKIP_DA_MASK BIT_MASK(GTHE3_CH_TXSYNC_SKIP_DA_MSB, GTHE3_CH_TXSYNC_SKIP_DA_LSB)
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#define GTHE3_CH_RXSYNC_SKIP_DA_ADDR 0x008A
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#define GTHE3_CH_RXSYNC_SKIP_DA_MSB 8
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#define GTHE3_CH_RXSYNC_SKIP_DA_LSB 8
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#define GTHE3_CH_RXSYNC_SKIP_DA_MASK BIT_MASK(GTHE3_CH_RXSYNC_SKIP_DA_MSB, GTHE3_CH_RXSYNC_SKIP_DA_LSB)
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#define GTHE3_CH_RXOSCALRESET_TIME_ADDR 0x008A
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#define GTHE3_CH_RXOSCALRESET_TIME_MSB 4
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#define GTHE3_CH_RXOSCALRESET_TIME_LSB 0
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#define GTHE3_CH_RXOSCALRESET_TIME_MASK BIT_MASK(GTHE3_CH_RXOSCALRESET_TIME_MSB, GTHE3_CH_RXOSCALRESET_TIME_LSB)
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#define GTHE3_CH_TXSYNC_MULTILANE_ADDR 0x008B
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#define GTHE3_CH_TXSYNC_MULTILANE_MSB 10
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#define GTHE3_CH_TXSYNC_MULTILANE_LSB 10
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#define GTHE3_CH_TXSYNC_MULTILANE_MASK BIT_MASK(GTHE3_CH_TXSYNC_MULTILANE_MSB, GTHE3_CH_TXSYNC_MULTILANE_LSB)
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#define GTHE3_CH_RXSYNC_MULTILANE_ADDR 0x008B
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#define GTHE3_CH_RXSYNC_MULTILANE_MSB 9
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#define GTHE3_CH_RXSYNC_MULTILANE_LSB 9
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#define GTHE3_CH_RXSYNC_MULTILANE_MASK BIT_MASK(GTHE3_CH_RXSYNC_MULTILANE_MSB, GTHE3_CH_RXSYNC_MULTILANE_LSB)
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#define GTHE3_CH_RX_CTLE3_LPF_ADDR 0x008B
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#define GTHE3_CH_RX_CTLE3_LPF_MSB 7
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#define GTHE3_CH_RX_CTLE3_LPF_LSB 0
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#define GTHE3_CH_RX_CTLE3_LPF_MASK BIT_MASK(GTHE3_CH_RX_CTLE3_LPF_MSB, GTHE3_CH_RX_CTLE3_LPF_LSB)
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#define GTHE3_CH_ACJTAG_MODE_ADDR 0x008C
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#define GTHE3_CH_ACJTAG_MODE_MSB 15
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#define GTHE3_CH_ACJTAG_MODE_LSB 15
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#define GTHE3_CH_ACJTAG_MODE_MASK BIT_MASK(GTHE3_CH_ACJTAG_MODE_MSB, GTHE3_CH_ACJTAG_MODE_LSB)
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#define GTHE3_CH_ACJTAG_DEBUG_MODE_ADDR 0x008C
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#define GTHE3_CH_ACJTAG_DEBUG_MODE_MSB 14
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#define GTHE3_CH_ACJTAG_DEBUG_MODE_LSB 14
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#define GTHE3_CH_ACJTAG_DEBUG_MODE_MASK BIT_MASK(GTHE3_CH_ACJTAG_DEBUG_MODE_MSB, GTHE3_CH_ACJTAG_DEBUG_MODE_LSB)
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#define GTHE3_CH_ACJTAG_RESET_ADDR 0x008C
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#define GTHE3_CH_ACJTAG_RESET_MSB 13
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#define GTHE3_CH_ACJTAG_RESET_LSB 13
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#define GTHE3_CH_ACJTAG_RESET_MASK BIT_MASK(GTHE3_CH_ACJTAG_RESET_MSB, GTHE3_CH_ACJTAG_RESET_LSB)
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#define GTHE3_CH_RESET_POWERSAVE_DISABLE_ADDR 0x008C
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#define GTHE3_CH_RESET_POWERSAVE_DISABLE_MSB 12
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#define GTHE3_CH_RESET_POWERSAVE_DISABLE_LSB 12
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#define GTHE3_CH_RESET_POWERSAVE_DISABLE_MASK BIT_MASK(GTHE3_CH_RESET_POWERSAVE_DISABLE_MSB, GTHE3_CH_RESET_POWERSAVE_DISABLE_LSB)
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#define GTHE3_CH_RX_TUNE_AFE_OS_ADDR 0x008C
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#define GTHE3_CH_RX_TUNE_AFE_OS_MSB 11
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#define GTHE3_CH_RX_TUNE_AFE_OS_LSB 10
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#define GTHE3_CH_RX_TUNE_AFE_OS_MASK BIT_MASK(GTHE3_CH_RX_TUNE_AFE_OS_MSB, GTHE3_CH_RX_TUNE_AFE_OS_LSB)
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#define GTHE3_CH_RX_DFE_KL_LPM_KL_CFG0_ADDR 0x008C
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#define GTHE3_CH_RX_DFE_KL_LPM_KL_CFG0_MSB 9
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#define GTHE3_CH_RX_DFE_KL_LPM_KL_CFG0_LSB 8
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#define GTHE3_CH_RX_DFE_KL_LPM_KL_CFG0_MASK BIT_MASK(GTHE3_CH_RX_DFE_KL_LPM_KL_CFG0_MSB, GTHE3_CH_RX_DFE_KL_LPM_KL_CFG0_LSB)
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#define GTHE3_CH_RX_DFE_KL_LPM_KL_CFG1_ADDR 0x008C
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#define GTHE3_CH_RX_DFE_KL_LPM_KL_CFG1_MSB 7
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#define GTHE3_CH_RX_DFE_KL_LPM_KL_CFG1_LSB 5
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#define GTHE3_CH_RX_DFE_KL_LPM_KL_CFG1_MASK BIT_MASK(GTHE3_CH_RX_DFE_KL_LPM_KL_CFG1_MSB, GTHE3_CH_RX_DFE_KL_LPM_KL_CFG1_LSB)
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#define GTHE3_CH_RXDFELPM_KL_CFG2_ADDR 0x008D
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#define GTHE3_CH_RXDFELPM_KL_CFG2_MSB 15
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#define GTHE3_CH_RXDFELPM_KL_CFG2_LSB 0
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#define GTHE3_CH_RXDFELPM_KL_CFG2_MASK BIT_MASK(GTHE3_CH_RXDFELPM_KL_CFG2_MSB, GTHE3_CH_RXDFELPM_KL_CFG2_LSB)
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#define GTHE3_CH_RXDFE_VP_CFG0_ADDR 0x008E
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#define GTHE3_CH_RXDFE_VP_CFG0_MSB 15
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#define GTHE3_CH_RXDFE_VP_CFG0_LSB 0
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#define GTHE3_CH_RXDFE_VP_CFG0_MASK BIT_MASK(GTHE3_CH_RXDFE_VP_CFG0_MSB, GTHE3_CH_RXDFE_VP_CFG0_LSB)
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#define GTHE3_CH_RXDFE_VP_CFG1_ADDR 0x008F
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#define GTHE3_CH_RXDFE_VP_CFG1_MSB 15
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#define GTHE3_CH_RXDFE_VP_CFG1_LSB 0
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#define GTHE3_CH_RXDFE_VP_CFG1_MASK BIT_MASK(GTHE3_CH_RXDFE_VP_CFG1_MSB, GTHE3_CH_RXDFE_VP_CFG1_LSB)
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#define GTHE3_CH_RXDFE_UT_CFG1_ADDR 0x0090
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#define GTHE3_CH_RXDFE_UT_CFG1_MSB 15
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#define GTHE3_CH_RXDFE_UT_CFG1_LSB 0
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#define GTHE3_CH_RXDFE_UT_CFG1_MASK BIT_MASK(GTHE3_CH_RXDFE_UT_CFG1_MSB, GTHE3_CH_RXDFE_UT_CFG1_LSB)
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#define GTHE3_CH_ADAPT_CFG0_ADDR 0x0091
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#define GTHE3_CH_ADAPT_CFG0_MSB 15
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#define GTHE3_CH_ADAPT_CFG0_LSB 0
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#define GTHE3_CH_ADAPT_CFG0_MASK BIT_MASK(GTHE3_CH_ADAPT_CFG0_MSB, GTHE3_CH_ADAPT_CFG0_LSB)
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#define GTHE3_CH_ADAPT_CFG1_ADDR 0x0092
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#define GTHE3_CH_ADAPT_CFG1_MSB 15
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#define GTHE3_CH_ADAPT_CFG1_LSB 0
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#define GTHE3_CH_ADAPT_CFG1_MASK BIT_MASK(GTHE3_CH_ADAPT_CFG1_MSB, GTHE3_CH_ADAPT_CFG1_LSB)
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#define GTHE3_CH_RXCFOK_CFG0_ADDR 0x0093
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#define GTHE3_CH_RXCFOK_CFG0_MSB 15
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#define GTHE3_CH_RXCFOK_CFG0_LSB 0
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#define GTHE3_CH_RXCFOK_CFG0_MASK BIT_MASK(GTHE3_CH_RXCFOK_CFG0_MSB, GTHE3_CH_RXCFOK_CFG0_LSB)
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#define GTHE3_CH_ES_CLK_PHASE_SEL_ADDR 0x0094
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#define GTHE3_CH_ES_CLK_PHASE_SEL_MSB 11
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#define GTHE3_CH_ES_CLK_PHASE_SEL_LSB 11
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#define GTHE3_CH_ES_CLK_PHASE_SEL_MASK BIT_MASK(GTHE3_CH_ES_CLK_PHASE_SEL_MSB, GTHE3_CH_ES_CLK_PHASE_SEL_LSB)
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#define GTHE3_CH_USE_PCS_CLK_PHASE_SEL_ADDR 0x0094
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#define GTHE3_CH_USE_PCS_CLK_PHASE_SEL_MSB 10
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#define GTHE3_CH_USE_PCS_CLK_PHASE_SEL_LSB 10
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#define GTHE3_CH_USE_PCS_CLK_PHASE_SEL_MASK BIT_MASK(GTHE3_CH_USE_PCS_CLK_PHASE_SEL_MSB, GTHE3_CH_USE_PCS_CLK_PHASE_SEL_LSB)
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#define GTHE3_CH_PMA_RSV1_ADDR 0x0095
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#define GTHE3_CH_PMA_RSV1_MSB 15
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#define GTHE3_CH_PMA_RSV1_LSB 0
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#define GTHE3_CH_PMA_RSV1_MASK BIT_MASK(GTHE3_CH_PMA_RSV1_MSB, GTHE3_CH_PMA_RSV1_LSB)
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#define GTHE3_CH_RX_AFE_CM_EN_ADDR 0x0097
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#define GTHE3_CH_RX_AFE_CM_EN_MSB 12
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#define GTHE3_CH_RX_AFE_CM_EN_LSB 12
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#define GTHE3_CH_RX_AFE_CM_EN_MASK BIT_MASK(GTHE3_CH_RX_AFE_CM_EN_MSB, GTHE3_CH_RX_AFE_CM_EN_LSB)
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#define GTHE3_CH_RX_CAPFF_SARC_ENB_ADDR 0x0097
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#define GTHE3_CH_RX_CAPFF_SARC_ENB_MSB 11
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#define GTHE3_CH_RX_CAPFF_SARC_ENB_LSB 11
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#define GTHE3_CH_RX_CAPFF_SARC_ENB_MASK BIT_MASK(GTHE3_CH_RX_CAPFF_SARC_ENB_MSB, GTHE3_CH_RX_CAPFF_SARC_ENB_LSB)
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#define GTHE3_CH_RX_EYESCAN_VS_NEG_DIR_ADDR 0x0097
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#define GTHE3_CH_RX_EYESCAN_VS_NEG_DIR_MSB 10
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#define GTHE3_CH_RX_EYESCAN_VS_NEG_DIR_LSB 10
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#define GTHE3_CH_RX_EYESCAN_VS_NEG_DIR_MASK BIT_MASK(GTHE3_CH_RX_EYESCAN_VS_NEG_DIR_MSB, GTHE3_CH_RX_EYESCAN_VS_NEG_DIR_LSB)
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#define GTHE3_CH_RX_EYESCAN_VS_UT_SIGN_ADDR 0x0097
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#define GTHE3_CH_RX_EYESCAN_VS_UT_SIGN_MSB 9
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#define GTHE3_CH_RX_EYESCAN_VS_UT_SIGN_LSB 9
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#define GTHE3_CH_RX_EYESCAN_VS_UT_SIGN_MASK BIT_MASK(GTHE3_CH_RX_EYESCAN_VS_UT_SIGN_MSB, GTHE3_CH_RX_EYESCAN_VS_UT_SIGN_LSB)
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#define GTHE3_CH_RX_EYESCAN_VS_CODE_ADDR 0x0097
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#define GTHE3_CH_RX_EYESCAN_VS_CODE_MSB 8
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#define GTHE3_CH_RX_EYESCAN_VS_CODE_LSB 2
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#define GTHE3_CH_RX_EYESCAN_VS_CODE_MASK BIT_MASK(GTHE3_CH_RX_EYESCAN_VS_CODE_MSB, GTHE3_CH_RX_EYESCAN_VS_CODE_LSB)
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#define GTHE3_CH_RX_EYESCAN_VS_RANGE_ADDR 0x0097
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#define GTHE3_CH_RX_EYESCAN_VS_RANGE_MSB 1
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#define GTHE3_CH_RX_EYESCAN_VS_RANGE_LSB 0
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#define GTHE3_CH_RX_EYESCAN_VS_RANGE_MASK BIT_MASK(GTHE3_CH_RX_EYESCAN_VS_RANGE_MSB, GTHE3_CH_RX_EYESCAN_VS_RANGE_LSB)
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#define GTHE3_CH_RXDFE_HE_CFG1_ADDR 0x0098
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#define GTHE3_CH_RXDFE_HE_CFG1_MSB 15
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#define GTHE3_CH_RXDFE_HE_CFG1_LSB 0
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#define GTHE3_CH_RXDFE_HE_CFG1_MASK BIT_MASK(GTHE3_CH_RXDFE_HE_CFG1_MSB, GTHE3_CH_RXDFE_HE_CFG1_LSB)
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#define GTHE3_CH_GEARBOX_MODE_ADDR 0x0099
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#define GTHE3_CH_GEARBOX_MODE_MSB 15
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#define GTHE3_CH_GEARBOX_MODE_LSB 11
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#define GTHE3_CH_GEARBOX_MODE_MASK BIT_MASK(GTHE3_CH_GEARBOX_MODE_MSB, GTHE3_CH_GEARBOX_MODE_LSB)
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#define GTHE3_CH_TXPI_SYNFREQ_PPM_ADDR 0x0099
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#define GTHE3_CH_TXPI_SYNFREQ_PPM_MSB 10
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#define GTHE3_CH_TXPI_SYNFREQ_PPM_LSB 8
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#define GTHE3_CH_TXPI_SYNFREQ_PPM_MASK BIT_MASK(GTHE3_CH_TXPI_SYNFREQ_PPM_MSB, GTHE3_CH_TXPI_SYNFREQ_PPM_LSB)
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#define GTHE3_CH_TXPI_PPMCLK_SEL_ADDR 0x0099
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#define GTHE3_CH_TXPI_PPMCLK_SEL_MSB 7
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#define GTHE3_CH_TXPI_PPMCLK_SEL_LSB 7
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#define GTHE3_CH_TXPI_PPMCLK_SEL_MASK BIT_MASK(GTHE3_CH_TXPI_PPMCLK_SEL_MSB, GTHE3_CH_TXPI_PPMCLK_SEL_LSB)
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#define GTHE3_CH_TXPI_PPMCLK_SEL_TXUSRCLK 0
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#define GTHE3_CH_TXPI_PPMCLK_SEL_TXUSRCLK2 1
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#define GTHE3_CH_TXPI_INVSTROBE_SEL_ADDR 0x0099
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#define GTHE3_CH_TXPI_INVSTROBE_SEL_MSB 6
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#define GTHE3_CH_TXPI_INVSTROBE_SEL_LSB 6
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#define GTHE3_CH_TXPI_INVSTROBE_SEL_MASK BIT_MASK(GTHE3_CH_TXPI_INVSTROBE_SEL_MSB, GTHE3_CH_TXPI_INVSTROBE_SEL_LSB)
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#define GTHE3_CH_TXPI_GRAY_SEL_ADDR 0x0099
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#define GTHE3_CH_TXPI_GRAY_SEL_MSB 5
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#define GTHE3_CH_TXPI_GRAY_SEL_LSB 5
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#define GTHE3_CH_TXPI_GRAY_SEL_MASK BIT_MASK(GTHE3_CH_TXPI_GRAY_SEL_MSB, GTHE3_CH_TXPI_GRAY_SEL_LSB)
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#define GTHE3_CH_TXPI_LPM_ADDR 0x0099
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#define GTHE3_CH_TXPI_LPM_MSB 3
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#define GTHE3_CH_TXPI_LPM_LSB 3
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#define GTHE3_CH_TXPI_LPM_MASK BIT_MASK(GTHE3_CH_TXPI_LPM_MSB, GTHE3_CH_TXPI_LPM_LSB)
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#define GTHE3_CH_TXPI_VREFSEL_ADDR 0x0099
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#define GTHE3_CH_TXPI_VREFSEL_MSB 2
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#define GTHE3_CH_TXPI_VREFSEL_LSB 2
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#define GTHE3_CH_TXPI_VREFSEL_MASK BIT_MASK(GTHE3_CH_TXPI_VREFSEL_MSB, GTHE3_CH_TXPI_VREFSEL_LSB)
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#define GTHE3_CH_TXPI_PPM_CFG_ADDR 0x009A
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#define GTHE3_CH_TXPI_PPM_CFG_MSB 7
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#define GTHE3_CH_TXPI_PPM_CFG_LSB 0
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#define GTHE3_CH_TXPI_PPM_CFG_MASK BIT_MASK(GTHE3_CH_TXPI_PPM_CFG_MSB, GTHE3_CH_TXPI_PPM_CFG_LSB)
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#define GTHE3_CH_RX_DFELPM_KLKH_AGC_STUP_EN_ADDR 0x009B
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#define GTHE3_CH_RX_DFELPM_KLKH_AGC_STUP_EN_MSB 15
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#define GTHE3_CH_RX_DFELPM_KLKH_AGC_STUP_EN_LSB 15
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#define GTHE3_CH_RX_DFELPM_KLKH_AGC_STUP_EN_MASK BIT_MASK(GTHE3_CH_RX_DFELPM_KLKH_AGC_STUP_EN_MSB, GTHE3_CH_RX_DFELPM_KLKH_AGC_STUP_EN_LSB)
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#define GTHE3_CH_RX_DFELPM_CFG0_ADDR 0x009B
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#define GTHE3_CH_RX_DFELPM_CFG0_MSB 14
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#define GTHE3_CH_RX_DFELPM_CFG0_LSB 11
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#define GTHE3_CH_RX_DFELPM_CFG0_MASK BIT_MASK(GTHE3_CH_RX_DFELPM_CFG0_MSB, GTHE3_CH_RX_DFELPM_CFG0_LSB)
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#define GTHE3_CH_RX_DFELPM_CFG1_ADDR 0x009B
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#define GTHE3_CH_RX_DFELPM_CFG1_MSB 10
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#define GTHE3_CH_RX_DFELPM_CFG1_LSB 10
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#define GTHE3_CH_RX_DFELPM_CFG1_MASK BIT_MASK(GTHE3_CH_RX_DFELPM_CFG1_MSB, GTHE3_CH_RX_DFELPM_CFG1_LSB)
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#define GTHE3_CH_RX_DFE_KL_LPM_KH_CFG0_ADDR 0x009B
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#define GTHE3_CH_RX_DFE_KL_LPM_KH_CFG0_MSB 9
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#define GTHE3_CH_RX_DFE_KL_LPM_KH_CFG0_LSB 8
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#define GTHE3_CH_RX_DFE_KL_LPM_KH_CFG0_MASK BIT_MASK(GTHE3_CH_RX_DFE_KL_LPM_KH_CFG0_MSB, GTHE3_CH_RX_DFE_KL_LPM_KH_CFG0_LSB)
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#define GTHE3_CH_RX_DFE_KL_LPM_KH_CFG1_ADDR 0x009B
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#define GTHE3_CH_RX_DFE_KL_LPM_KH_CFG1_MSB 7
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#define GTHE3_CH_RX_DFE_KL_LPM_KH_CFG1_LSB 5
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#define GTHE3_CH_RX_DFE_KL_LPM_KH_CFG1_MASK BIT_MASK(GTHE3_CH_RX_DFE_KL_LPM_KH_CFG1_MSB, GTHE3_CH_RX_DFE_KL_LPM_KH_CFG1_LSB)
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#define GTHE3_CH_TXPI_CFG0_ADDR 0x009C
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#define GTHE3_CH_TXPI_CFG0_MSB 12
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#define GTHE3_CH_TXPI_CFG0_LSB 11
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#define GTHE3_CH_TXPI_CFG0_MASK BIT_MASK(GTHE3_CH_TXPI_CFG0_MSB, GTHE3_CH_TXPI_CFG0_LSB)
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#define GTHE3_CH_TXPI_CFG1_ADDR 0x009C
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#define GTHE3_CH_TXPI_CFG1_MSB 10
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#define GTHE3_CH_TXPI_CFG1_LSB 9
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#define GTHE3_CH_TXPI_CFG1_MASK BIT_MASK(GTHE3_CH_TXPI_CFG1_MSB, GTHE3_CH_TXPI_CFG1_LSB)
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#define GTHE3_CH_TXPI_CFG2_ADDR 0x009C
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#define GTHE3_CH_TXPI_CFG2_MSB 8
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#define GTHE3_CH_TXPI_CFG2_LSB 7
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#define GTHE3_CH_TXPI_CFG2_MASK BIT_MASK(GTHE3_CH_TXPI_CFG2_MSB, GTHE3_CH_TXPI_CFG2_LSB)
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#define GTHE3_CH_TXPI_CFG3_ADDR 0x009C
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#define GTHE3_CH_TXPI_CFG3_MSB 6
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#define GTHE3_CH_TXPI_CFG3_LSB 6
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#define GTHE3_CH_TXPI_CFG3_MASK BIT_MASK(GTHE3_CH_TXPI_CFG3_MSB, GTHE3_CH_TXPI_CFG3_LSB)
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#define GTHE3_CH_TXPI_CFG4_ADDR 0x009C
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#define GTHE3_CH_TXPI_CFG4_MSB 5
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#define GTHE3_CH_TXPI_CFG4_LSB 5
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#define GTHE3_CH_TXPI_CFG4_MASK BIT_MASK(GTHE3_CH_TXPI_CFG4_MSB, GTHE3_CH_TXPI_CFG4_LSB)
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#define GTHE3_CH_TXPI_CFG5_ADDR 0x009C
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#define GTHE3_CH_TXPI_CFG5_MSB 4
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#define GTHE3_CH_TXPI_CFG5_LSB 2
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#define GTHE3_CH_TXPI_CFG5_MASK BIT_MASK(GTHE3_CH_TXPI_CFG5_MSB, GTHE3_CH_TXPI_CFG5_LSB)
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#define GTHE3_CH_RXPI_CFG1_ADDR 0x009D
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#define GTHE3_CH_RXPI_CFG1_MSB 15
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#define GTHE3_CH_RXPI_CFG1_LSB 14
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#define GTHE3_CH_RXPI_CFG1_MASK BIT_MASK(GTHE3_CH_RXPI_CFG1_MSB, GTHE3_CH_RXPI_CFG1_LSB)
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#define GTHE3_CH_RXPI_CFG2_ADDR 0x009D
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#define GTHE3_CH_RXPI_CFG2_MSB 13
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#define GTHE3_CH_RXPI_CFG2_LSB 12
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#define GTHE3_CH_RXPI_CFG2_MASK BIT_MASK(GTHE3_CH_RXPI_CFG2_MSB, GTHE3_CH_RXPI_CFG2_LSB)
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#define GTHE3_CH_RXPI_CFG3_ADDR 0x009D
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#define GTHE3_CH_RXPI_CFG3_MSB 11
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#define GTHE3_CH_RXPI_CFG3_LSB 10
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#define GTHE3_CH_RXPI_CFG3_MASK BIT_MASK(GTHE3_CH_RXPI_CFG3_MSB, GTHE3_CH_RXPI_CFG3_LSB)
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#define GTHE3_CH_RXPI_CFG4_ADDR 0x009D
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#define GTHE3_CH_RXPI_CFG4_MSB 9
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#define GTHE3_CH_RXPI_CFG4_LSB 9
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#define GTHE3_CH_RXPI_CFG4_MASK BIT_MASK(GTHE3_CH_RXPI_CFG4_MSB, GTHE3_CH_RXPI_CFG4_LSB)
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#define GTHE3_CH_RXPI_CFG5_ADDR 0x009D
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#define GTHE3_CH_RXPI_CFG5_MSB 8
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#define GTHE3_CH_RXPI_CFG5_LSB 8
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#define GTHE3_CH_RXPI_CFG5_MASK BIT_MASK(GTHE3_CH_RXPI_CFG5_MSB, GTHE3_CH_RXPI_CFG5_LSB)
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#define GTHE3_CH_RXPI_CFG6_ADDR 0x009D
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#define GTHE3_CH_RXPI_CFG6_MSB 7
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#define GTHE3_CH_RXPI_CFG6_LSB 5
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#define GTHE3_CH_RXPI_CFG6_MASK BIT_MASK(GTHE3_CH_RXPI_CFG6_MSB, GTHE3_CH_RXPI_CFG6_LSB)
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#define GTHE3_CH_RXPI_CFG0_ADDR 0x009D
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#define GTHE3_CH_RXPI_CFG0_MSB 4
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#define GTHE3_CH_RXPI_CFG0_LSB 3
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#define GTHE3_CH_RXPI_CFG0_MASK BIT_MASK(GTHE3_CH_RXPI_CFG0_MSB, GTHE3_CH_RXPI_CFG0_LSB)
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#define GTHE3_CH_RXDFE_UT_CFG0_ADDR 0x009E
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#define GTHE3_CH_RXDFE_UT_CFG0_MSB 15
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#define GTHE3_CH_RXDFE_UT_CFG0_LSB 0
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#define GTHE3_CH_RXDFE_UT_CFG0_MASK BIT_MASK(GTHE3_CH_RXDFE_UT_CFG0_MSB, GTHE3_CH_RXDFE_UT_CFG0_LSB)
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#define GTHE3_CH_RXDFE_GC_CFG0_ADDR 0x009F
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#define GTHE3_CH_RXDFE_GC_CFG0_MSB 15
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#define GTHE3_CH_RXDFE_GC_CFG0_LSB 0
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#define GTHE3_CH_RXDFE_GC_CFG0_MASK BIT_MASK(GTHE3_CH_RXDFE_GC_CFG0_MSB, GTHE3_CH_RXDFE_GC_CFG0_LSB)
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#define GTHE3_CH_RXDFE_GC_CFG1_ADDR 0x00A0
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#define GTHE3_CH_RXDFE_GC_CFG1_MSB 15
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#define GTHE3_CH_RXDFE_GC_CFG1_LSB 0
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#define GTHE3_CH_RXDFE_GC_CFG1_MASK BIT_MASK(GTHE3_CH_RXDFE_GC_CFG1_MSB, GTHE3_CH_RXDFE_GC_CFG1_LSB)
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#define GTHE3_CH_RXDFE_GC_CFG2_ADDR 0x00A1
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#define GTHE3_CH_RXDFE_GC_CFG2_MSB 15
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#define GTHE3_CH_RXDFE_GC_CFG2_LSB 0
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#define GTHE3_CH_RXDFE_GC_CFG2_MASK BIT_MASK(GTHE3_CH_RXDFE_GC_CFG2_MSB, GTHE3_CH_RXDFE_GC_CFG2_LSB)
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#define GTHE3_CH_RXCDR_CFG0_GEN3_ADDR 0x00A2
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#define GTHE3_CH_RXCDR_CFG0_GEN3_MSB 15
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#define GTHE3_CH_RXCDR_CFG0_GEN3_LSB 0
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#define GTHE3_CH_RXCDR_CFG0_GEN3_MASK BIT_MASK(GTHE3_CH_RXCDR_CFG0_GEN3_MSB, GTHE3_CH_RXCDR_CFG0_GEN3_LSB)
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#define GTHE3_CH_RXCDR_CFG1_GEN3_ADDR 0x00A3
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#define GTHE3_CH_RXCDR_CFG1_GEN3_MSB 15
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#define GTHE3_CH_RXCDR_CFG1_GEN3_LSB 0
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#define GTHE3_CH_RXCDR_CFG1_GEN3_MASK BIT_MASK(GTHE3_CH_RXCDR_CFG1_GEN3_MSB, GTHE3_CH_RXCDR_CFG1_GEN3_LSB)
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#define GTHE3_CH_RXCDR_CFG2_GEN3_ADDR 0x00A4
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#define GTHE3_CH_RXCDR_CFG2_GEN3_MSB 15
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#define GTHE3_CH_RXCDR_CFG2_GEN3_LSB 0
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#define GTHE3_CH_RXCDR_CFG2_GEN3_MASK BIT_MASK(GTHE3_CH_RXCDR_CFG2_GEN3_MSB, GTHE3_CH_RXCDR_CFG2_GEN3_LSB)
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#define GTHE3_CH_RXCDR_CFG3_GEN3_ADDR 0x00A5
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#define GTHE3_CH_RXCDR_CFG3_GEN3_MSB 15
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#define GTHE3_CH_RXCDR_CFG3_GEN3_LSB 0
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#define GTHE3_CH_RXCDR_CFG3_GEN3_MASK BIT_MASK(GTHE3_CH_RXCDR_CFG3_GEN3_MSB, GTHE3_CH_RXCDR_CFG3_GEN3_LSB)
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#define GTHE3_CH_RXCDR_CFG4_GEN3_ADDR 0x00A6
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#define GTHE3_CH_RXCDR_CFG4_GEN3_MSB 15
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#define GTHE3_CH_RXCDR_CFG4_GEN3_LSB 0
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#define GTHE3_CH_RXCDR_CFG4_GEN3_MASK BIT_MASK(GTHE3_CH_RXCDR_CFG4_GEN3_MSB, GTHE3_CH_RXCDR_CFG4_GEN3_LSB)
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#define GTHE3_CH_RXCDR_CFG5_GEN3_ADDR 0x00A7
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#define GTHE3_CH_RXCDR_CFG5_GEN3_MSB 15
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#define GTHE3_CH_RXCDR_CFG5_GEN3_LSB 0
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#define GTHE3_CH_RXCDR_CFG5_GEN3_MASK BIT_MASK(GTHE3_CH_RXCDR_CFG5_GEN3_MSB, GTHE3_CH_RXCDR_CFG5_GEN3_LSB)
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#define GTHE3_CH_RXCDR_CFG5_ADDR 0x00A8
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#define GTHE3_CH_RXCDR_CFG5_MSB 15
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#define GTHE3_CH_RXCDR_CFG5_LSB 0
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#define GTHE3_CH_RXCDR_CFG5_MASK BIT_MASK(GTHE3_CH_RXCDR_CFG5_MSB, GTHE3_CH_RXCDR_CFG5_LSB)
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#define GTHE3_CH_PCIE_RXPMA_CFG_ADDR 0x00A9
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#define GTHE3_CH_PCIE_RXPMA_CFG_MSB 15
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#define GTHE3_CH_PCIE_RXPMA_CFG_LSB 0
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#define GTHE3_CH_PCIE_RXPMA_CFG_MASK BIT_MASK(GTHE3_CH_PCIE_RXPMA_CFG_MSB, GTHE3_CH_PCIE_RXPMA_CFG_LSB)
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#define GTHE3_CH_PCIE_TXPCS_CFG_GEN3_ADDR 0x00AA
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#define GTHE3_CH_PCIE_TXPCS_CFG_GEN3_MSB 15
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#define GTHE3_CH_PCIE_TXPCS_CFG_GEN3_LSB 0
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#define GTHE3_CH_PCIE_TXPCS_CFG_GEN3_MASK BIT_MASK(GTHE3_CH_PCIE_TXPCS_CFG_GEN3_MSB, GTHE3_CH_PCIE_TXPCS_CFG_GEN3_LSB)
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#define GTHE3_CH_PCIE_TXPMA_CFG_ADDR 0x00AB
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#define GTHE3_CH_PCIE_TXPMA_CFG_MSB 15
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#define GTHE3_CH_PCIE_TXPMA_CFG_LSB 0
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#define GTHE3_CH_PCIE_TXPMA_CFG_MASK BIT_MASK(GTHE3_CH_PCIE_TXPMA_CFG_MSB, GTHE3_CH_PCIE_TXPMA_CFG_LSB)
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#define GTHE3_CH_RX_CLK_SLIP_OVRD_ADDR 0x00AC
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#define GTHE3_CH_RX_CLK_SLIP_OVRD_MSB 7
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#define GTHE3_CH_RX_CLK_SLIP_OVRD_LSB 3
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#define GTHE3_CH_RX_CLK_SLIP_OVRD_MASK BIT_MASK(GTHE3_CH_RX_CLK_SLIP_OVRD_MSB, GTHE3_CH_RX_CLK_SLIP_OVRD_LSB)
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#define GTHE3_CH_PCS_RSVD1_ADDR 0x00AC
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#define GTHE3_CH_PCS_RSVD1_MSB 2
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#define GTHE3_CH_PCS_RSVD1_LSB 0
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#define GTHE3_CH_PCS_RSVD1_MASK BIT_MASK(GTHE3_CH_PCS_RSVD1_MSB, GTHE3_CH_PCS_RSVD1_LSB)
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#define GTHE3_CH_PLL_SEL_MODE_GEN3_ADDR 0x00AD
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#define GTHE3_CH_PLL_SEL_MODE_GEN3_MSB 12
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#define GTHE3_CH_PLL_SEL_MODE_GEN3_LSB 11
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#define GTHE3_CH_PLL_SEL_MODE_GEN3_MASK BIT_MASK(GTHE3_CH_PLL_SEL_MODE_GEN3_MSB, GTHE3_CH_PLL_SEL_MODE_GEN3_LSB)
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#define GTHE3_CH_PLL_SEL_MODE_GEN12_ADDR 0x00AD
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#define GTHE3_CH_PLL_SEL_MODE_GEN12_MSB 10
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#define GTHE3_CH_PLL_SEL_MODE_GEN12_LSB 9
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#define GTHE3_CH_PLL_SEL_MODE_GEN12_MASK BIT_MASK(GTHE3_CH_PLL_SEL_MODE_GEN12_MSB, GTHE3_CH_PLL_SEL_MODE_GEN12_LSB)
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#define GTHE3_CH_RATE_SW_USE_DRP_ADDR 0x00AD
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#define GTHE3_CH_RATE_SW_USE_DRP_MSB 8
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#define GTHE3_CH_RATE_SW_USE_DRP_LSB 8
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#define GTHE3_CH_RATE_SW_USE_DRP_MASK BIT_MASK(GTHE3_CH_RATE_SW_USE_DRP_MSB, GTHE3_CH_RATE_SW_USE_DRP_LSB)
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#define GTHE3_CH_RXPI_LPM_ADDR 0x00AD
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#define GTHE3_CH_RXPI_LPM_MSB 3
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#define GTHE3_CH_RXPI_LPM_LSB 3
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#define GTHE3_CH_RXPI_LPM_MASK BIT_MASK(GTHE3_CH_RXPI_LPM_MSB, GTHE3_CH_RXPI_LPM_LSB)
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#define GTHE3_CH_RXPI_VREFSEL_ADDR 0x00AD
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#define GTHE3_CH_RXPI_VREFSEL_MSB 2
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#define GTHE3_CH_RXPI_VREFSEL_LSB 2
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#define GTHE3_CH_RXPI_VREFSEL_MASK BIT_MASK(GTHE3_CH_RXPI_VREFSEL_MSB, GTHE3_CH_RXPI_VREFSEL_LSB)
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#define GTHE3_CH_RXDFE_H3_CFG0_ADDR 0x00AE
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#define GTHE3_CH_RXDFE_H3_CFG0_MSB 15
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#define GTHE3_CH_RXDFE_H3_CFG0_LSB 0
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#define GTHE3_CH_RXDFE_H3_CFG0_MASK BIT_MASK(GTHE3_CH_RXDFE_H3_CFG0_MSB, GTHE3_CH_RXDFE_H3_CFG0_LSB)
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#define GTHE3_CH_DFE_D_X_REL_POS_ADDR 0x00AF
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#define GTHE3_CH_DFE_D_X_REL_POS_MSB 15
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#define GTHE3_CH_DFE_D_X_REL_POS_LSB 15
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#define GTHE3_CH_DFE_D_X_REL_POS_MASK BIT_MASK(GTHE3_CH_DFE_D_X_REL_POS_MSB, GTHE3_CH_DFE_D_X_REL_POS_LSB)
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#define GTHE3_CH_DFE_VCM_COMP_EN_ADDR 0x00AF
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#define GTHE3_CH_DFE_VCM_COMP_EN_MSB 14
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#define GTHE3_CH_DFE_VCM_COMP_EN_LSB 14
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#define GTHE3_CH_DFE_VCM_COMP_EN_MASK BIT_MASK(GTHE3_CH_DFE_VCM_COMP_EN_MSB, GTHE3_CH_DFE_VCM_COMP_EN_LSB)
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#define GTHE3_CH_GM_BIAS_SELECT_ADDR 0x00AF
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#define GTHE3_CH_GM_BIAS_SELECT_MSB 13
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#define GTHE3_CH_GM_BIAS_SELECT_LSB 13
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#define GTHE3_CH_GM_BIAS_SELECT_MASK BIT_MASK(GTHE3_CH_GM_BIAS_SELECT_MSB, GTHE3_CH_GM_BIAS_SELECT_LSB)
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#define GTHE3_CH_EVODD_PHI_CFG_ADDR 0x00AF
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#define GTHE3_CH_EVODD_PHI_CFG_MSB 10
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#define GTHE3_CH_EVODD_PHI_CFG_LSB 0
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#define GTHE3_CH_EVODD_PHI_CFG_MASK BIT_MASK(GTHE3_CH_EVODD_PHI_CFG_MSB, GTHE3_CH_EVODD_PHI_CFG_LSB)
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#define GTHE3_CH_RXDFE_H3_CFG1_ADDR 0x00B0
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#define GTHE3_CH_RXDFE_H3_CFG1_MSB 15
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#define GTHE3_CH_RXDFE_H3_CFG1_LSB 0
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#define GTHE3_CH_RXDFE_H3_CFG1_MASK BIT_MASK(GTHE3_CH_RXDFE_H3_CFG1_MSB, GTHE3_CH_RXDFE_H3_CFG1_LSB)
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#define GTHE3_CH_RXDFE_H4_CFG0_ADDR 0x00B1
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#define GTHE3_CH_RXDFE_H4_CFG0_MSB 15
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#define GTHE3_CH_RXDFE_H4_CFG0_LSB 0
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#define GTHE3_CH_RXDFE_H4_CFG0_MASK BIT_MASK(GTHE3_CH_RXDFE_H4_CFG0_MSB, GTHE3_CH_RXDFE_H4_CFG0_LSB)
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#define GTHE3_CH_RXDFE_H4_CFG1_ADDR 0x00B2
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#define GTHE3_CH_RXDFE_H4_CFG1_MSB 15
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#define GTHE3_CH_RXDFE_H4_CFG1_LSB 0
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#define GTHE3_CH_RXDFE_H4_CFG1_MASK BIT_MASK(GTHE3_CH_RXDFE_H4_CFG1_MSB, GTHE3_CH_RXDFE_H4_CFG1_LSB)
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#define GTHE3_CH_RXDFE_H5_CFG0_ADDR 0x00B3
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#define GTHE3_CH_RXDFE_H5_CFG0_MSB 15
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#define GTHE3_CH_RXDFE_H5_CFG0_LSB 0
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#define GTHE3_CH_RXDFE_H5_CFG0_MASK BIT_MASK(GTHE3_CH_RXDFE_H5_CFG0_MSB, GTHE3_CH_RXDFE_H5_CFG0_LSB)
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#define GTHE3_CH_PROCESS_PAR_ADDR 0x00B4
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#define GTHE3_CH_PROCESS_PAR_MSB 15
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#define GTHE3_CH_PROCESS_PAR_LSB 13
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#define GTHE3_CH_PROCESS_PAR_MASK BIT_MASK(GTHE3_CH_PROCESS_PAR_MSB, GTHE3_CH_PROCESS_PAR_LSB)
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#define GTHE3_CH_TEMPERATUR_PAR_ADDR 0x00B4
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#define GTHE3_CH_TEMPERATUR_PAR_MSB 11
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#define GTHE3_CH_TEMPERATUR_PAR_LSB 8
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#define GTHE3_CH_TEMPERATUR_PAR_MASK BIT_MASK(GTHE3_CH_TEMPERATUR_PAR_MSB, GTHE3_CH_TEMPERATUR_PAR_LSB)
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#define GTHE3_CH_TX_MODE_SEL_ADDR 0x00B4
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#define GTHE3_CH_TX_MODE_SEL_MSB 7
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#define GTHE3_CH_TX_MODE_SEL_LSB 5
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#define GTHE3_CH_TX_MODE_SEL_MASK BIT_MASK(GTHE3_CH_TX_MODE_SEL_MSB, GTHE3_CH_TX_MODE_SEL_LSB)
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#define GTHE3_CH_TX_SARC_LPBK_ENB_ADDR 0x00B4
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#define GTHE3_CH_TX_SARC_LPBK_ENB_MSB 4
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#define GTHE3_CH_TX_SARC_LPBK_ENB_LSB 4
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#define GTHE3_CH_TX_SARC_LPBK_ENB_MASK BIT_MASK(GTHE3_CH_TX_SARC_LPBK_ENB_MSB, GTHE3_CH_TX_SARC_LPBK_ENB_LSB)
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#define GTHE3_CH_RXDFE_H5_CFG1_ADDR 0x00B5
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#define GTHE3_CH_RXDFE_H5_CFG1_MSB 15
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#define GTHE3_CH_RXDFE_H5_CFG1_LSB 0
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#define GTHE3_CH_RXDFE_H5_CFG1_MASK BIT_MASK(GTHE3_CH_RXDFE_H5_CFG1_MSB, GTHE3_CH_RXDFE_H5_CFG1_LSB)
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#define GTHE3_CH_TX_DCD_CFG_ADDR 0x00B6
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#define GTHE3_CH_TX_DCD_CFG_MSB 15
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#define GTHE3_CH_TX_DCD_CFG_LSB 10
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#define GTHE3_CH_TX_DCD_CFG_MASK BIT_MASK(GTHE3_CH_TX_DCD_CFG_MSB, GTHE3_CH_TX_DCD_CFG_LSB)
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#define GTHE3_CH_TX_DCD_EN_ADDR 0x00B6
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#define GTHE3_CH_TX_DCD_EN_MSB 9
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#define GTHE3_CH_TX_DCD_EN_LSB 9
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#define GTHE3_CH_TX_DCD_EN_MASK BIT_MASK(GTHE3_CH_TX_DCD_EN_MSB, GTHE3_CH_TX_DCD_EN_LSB)
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#define GTHE3_CH_TX_EML_PHI_TUNE_ADDR 0x00B6
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#define GTHE3_CH_TX_EML_PHI_TUNE_MSB 8
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#define GTHE3_CH_TX_EML_PHI_TUNE_LSB 8
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#define GTHE3_CH_TX_EML_PHI_TUNE_MASK BIT_MASK(GTHE3_CH_TX_EML_PHI_TUNE_MSB, GTHE3_CH_TX_EML_PHI_TUNE_LSB)
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#define GTHE3_CH_CPLL_CFG3_ADDR 0x00B6
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#define GTHE3_CH_CPLL_CFG3_MSB 5
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#define GTHE3_CH_CPLL_CFG3_LSB 0
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#define GTHE3_CH_CPLL_CFG3_MASK BIT_MASK(GTHE3_CH_CPLL_CFG3_MSB, GTHE3_CH_CPLL_CFG3_LSB)
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#define GTHE3_CH_RXDFE_H6_CFG0_ADDR 0x00B7
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#define GTHE3_CH_RXDFE_H6_CFG0_MSB 15
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#define GTHE3_CH_RXDFE_H6_CFG0_LSB 0
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#define GTHE3_CH_RXDFE_H6_CFG0_MASK BIT_MASK(GTHE3_CH_RXDFE_H6_CFG0_MSB, GTHE3_CH_RXDFE_H6_CFG0_LSB)
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#define GTHE3_CH_RXDFE_H6_CFG1_ADDR 0x00B8
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#define GTHE3_CH_RXDFE_H6_CFG1_MSB 15
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#define GTHE3_CH_RXDFE_H6_CFG1_LSB 0
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#define GTHE3_CH_RXDFE_H6_CFG1_MASK BIT_MASK(GTHE3_CH_RXDFE_H6_CFG1_MSB, GTHE3_CH_RXDFE_H6_CFG1_LSB)
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#define GTHE3_CH_RXDFE_H7_CFG0_ADDR 0x00B9
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#define GTHE3_CH_RXDFE_H7_CFG0_MSB 15
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#define GTHE3_CH_RXDFE_H7_CFG0_LSB 0
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#define GTHE3_CH_RXDFE_H7_CFG0_MASK BIT_MASK(GTHE3_CH_RXDFE_H7_CFG0_MSB, GTHE3_CH_RXDFE_H7_CFG0_LSB)
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#define GTHE3_CH_DDI_REALIGN_WAIT_ADDR 0x00BA
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#define GTHE3_CH_DDI_REALIGN_WAIT_MSB 6
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#define GTHE3_CH_DDI_REALIGN_WAIT_LSB 2
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#define GTHE3_CH_DDI_REALIGN_WAIT_MASK BIT_MASK(GTHE3_CH_DDI_REALIGN_WAIT_MSB, GTHE3_CH_DDI_REALIGN_WAIT_LSB)
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#define GTHE3_CH_DDI_CTRL_ADDR 0x00BA
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#define GTHE3_CH_DDI_CTRL_MSB 1
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#define GTHE3_CH_DDI_CTRL_LSB 0
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#define GTHE3_CH_DDI_CTRL_MASK BIT_MASK(GTHE3_CH_DDI_CTRL_MSB, GTHE3_CH_DDI_CTRL_LSB)
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#define GTHE3_CH_TXGBOX_FIFO_INIT_RD_ADDR_ADDR 0x00BB
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#define GTHE3_CH_TXGBOX_FIFO_INIT_RD_ADDR_MSB 11
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#define GTHE3_CH_TXGBOX_FIFO_INIT_RD_ADDR_LSB 9
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#define GTHE3_CH_TXGBOX_FIFO_INIT_RD_ADDR_MASK BIT_MASK(GTHE3_CH_TXGBOX_FIFO_INIT_RD_ADDR_MSB, GTHE3_CH_TXGBOX_FIFO_INIT_RD_ADDR_LSB)
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#define GTHE3_CH_TX_SAMPLE_PERIOD_ADDR 0x00BB
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#define GTHE3_CH_TX_SAMPLE_PERIOD_MSB 8
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#define GTHE3_CH_TX_SAMPLE_PERIOD_LSB 6
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#define GTHE3_CH_TX_SAMPLE_PERIOD_MASK BIT_MASK(GTHE3_CH_TX_SAMPLE_PERIOD_MSB, GTHE3_CH_TX_SAMPLE_PERIOD_LSB)
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#define GTHE3_CH_RXGBOX_FIFO_INIT_RD_ADDR_ADDR 0x00BB
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#define GTHE3_CH_RXGBOX_FIFO_INIT_RD_ADDR_MSB 5
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#define GTHE3_CH_RXGBOX_FIFO_INIT_RD_ADDR_LSB 3
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#define GTHE3_CH_RXGBOX_FIFO_INIT_RD_ADDR_MASK BIT_MASK(GTHE3_CH_RXGBOX_FIFO_INIT_RD_ADDR_MSB, GTHE3_CH_RXGBOX_FIFO_INIT_RD_ADDR_LSB)
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#define GTHE3_CH_RX_SAMPLE_PERIOD_ADDR 0x00BB
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#define GTHE3_CH_RX_SAMPLE_PERIOD_MSB 2
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#define GTHE3_CH_RX_SAMPLE_PERIOD_LSB 0
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#define GTHE3_CH_RX_SAMPLE_PERIOD_MASK BIT_MASK(GTHE3_CH_RX_SAMPLE_PERIOD_MSB, GTHE3_CH_RX_SAMPLE_PERIOD_LSB)
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#define GTHE3_CH_CPLL_CFG2_ADDR 0x00BC
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#define GTHE3_CH_CPLL_CFG2_MSB 15
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#define GTHE3_CH_CPLL_CFG2_LSB 0
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#define GTHE3_CH_CPLL_CFG2_MASK BIT_MASK(GTHE3_CH_CPLL_CFG2_MSB, GTHE3_CH_CPLL_CFG2_LSB)
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#define GTHE3_CH_RXPHSAMP_CFG_ADDR 0x00BD
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#define GTHE3_CH_RXPHSAMP_CFG_MSB 15
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#define GTHE3_CH_RXPHSAMP_CFG_LSB 0
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#define GTHE3_CH_RXPHSAMP_CFG_MASK BIT_MASK(GTHE3_CH_RXPHSAMP_CFG_MSB, GTHE3_CH_RXPHSAMP_CFG_LSB)
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#define GTHE3_CH_RXPHSLIP_CFG_ADDR 0x00BE
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#define GTHE3_CH_RXPHSLIP_CFG_MSB 15
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#define GTHE3_CH_RXPHSLIP_CFG_LSB 0
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#define GTHE3_CH_RXPHSLIP_CFG_MASK BIT_MASK(GTHE3_CH_RXPHSLIP_CFG_MSB, GTHE3_CH_RXPHSLIP_CFG_LSB)
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#define GTHE3_CH_RXPHBEACON_CFG_ADDR 0x00BF
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#define GTHE3_CH_RXPHBEACON_CFG_MSB 15
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#define GTHE3_CH_RXPHBEACON_CFG_LSB 0
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#define GTHE3_CH_RXPHBEACON_CFG_MASK BIT_MASK(GTHE3_CH_RXPHBEACON_CFG_MSB, GTHE3_CH_RXPHBEACON_CFG_LSB)
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#define GTHE3_CH_RXDFE_H7_CFG1_ADDR 0x00C0
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#define GTHE3_CH_RXDFE_H7_CFG1_MSB 15
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#define GTHE3_CH_RXDFE_H7_CFG1_LSB 0
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#define GTHE3_CH_RXDFE_H7_CFG1_MASK BIT_MASK(GTHE3_CH_RXDFE_H7_CFG1_MSB, GTHE3_CH_RXDFE_H7_CFG1_LSB)
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#define GTHE3_CH_RXDFE_H8_CFG0_ADDR 0x00C1
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#define GTHE3_CH_RXDFE_H8_CFG0_MSB 15
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#define GTHE3_CH_RXDFE_H8_CFG0_LSB 0
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#define GTHE3_CH_RXDFE_H8_CFG0_MASK BIT_MASK(GTHE3_CH_RXDFE_H8_CFG0_MSB, GTHE3_CH_RXDFE_H8_CFG0_LSB)
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#define GTHE3_CH_RXDFE_H8_CFG1_ADDR 0x00C2
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#define GTHE3_CH_RXDFE_H8_CFG1_MSB 15
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#define GTHE3_CH_RXDFE_H8_CFG1_LSB 0
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#define GTHE3_CH_RXDFE_H8_CFG1_MASK BIT_MASK(GTHE3_CH_RXDFE_H8_CFG1_MSB, GTHE3_CH_RXDFE_H8_CFG1_LSB)
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#define GTHE3_CH_PCIE_BUFG_DIV_CTRL_ADDR 0x00C3
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#define GTHE3_CH_PCIE_BUFG_DIV_CTRL_MSB 15
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#define GTHE3_CH_PCIE_BUFG_DIV_CTRL_LSB 0
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#define GTHE3_CH_PCIE_BUFG_DIV_CTRL_MASK BIT_MASK(GTHE3_CH_PCIE_BUFG_DIV_CTRL_MSB, GTHE3_CH_PCIE_BUFG_DIV_CTRL_LSB)
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#define GTHE3_CH_PCIE_RXPCS_CFG_GEN3_ADDR 0x00C4
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#define GTHE3_CH_PCIE_RXPCS_CFG_GEN3_MSB 15
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#define GTHE3_CH_PCIE_RXPCS_CFG_GEN3_LSB 0
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#define GTHE3_CH_PCIE_RXPCS_CFG_GEN3_MASK BIT_MASK(GTHE3_CH_PCIE_RXPCS_CFG_GEN3_MSB, GTHE3_CH_PCIE_RXPCS_CFG_GEN3_LSB)
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#define GTHE3_CH_RXDFE_H9_CFG0_ADDR 0x00C5
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#define GTHE3_CH_RXDFE_H9_CFG0_MSB 15
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#define GTHE3_CH_RXDFE_H9_CFG0_LSB 0
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#define GTHE3_CH_RXDFE_H9_CFG0_MASK BIT_MASK(GTHE3_CH_RXDFE_H9_CFG0_MSB, GTHE3_CH_RXDFE_H9_CFG0_LSB)
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#define GTHE3_CH_RX_PROGDIV_CFG_ADDR 0x00C6
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#define GTHE3_CH_RX_PROGDIV_CFG_MSB 15
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#define GTHE3_CH_RX_PROGDIV_CFG_LSB 0
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#define GTHE3_CH_RX_PROGDIV_CFG_MASK BIT_MASK(GTHE3_CH_RX_PROGDIV_CFG_MSB, GTHE3_CH_RX_PROGDIV_CFG_LSB)
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#define GTHE3_CH_RX_PROGDIV_CFG_0 32768
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#define GTHE3_CH_RX_PROGDIV_CFG_4 57744
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#define GTHE3_CH_RX_PROGDIV_CFG_5 49648
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#define GTHE3_CH_RX_PROGDIV_CFG_8 57728
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#define GTHE3_CH_RX_PROGDIV_CFG_10 57760
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#define GTHE3_CH_RX_PROGDIV_CFG_16 57730
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#define GTHE3_CH_RX_PROGDIV_CFG_16P5 49672
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#define GTHE3_CH_RX_PROGDIV_CFG_20 57762
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#define GTHE3_CH_RX_PROGDIV_CFG_32 57734
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#define GTHE3_CH_RX_PROGDIV_CFG_33 49800
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#define GTHE3_CH_RX_PROGDIV_CFG_40 57766
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#define GTHE3_CH_RX_PROGDIV_CFG_64 57742
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#define GTHE3_CH_RX_PROGDIV_CFG_66 50056
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#define GTHE3_CH_RX_PROGDIV_CFG_80 57743
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#define GTHE3_CH_RX_PROGDIV_CFG_100 57775
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#define GTHE3_CH_RXDFE_H9_CFG1_ADDR 0x00C7
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#define GTHE3_CH_RXDFE_H9_CFG1_MSB 15
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#define GTHE3_CH_RXDFE_H9_CFG1_LSB 0
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#define GTHE3_CH_RXDFE_H9_CFG1_MASK BIT_MASK(GTHE3_CH_RXDFE_H9_CFG1_MSB, GTHE3_CH_RXDFE_H9_CFG1_LSB)
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#define GTHE3_CH_RXDFE_HA_CFG0_ADDR 0x00C8
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#define GTHE3_CH_RXDFE_HA_CFG0_MSB 15
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#define GTHE3_CH_RXDFE_HA_CFG0_LSB 0
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#define GTHE3_CH_RXDFE_HA_CFG0_MASK BIT_MASK(GTHE3_CH_RXDFE_HA_CFG0_MSB, GTHE3_CH_RXDFE_HA_CFG0_LSB)
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#define GTHE3_CH_CHAN_BOND_SEQ_1_2_ADDR 0x00CA
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#define GTHE3_CH_CHAN_BOND_SEQ_1_2_MSB 9
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#define GTHE3_CH_CHAN_BOND_SEQ_1_2_LSB 0
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#define GTHE3_CH_CHAN_BOND_SEQ_1_2_MASK BIT_MASK(GTHE3_CH_CHAN_BOND_SEQ_1_2_MSB, GTHE3_CH_CHAN_BOND_SEQ_1_2_LSB)
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#define GTHE3_CH_CPLL_CFG0_ADDR 0x00CB
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#define GTHE3_CH_CPLL_CFG0_MSB 15
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#define GTHE3_CH_CPLL_CFG0_LSB 0
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#define GTHE3_CH_CPLL_CFG0_MASK BIT_MASK(GTHE3_CH_CPLL_CFG0_MSB, GTHE3_CH_CPLL_CFG0_LSB)
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#define GTHE3_CH_CPLL_CFG1_ADDR 0x00CC
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#define GTHE3_CH_CPLL_CFG1_MSB 15
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#define GTHE3_CH_CPLL_CFG1_LSB 0
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#define GTHE3_CH_CPLL_CFG1_MASK BIT_MASK(GTHE3_CH_CPLL_CFG1_MSB, GTHE3_CH_CPLL_CFG1_LSB)
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#define GTHE3_CH_CPLL_INIT_CFG1_ADDR 0x00CD
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#define GTHE3_CH_CPLL_INIT_CFG1_MSB 15
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#define GTHE3_CH_CPLL_INIT_CFG1_LSB 8
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#define GTHE3_CH_CPLL_INIT_CFG1_MASK BIT_MASK(GTHE3_CH_CPLL_INIT_CFG1_MSB, GTHE3_CH_CPLL_INIT_CFG1_LSB)
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#define GTHE3_CH_RX_DDI_SEL_ADDR 0x00CD
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#define GTHE3_CH_RX_DDI_SEL_MSB 7
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#define GTHE3_CH_RX_DDI_SEL_LSB 2
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#define GTHE3_CH_RX_DDI_SEL_MASK BIT_MASK(GTHE3_CH_RX_DDI_SEL_MSB, GTHE3_CH_RX_DDI_SEL_LSB)
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#define GTHE3_CH_DEC_VALID_COMMA_ONLY_ADDR 0x00CD
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#define GTHE3_CH_DEC_VALID_COMMA_ONLY_MSB 1
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#define GTHE3_CH_DEC_VALID_COMMA_ONLY_LSB 1
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#define GTHE3_CH_DEC_VALID_COMMA_ONLY_MASK BIT_MASK(GTHE3_CH_DEC_VALID_COMMA_ONLY_MSB, GTHE3_CH_DEC_VALID_COMMA_ONLY_LSB)
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#define GTHE3_CH_DEC_MCOMMA_DETECT_ADDR 0x00CD
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#define GTHE3_CH_DEC_MCOMMA_DETECT_MSB 0
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#define GTHE3_CH_DEC_MCOMMA_DETECT_LSB 0
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#define GTHE3_CH_DEC_MCOMMA_DETECT_MASK BIT_MASK(GTHE3_CH_DEC_MCOMMA_DETECT_MSB, GTHE3_CH_DEC_MCOMMA_DETECT_LSB)
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#define GTHE3_CH_RXDFE_HA_CFG1_ADDR 0x00CE
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#define GTHE3_CH_RXDFE_HA_CFG1_MSB 15
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#define GTHE3_CH_RXDFE_HA_CFG1_LSB 0
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#define GTHE3_CH_RXDFE_HA_CFG1_MASK BIT_MASK(GTHE3_CH_RXDFE_HA_CFG1_MSB, GTHE3_CH_RXDFE_HA_CFG1_LSB)
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#define GTHE3_CH_RXDFE_HB_CFG0_ADDR 0x00CF
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#define GTHE3_CH_RXDFE_HB_CFG0_MSB 15
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#define GTHE3_CH_RXDFE_HB_CFG0_LSB 0
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#define GTHE3_CH_RXDFE_HB_CFG0_MASK BIT_MASK(GTHE3_CH_RXDFE_HB_CFG0_MSB, GTHE3_CH_RXDFE_HB_CFG0_LSB)
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#define GTHE3_CH_COMMA_ALIGN_LATENCY_ADDR 0x0150
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#define GTHE3_CH_COMMA_ALIGN_LATENCY_MSB 6
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#define GTHE3_CH_COMMA_ALIGN_LATENCY_LSB 0
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#define GTHE3_CH_COMMA_ALIGN_LATENCY_MASK BIT_MASK(GTHE3_CH_COMMA_ALIGN_LATENCY_MSB, GTHE3_CH_COMMA_ALIGN_LATENCY_LSB)
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#define GTHE3_CH_ES_ERROR_COUNT_ADDR 0x0151
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#define GTHE3_CH_ES_ERROR_COUNT_MSB 15
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#define GTHE3_CH_ES_ERROR_COUNT_LSB 0
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#define GTHE3_CH_ES_ERROR_COUNT_MASK BIT_MASK(GTHE3_CH_ES_ERROR_COUNT_MSB, GTHE3_CH_ES_ERROR_COUNT_LSB)
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#define GTHE3_CH_ES_SAMPLE_COUNT_ADDR 0x0152
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#define GTHE3_CH_ES_SAMPLE_COUNT_MSB 15
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#define GTHE3_CH_ES_SAMPLE_COUNT_LSB 0
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#define GTHE3_CH_ES_SAMPLE_COUNT_MASK BIT_MASK(GTHE3_CH_ES_SAMPLE_COUNT_MSB, GTHE3_CH_ES_SAMPLE_COUNT_LSB)
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#define GTHE3_CH_ES_CONTROL_STATUS_ADDR 0x0153
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#define GTHE3_CH_ES_CONTROL_STATUS_MSB 3
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#define GTHE3_CH_ES_CONTROL_STATUS_LSB 0
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#define GTHE3_CH_ES_CONTROL_STATUS_MASK BIT_MASK(GTHE3_CH_ES_CONTROL_STATUS_MSB, GTHE3_CH_ES_CONTROL_STATUS_LSB)
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#define GTHE3_CH_ES_RDATA_BYTE4_ADDR 0x0154
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#define GTHE3_CH_ES_RDATA_BYTE4_MSB 15
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#define GTHE3_CH_ES_RDATA_BYTE4_LSB 0
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#define GTHE3_CH_ES_RDATA_BYTE4_MASK BIT_MASK(GTHE3_CH_ES_RDATA_BYTE4_MSB, GTHE3_CH_ES_RDATA_BYTE4_LSB)
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#define GTHE3_CH_ES_RDATA_BYTE3_ADDR 0x0155
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#define GTHE3_CH_ES_RDATA_BYTE3_MSB 15
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#define GTHE3_CH_ES_RDATA_BYTE3_LSB 0
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#define GTHE3_CH_ES_RDATA_BYTE3_MASK BIT_MASK(GTHE3_CH_ES_RDATA_BYTE3_MSB, GTHE3_CH_ES_RDATA_BYTE3_LSB)
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#define GTHE3_CH_ES_RDATA_BYTE2_ADDR 0x0156
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#define GTHE3_CH_ES_RDATA_BYTE2_MSB 15
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#define GTHE3_CH_ES_RDATA_BYTE2_LSB 0
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#define GTHE3_CH_ES_RDATA_BYTE2_MASK BIT_MASK(GTHE3_CH_ES_RDATA_BYTE2_MSB, GTHE3_CH_ES_RDATA_BYTE2_LSB)
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#define GTHE3_CH_ES_RDATA_BYTE1_ADDR 0x0157
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#define GTHE3_CH_ES_RDATA_BYTE1_MSB 15
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#define GTHE3_CH_ES_RDATA_BYTE1_LSB 0
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#define GTHE3_CH_ES_RDATA_BYTE1_MASK BIT_MASK(GTHE3_CH_ES_RDATA_BYTE1_MSB, GTHE3_CH_ES_RDATA_BYTE1_LSB)
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#define GTHE3_CH_ES_RDATA_BYTE0_ADDR 0x0158
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#define GTHE3_CH_ES_RDATA_BYTE0_MSB 15
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#define GTHE3_CH_ES_RDATA_BYTE0_LSB 0
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#define GTHE3_CH_ES_RDATA_BYTE0_MASK BIT_MASK(GTHE3_CH_ES_RDATA_BYTE0_MSB, GTHE3_CH_ES_RDATA_BYTE0_LSB)
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#define GTHE3_CH_ES_SDATA_BYTE4_ADDR 0x0159
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#define GTHE3_CH_ES_SDATA_BYTE4_MSB 15
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#define GTHE3_CH_ES_SDATA_BYTE4_LSB 0
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#define GTHE3_CH_ES_SDATA_BYTE4_MASK BIT_MASK(GTHE3_CH_ES_SDATA_BYTE4_MSB, GTHE3_CH_ES_SDATA_BYTE4_LSB)
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#define GTHE3_CH_ES_SDATA_BYTE3_ADDR 0x015A
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#define GTHE3_CH_ES_SDATA_BYTE3_MSB 15
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#define GTHE3_CH_ES_SDATA_BYTE3_LSB 0
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#define GTHE3_CH_ES_SDATA_BYTE3_MASK BIT_MASK(GTHE3_CH_ES_SDATA_BYTE3_MSB, GTHE3_CH_ES_SDATA_BYTE3_LSB)
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#define GTHE3_CH_ES_SDATA_BYTE2_ADDR 0x015B
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#define GTHE3_CH_ES_SDATA_BYTE2_MSB 15
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#define GTHE3_CH_ES_SDATA_BYTE2_LSB 0
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#define GTHE3_CH_ES_SDATA_BYTE2_MASK BIT_MASK(GTHE3_CH_ES_SDATA_BYTE2_MSB, GTHE3_CH_ES_SDATA_BYTE2_LSB)
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#define GTHE3_CH_ES_SDATA_BYTE1_ADDR 0x015C
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#define GTHE3_CH_ES_SDATA_BYTE1_MSB 15
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#define GTHE3_CH_ES_SDATA_BYTE1_LSB 0
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#define GTHE3_CH_ES_SDATA_BYTE1_MASK BIT_MASK(GTHE3_CH_ES_SDATA_BYTE1_MSB, GTHE3_CH_ES_SDATA_BYTE1_LSB)
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#define GTHE3_CH_ES_SDATA_BYTE0_ADDR 0x015D
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#define GTHE3_CH_ES_SDATA_BYTE0_MSB 15
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#define GTHE3_CH_ES_SDATA_BYTE0_LSB 0
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#define GTHE3_CH_ES_SDATA_BYTE0_MASK BIT_MASK(GTHE3_CH_ES_SDATA_BYTE0_MSB, GTHE3_CH_ES_SDATA_BYTE0_LSB)
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#define GTHE3_CH_RX_PRBS_ERR_CNT_L_ADDR 0x015E
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#define GTHE3_CH_RX_PRBS_ERR_CNT_L_MSB 15
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#define GTHE3_CH_RX_PRBS_ERR_CNT_L_LSB 0
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#define GTHE3_CH_RX_PRBS_ERR_CNT_L_MASK BIT_MASK(GTHE3_CH_RX_PRBS_ERR_CNT_L_MSB, GTHE3_CH_RX_PRBS_ERR_CNT_L_LSB)
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#define GTHE3_CH_RX_PRBS_ERR_CNT_H_ADDR 0x015F
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#define GTHE3_CH_RX_PRBS_ERR_CNT_H_MSB 15
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#define GTHE3_CH_RX_PRBS_ERR_CNT_H_LSB 0
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#define GTHE3_CH_RX_PRBS_ERR_CNT_H_MASK BIT_MASK(GTHE3_CH_RX_PRBS_ERR_CNT_H_MSB, GTHE3_CH_RX_PRBS_ERR_CNT_H_LSB)
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#define GTHE3_CH_TXGBOX_FIFO_LATENCY_ADDR 0x0163
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#define GTHE3_CH_TXGBOX_FIFO_LATENCY_MSB 15
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#define GTHE3_CH_TXGBOX_FIFO_LATENCY_LSB 0
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#define GTHE3_CH_TXGBOX_FIFO_LATENCY_MASK BIT_MASK(GTHE3_CH_TXGBOX_FIFO_LATENCY_MSB, GTHE3_CH_TXGBOX_FIFO_LATENCY_LSB)
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#define GTHE3_CH_RXGBOX_FIFO_LATENCY_ADDR 0x0169
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#define GTHE3_CH_RXGBOX_FIFO_LATENCY_MSB 15
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#define GTHE3_CH_RXGBOX_FIFO_LATENCY_LSB 0
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#define GTHE3_CH_RXGBOX_FIFO_LATENCY_MASK BIT_MASK(GTHE3_CH_RXGBOX_FIFO_LATENCY_MSB, GTHE3_CH_RXGBOX_FIFO_LATENCY_LSB)
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#endif /* GTHE3_REGS_H */
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