mirror of
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489 lines
22 KiB
C
489 lines
22 KiB
C
/*
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Copyright 2019, The Regents of the University of California.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
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IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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The views and conclusions contained in the software and documentation are those
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of the authors and should not be interpreted as representing official policies,
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either expressed or implied, of The Regents of the University of California.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <mqnic/mqnic.h>
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static void usage(char *name)
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{
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fprintf(stderr,
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"usage: %s [options]\n"
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" -d name device to open (/dev/mqnic0)\n"
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" -i number interface\n"
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" -P number port\n",
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name);
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}
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int main(int argc, char *argv[])
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{
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char *name;
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int opt;
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int ret = 0;
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char *device = NULL;
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struct mqnic *dev;
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int interface = 0;
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int port = 0;
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int sched_block = 0;
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name = strrchr(argv[0], '/');
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name = name ? 1+name : argv[0];
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while ((opt = getopt(argc, argv, "d:i:P:h?")) != EOF)
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{
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switch (opt)
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{
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case 'd':
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device = optarg;
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break;
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case 'i':
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interface = atoi(optarg);
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break;
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case 'P':
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port = atoi(optarg);
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break;
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case 'h':
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case '?':
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usage(name);
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return 0;
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default:
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usage(name);
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return -1;
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}
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}
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if (!device)
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{
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fprintf(stderr, "Device not specified\n");
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usage(name);
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return -1;
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}
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dev = mqnic_open(device);
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if (!dev)
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{
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fprintf(stderr, "Failed to open device\n");
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return -1;
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}
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if (dev->pci_device_path[0])
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{
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char *ptr = strrchr(dev->pci_device_path, '/');
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if (ptr)
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printf("PCIe ID: %s\n", ptr+1);
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}
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printf("Control region size: %lu\n", dev->regs_size);
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if (dev->app_regs_size)
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printf("Application region size: %lu\n", dev->app_regs_size);
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if (dev->ram_size)
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printf("RAM region size: %lu\n", dev->ram_size);
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printf("Device-level register blocks:\n");
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for (struct mqnic_reg_block *rb = dev->rb_list; rb->regs; rb++)
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printf(" type 0x%08x (v %d.%d.%d.%d)\n", rb->type, rb->version >> 24,
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(rb->version >> 16) & 0xff, (rb->version >> 8) & 0xff, rb->version & 0xff);
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mqnic_print_fw_id(dev);
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printf("IF offset: 0x%08x\n", dev->if_offset);
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printf("IF count: %d\n", dev->if_count);
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printf("IF stride: 0x%08x\n", dev->if_stride);
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printf("IF CSR offset: 0x%08x\n", dev->if_csr_offset);
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if (dev->phc_rb)
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{
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int ch;
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uint32_t ns;
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uint32_t fns;
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printf("PHC time: %ld.%09d s\n", mqnic_reg_read32(dev->phc_rb->regs, MQNIC_RB_PHC_REG_CUR_SEC_L) +
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(((int64_t)mqnic_reg_read32(dev->phc_rb->regs, MQNIC_RB_PHC_REG_CUR_SEC_H)) << 32),
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mqnic_reg_read32(dev->phc_rb->regs, MQNIC_RB_PHC_REG_CUR_NS));
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ns = mqnic_reg_read32(dev->phc_rb->regs, MQNIC_RB_PHC_REG_PERIOD_NS);
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fns = mqnic_reg_read32(dev->phc_rb->regs, MQNIC_RB_PHC_REG_PERIOD_FNS);
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printf("PHC period: %d.%09ld ns (raw 0x%x ns 0x%08x fns)\n", ns, ((uint64_t)fns * 1000000000) >> 32, ns, fns);
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ns = mqnic_reg_read32(dev->phc_rb->regs, MQNIC_RB_PHC_REG_NOM_PERIOD_NS);
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fns = mqnic_reg_read32(dev->phc_rb->regs, MQNIC_RB_PHC_REG_NOM_PERIOD_FNS);
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printf("PHC nom period: %d.%09ld ns (raw 0x%x ns 0x%08x fns)\n", ns, ((uint64_t)fns * 1000000000) >> 32, ns, fns);
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ch = 0;
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for (struct mqnic_reg_block *rb = dev->rb_list; rb->regs; rb++)
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{
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if (rb->type == MQNIC_RB_PHC_PEROUT_TYPE && rb->version == MQNIC_RB_PHC_PEROUT_VER)
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{
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printf("PHC perout ch %d ctrl: 0x%08x\n", ch, mqnic_reg_read32(rb->regs, MQNIC_RB_PHC_PEROUT_REG_CTRL));
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printf("PHC perout ch %d start: %ld.%09d s\n", ch, mqnic_reg_read32(rb->regs, MQNIC_RB_PHC_PEROUT_REG_START_SEC_L) +
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(((int64_t)mqnic_reg_read32(rb->regs, MQNIC_RB_PHC_PEROUT_REG_START_SEC_H)) << 32),
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mqnic_reg_read32(rb->regs, MQNIC_RB_PHC_PEROUT_REG_START_NS));
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printf("PHC perout ch %d period: %ld.%09d s\n", ch, mqnic_reg_read32(rb->regs, MQNIC_RB_PHC_PEROUT_REG_PERIOD_SEC_L) +
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(((int64_t)mqnic_reg_read32(rb->regs, MQNIC_RB_PHC_PEROUT_REG_PERIOD_SEC_H)) << 32),
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mqnic_reg_read32(rb->regs, MQNIC_RB_PHC_PEROUT_REG_PERIOD_NS));
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printf("PHC perout ch %d width: %ld.%09d s\n", ch, mqnic_reg_read32(rb->regs, MQNIC_RB_PHC_PEROUT_REG_WIDTH_SEC_L) +
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(((int64_t)mqnic_reg_read32(rb->regs, MQNIC_RB_PHC_PEROUT_REG_WIDTH_SEC_H)) << 32),
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mqnic_reg_read32(rb->regs, MQNIC_RB_PHC_PEROUT_REG_WIDTH_NS));
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ch++;
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}
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}
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}
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if (dev->clk_info_rb)
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{
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uint32_t num;
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uint32_t denom;
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uint32_t ns;
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uint32_t fns;
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uint32_t mhz;
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uint32_t hz;
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num = dev->ref_clk_nom_per_ns_num;
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denom = dev->ref_clk_nom_per_ns_denom;
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ns = num/denom;
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fns = ((num-ns*denom)*1000000000ull)/denom;
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printf("Ref clock nominal period: %d.%09d ns (raw %d/%d ns)\n", ns, fns, num, denom);
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hz = mqnic_get_ref_clk_nom_freq_hz(dev);
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mhz = hz / 1000000;
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hz = hz - (mhz * 1000000);
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printf("Ref clock nominal freq: %d.%06d MHz\n", mhz, hz);
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num = dev->core_clk_nom_per_ns_num;
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denom = dev->core_clk_nom_per_ns_denom;
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ns = num/denom;
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fns = ((num-ns*denom)*1000000000ull)/denom;
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printf("Core clock nominal period: %d.%09d ns (raw %d/%d ns)\n", ns, fns, num, denom);
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hz = mqnic_get_core_clk_nom_freq_hz(dev);
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mhz = hz / 1000000;
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hz = hz - (mhz * 1000000);
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printf("Core clock nominal freq: %d.%06d MHz\n", mhz, hz);
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hz = mqnic_get_core_clk_freq_hz(dev);
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mhz = hz / 1000000;
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hz = hz - (mhz * 1000000);
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printf("Core clock freq: %d.%06d MHz\n", mhz, hz);
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for (int ch = 0; ch < dev->clk_info_channels; ch++)
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{
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hz = mqnic_get_clk_freq_hz(dev, ch);
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mhz = hz / 1000000;
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hz = hz - (mhz * 1000000);
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printf("CH%d: clock freq: %d.%06d MHz\n", ch, mhz, hz);
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}
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}
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if (interface < 0 || interface >= dev->if_count)
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{
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fprintf(stderr, "Interface out of range\n");
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ret = -1;
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goto err;
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}
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struct mqnic_if *dev_interface = dev->interfaces[interface];
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if (!dev_interface)
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{
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fprintf(stderr, "Invalid interface\n");
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ret = -1;
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goto err;
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}
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printf("Interface-level register blocks:\n");
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for (struct mqnic_reg_block *rb = dev_interface->rb_list; rb->regs; rb++)
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printf(" type 0x%08x (v %d.%d.%d.%d)\n", rb->type, rb->version >> 24,
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(rb->version >> 16) & 0xff, (rb->version >> 8) & 0xff, rb->version & 0xff);
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printf("IF features: 0x%08x\n", dev_interface->if_features);
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printf("Port count: %d\n", dev_interface->port_count);
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printf("Scheduler block count: %d\n", dev_interface->sched_block_count);
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printf("Max TX MTU: %d\n", dev_interface->max_tx_mtu);
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printf("Max RX MTU: %d\n", dev_interface->max_rx_mtu);
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printf("TX MTU: %d\n", mqnic_interface_get_tx_mtu(dev_interface));
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printf("RX MTU: %d\n", mqnic_interface_get_rx_mtu(dev_interface));
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printf("Event queue offset: 0x%08x\n", dev_interface->event_queue_offset);
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printf("Event queue count: %d\n", dev_interface->event_queue_count);
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printf("Event queue stride: 0x%08x\n", dev_interface->event_queue_stride);
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printf("TX queue offset: 0x%08x\n", dev_interface->tx_queue_offset);
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printf("TX queue count: %d\n", dev_interface->tx_queue_count);
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printf("TX queue stride: 0x%08x\n", dev_interface->tx_queue_stride);
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printf("TX completion queue offset: 0x%08x\n", dev_interface->tx_cpl_queue_offset);
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printf("TX completion queue count: %d\n", dev_interface->tx_cpl_queue_count);
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printf("TX completion queue stride: 0x%08x\n", dev_interface->tx_cpl_queue_stride);
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printf("RX queue offset: 0x%08x\n", dev_interface->rx_queue_offset);
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printf("RX queue count: %d\n", dev_interface->rx_queue_count);
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printf("RX queue stride: 0x%08x\n", dev_interface->rx_queue_stride);
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printf("RX completion queue offset: 0x%08x\n", dev_interface->rx_cpl_queue_offset);
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printf("RX completion queue count: %d\n", dev_interface->rx_cpl_queue_count);
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printf("RX completion queue stride: 0x%08x\n", dev_interface->rx_cpl_queue_stride);
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for (int k = 0; k < dev_interface->port_count; k++)
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{
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printf("Port %d RX queue map offset: %d\n", k, mqnic_interface_get_rx_queue_map_offset(dev_interface, k));
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printf("Port %d RX queue map RSS mask: 0x%08x\n", k, mqnic_interface_get_rx_queue_map_rss_mask(dev_interface, k));
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printf("Port %d RX queue map app mask: 0x%08x\n", k, mqnic_interface_get_rx_queue_map_app_mask(dev_interface, k));
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}
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if (port < 0 || port >= dev_interface->port_count)
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{
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fprintf(stderr, "Port out of range\n");
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ret = -1;
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goto err;
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}
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struct mqnic_port *dev_port = dev_interface->ports[port];
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if (!dev_port)
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{
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fprintf(stderr, "Invalid port\n");
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ret = -1;
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goto err;
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}
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printf("Port-level register blocks:\n");
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for (struct mqnic_reg_block *rb = dev_port->rb_list; rb->regs; rb++)
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printf(" type 0x%08x (v %d.%d.%d.%d)\n", rb->type, rb->version >> 24,
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(rb->version >> 16) & 0xff, (rb->version >> 8) & 0xff, rb->version & 0xff);
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printf("Port features: 0x%08x\n", dev_port->port_features);
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printf("Port TX status: 0x%08x\n", mqnic_port_get_tx_status(dev_port));
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printf("Port RX status: 0x%08x\n", mqnic_port_get_rx_status(dev_port));
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sched_block = port;
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if (sched_block < 0 || sched_block >= dev_interface->sched_block_count)
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{
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fprintf(stderr, "Scheduler block out of range\n");
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ret = -1;
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goto err;
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}
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struct mqnic_sched_block *dev_sched_block = dev_interface->sched_blocks[sched_block];
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if (!dev_sched_block)
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{
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fprintf(stderr, "Invalid scheduler block\n");
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ret = -1;
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goto err;
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}
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printf("Scheduler block-level register blocks:\n");
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for (struct mqnic_reg_block *rb = dev_sched_block->rb_list; rb->regs; rb++)
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printf(" type 0x%08x (v %d.%d.%d.%d)\n", rb->type, rb->version >> 24,
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(rb->version >> 16) & 0xff, (rb->version >> 8) & 0xff, rb->version & 0xff);
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printf("Sched count: %d\n", dev_sched_block->sched_count);
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for (struct mqnic_reg_block *rb = dev_sched_block->rb_list; rb->regs; rb++)
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{
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if (rb->type == MQNIC_RB_SCHED_RR_TYPE && rb->version == MQNIC_RB_SCHED_RR_VER)
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{
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printf("Round-robin scheduler\n");
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printf("Sched channel count: %d\n", mqnic_reg_read32(rb->regs, MQNIC_RB_SCHED_RR_REG_CH_COUNT));
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printf("Sched channel stride: %d\n", mqnic_reg_read32(rb->regs, MQNIC_RB_SCHED_RR_REG_CH_STRIDE));
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printf("Sched control: %d\n", mqnic_reg_read32(rb->regs, MQNIC_RB_SCHED_RR_REG_CTRL));
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printf("Sched dest: %d\n", mqnic_reg_read32(rb->regs, MQNIC_RB_SCHED_RR_REG_DEST));
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}
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else if (rb->type == MQNIC_RB_SCHED_CTRL_TDMA_TYPE && rb->version == MQNIC_RB_SCHED_CTRL_TDMA_VER)
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{
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printf("TDMA scheduler controller\n");
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printf("Sched channel count: %d\n", mqnic_reg_read32(rb->regs, MQNIC_RB_SCHED_CTRL_TDMA_REG_CH_COUNT));
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printf("Sched channel stride: %d\n", mqnic_reg_read32(rb->regs, MQNIC_RB_SCHED_CTRL_TDMA_REG_CH_STRIDE));
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printf("Sched control: %d\n", mqnic_reg_read32(rb->regs, MQNIC_RB_SCHED_CTRL_TDMA_REG_CTRL));
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printf("Sched timeslot count: %d\n", mqnic_reg_read32(rb->regs, MQNIC_RB_SCHED_CTRL_TDMA_REG_TS_COUNT));
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}
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else if (rb->type == MQNIC_RB_TDMA_SCH_TYPE && rb->version == MQNIC_RB_TDMA_SCH_VER)
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{
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printf("TDMA scheduler\n");
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printf("TDMA timeslot count: %d\n", mqnic_reg_read32(rb->regs, MQNIC_RB_TDMA_SCH_REG_TS_COUNT));
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printf("TDMA control: 0x%08x\n", mqnic_reg_read32(rb->regs, MQNIC_RB_TDMA_SCH_REG_CTRL));
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printf("TDMA status: 0x%08x\n", mqnic_reg_read32(rb->regs, MQNIC_RB_TDMA_SCH_REG_STATUS));
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printf("TDMA schedule start: %ld.%09d s\n", mqnic_reg_read32(rb->regs, MQNIC_RB_TDMA_SCH_REG_SCH_START_SEC_L) +
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(((int64_t)mqnic_reg_read32(rb->regs, MQNIC_RB_TDMA_SCH_REG_SCH_START_SEC_H)) << 32),
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mqnic_reg_read32(rb->regs, MQNIC_RB_TDMA_SCH_REG_SCH_START_NS));
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printf("TDMA schedule period: %ld.%09d s\n", mqnic_reg_read32(rb->regs, MQNIC_RB_TDMA_SCH_REG_SCH_PERIOD_SEC_L) +
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(((int64_t)mqnic_reg_read32(rb->regs, MQNIC_RB_TDMA_SCH_REG_SCH_PERIOD_SEC_H)) << 32),
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mqnic_reg_read32(rb->regs, MQNIC_RB_TDMA_SCH_REG_SCH_PERIOD_NS));
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printf("TDMA timeslot period: %ld.%09d s\n", mqnic_reg_read32(rb->regs, MQNIC_RB_TDMA_SCH_REG_TS_PERIOD_SEC_L) +
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(((int64_t)mqnic_reg_read32(rb->regs, MQNIC_RB_TDMA_SCH_REG_TS_PERIOD_SEC_H)) << 32),
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mqnic_reg_read32(rb->regs, MQNIC_RB_TDMA_SCH_REG_TS_PERIOD_NS));
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printf("TDMA active period: %ld.%09d s\n", mqnic_reg_read32(rb->regs, MQNIC_RB_TDMA_SCH_REG_ACTIVE_PERIOD_SEC_L) +
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(((int64_t)mqnic_reg_read32(rb->regs, MQNIC_RB_TDMA_SCH_REG_ACTIVE_PERIOD_SEC_H)) << 32),
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mqnic_reg_read32(rb->regs, MQNIC_RB_TDMA_SCH_REG_ACTIVE_PERIOD_NS));
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}
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}
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printf("TX queue info\n");
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printf(" Queue Base Address E B LS CPL Head Tail Len\n");
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for (int k = 0; k < dev_interface->tx_queue_count; k++)
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{
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volatile uint8_t *base = dev_interface->regs+dev_interface->tx_queue_offset+k*dev_interface->tx_queue_stride;
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uint64_t base_addr = (uint64_t)mqnic_reg_read32(base, MQNIC_QUEUE_BASE_ADDR_REG) + ((uint64_t)mqnic_reg_read32(base, MQNIC_QUEUE_BASE_ADDR_REG+4) << 32);
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uint8_t active = (mqnic_reg_read32(base, MQNIC_QUEUE_ACTIVE_LOG_SIZE_REG) & MQNIC_QUEUE_ACTIVE_MASK) != 0;
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uint8_t log_desc_block_size = (mqnic_reg_read32(base, MQNIC_QUEUE_ACTIVE_LOG_SIZE_REG) >> 8) & 0xff;
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uint8_t log_queue_size = mqnic_reg_read32(base, MQNIC_QUEUE_ACTIVE_LOG_SIZE_REG) & 0xff;
|
|
uint32_t cpl_queue_index = mqnic_reg_read32(base, MQNIC_QUEUE_CPL_QUEUE_INDEX_REG);
|
|
uint32_t head_ptr = mqnic_reg_read32(base, MQNIC_QUEUE_HEAD_PTR_REG);
|
|
uint32_t tail_ptr = mqnic_reg_read32(base, MQNIC_QUEUE_TAIL_PTR_REG);
|
|
uint32_t occupancy = (head_ptr - tail_ptr) & 0xffff;
|
|
|
|
printf("TXQ %4d 0x%016lx %d %d %2d %4d %6d %6d %6d\n", k, base_addr, active, log_desc_block_size, log_queue_size, cpl_queue_index, head_ptr, tail_ptr, occupancy);
|
|
}
|
|
|
|
printf("TX completion queue info\n");
|
|
printf(" Queue Base Address E LS A C Int Head Tail Len\n");
|
|
for (int k = 0; k < dev_interface->tx_queue_count; k++)
|
|
{
|
|
volatile uint8_t *base = dev_interface->regs+dev_interface->tx_cpl_queue_offset+k*dev_interface->tx_cpl_queue_stride;
|
|
|
|
uint64_t base_addr = (uint64_t)mqnic_reg_read32(base, MQNIC_CPL_QUEUE_BASE_ADDR_REG) + ((uint64_t)mqnic_reg_read32(base, MQNIC_CPL_QUEUE_BASE_ADDR_REG+4) << 32);
|
|
uint8_t active = (mqnic_reg_read32(base, MQNIC_CPL_QUEUE_ACTIVE_LOG_SIZE_REG) & MQNIC_CPL_QUEUE_ACTIVE_MASK) != 0;
|
|
uint8_t log_queue_size = mqnic_reg_read32(base, MQNIC_CPL_QUEUE_ACTIVE_LOG_SIZE_REG) & 0xff;
|
|
uint8_t armed = (mqnic_reg_read32(base, MQNIC_CPL_QUEUE_INTERRUPT_INDEX_REG) & MQNIC_CPL_QUEUE_ARM_MASK) != 0;
|
|
uint8_t continuous = (mqnic_reg_read32(base, MQNIC_CPL_QUEUE_INTERRUPT_INDEX_REG) & MQNIC_CPL_QUEUE_CONT_MASK) != 0;
|
|
uint32_t interrupt_index = mqnic_reg_read32(base, MQNIC_CPL_QUEUE_INTERRUPT_INDEX_REG) & 0xffff;
|
|
uint32_t head_ptr = mqnic_reg_read32(base, MQNIC_CPL_QUEUE_HEAD_PTR_REG);
|
|
uint32_t tail_ptr = mqnic_reg_read32(base, MQNIC_CPL_QUEUE_TAIL_PTR_REG);
|
|
uint32_t occupancy = (head_ptr - tail_ptr) & 0xffff;
|
|
|
|
printf("TXCQ %4d 0x%016lx %d %2d %d %d %4d %6d %6d %6d\n", k, base_addr, active, log_queue_size, armed, continuous, interrupt_index, head_ptr, tail_ptr, occupancy);
|
|
}
|
|
|
|
printf("RX queue info\n");
|
|
printf(" Queue Base Address E B LS CPL Head Tail Len\n");
|
|
for (int k = 0; k < dev_interface->rx_queue_count; k++)
|
|
{
|
|
volatile uint8_t *base = dev_interface->regs+dev_interface->rx_queue_offset+k*dev_interface->rx_queue_stride;
|
|
|
|
uint64_t base_addr = (uint64_t)mqnic_reg_read32(base, MQNIC_QUEUE_BASE_ADDR_REG) + ((uint64_t)mqnic_reg_read32(base, MQNIC_QUEUE_BASE_ADDR_REG+4) << 32);
|
|
uint8_t active = (mqnic_reg_read32(base, MQNIC_QUEUE_ACTIVE_LOG_SIZE_REG) & MQNIC_QUEUE_ACTIVE_MASK) != 0;
|
|
uint8_t log_desc_block_size = (mqnic_reg_read32(base, MQNIC_QUEUE_ACTIVE_LOG_SIZE_REG) >> 8) & 0xff;
|
|
uint8_t log_queue_size = mqnic_reg_read32(base, MQNIC_QUEUE_ACTIVE_LOG_SIZE_REG) & 0xff;
|
|
uint32_t cpl_queue_index = mqnic_reg_read32(base, MQNIC_QUEUE_CPL_QUEUE_INDEX_REG);
|
|
uint32_t head_ptr = mqnic_reg_read32(base, MQNIC_QUEUE_HEAD_PTR_REG);
|
|
uint32_t tail_ptr = mqnic_reg_read32(base, MQNIC_QUEUE_TAIL_PTR_REG);
|
|
uint32_t occupancy = (head_ptr - tail_ptr) & 0xffff;
|
|
|
|
printf("RXQ %4d 0x%016lx %d %d %2d %4d %6d %6d %6d\n", k, base_addr, active, log_desc_block_size, log_queue_size, cpl_queue_index, head_ptr, tail_ptr, occupancy);
|
|
}
|
|
|
|
printf("RX completion queue info\n");
|
|
printf(" Queue Base Address E LS A C Int Head Tail Len\n");
|
|
for (int k = 0; k < dev_interface->rx_queue_count; k++)
|
|
{
|
|
volatile uint8_t *base = dev_interface->regs+dev_interface->rx_cpl_queue_offset+k*dev_interface->rx_cpl_queue_stride;
|
|
|
|
uint64_t base_addr = (uint64_t)mqnic_reg_read32(base, MQNIC_CPL_QUEUE_BASE_ADDR_REG) + ((uint64_t)mqnic_reg_read32(base, MQNIC_CPL_QUEUE_BASE_ADDR_REG+4) << 32);
|
|
uint8_t active = (mqnic_reg_read32(base, MQNIC_CPL_QUEUE_ACTIVE_LOG_SIZE_REG) & MQNIC_CPL_QUEUE_ACTIVE_MASK) != 0;
|
|
uint8_t log_queue_size = mqnic_reg_read32(base, MQNIC_CPL_QUEUE_ACTIVE_LOG_SIZE_REG) & 0xff;
|
|
uint8_t armed = (mqnic_reg_read32(base, MQNIC_CPL_QUEUE_INTERRUPT_INDEX_REG) & MQNIC_CPL_QUEUE_ARM_MASK) != 0;
|
|
uint8_t continuous = (mqnic_reg_read32(base, MQNIC_CPL_QUEUE_INTERRUPT_INDEX_REG) & MQNIC_CPL_QUEUE_CONT_MASK) != 0;
|
|
uint32_t interrupt_index = mqnic_reg_read32(base, MQNIC_CPL_QUEUE_INTERRUPT_INDEX_REG) & 0xffff;
|
|
uint32_t head_ptr = mqnic_reg_read32(base, MQNIC_CPL_QUEUE_HEAD_PTR_REG);
|
|
uint32_t tail_ptr = mqnic_reg_read32(base, MQNIC_CPL_QUEUE_TAIL_PTR_REG);
|
|
uint32_t occupancy = (head_ptr - tail_ptr) & 0xffff;
|
|
|
|
printf("RXCQ %4d 0x%016lx %d %2d %d %d %4d %6d %6d %6d\n", k, base_addr, active, log_queue_size, armed, continuous, interrupt_index, head_ptr, tail_ptr, occupancy);
|
|
}
|
|
|
|
printf("Event queue info\n");
|
|
printf(" Queue Base Address E LS A C Int Head Tail Len\n");
|
|
for (int k = 0; k < dev_interface->event_queue_count; k++)
|
|
{
|
|
volatile uint8_t *base = dev_interface->regs+dev_interface->event_queue_offset+k*dev_interface->event_queue_stride;
|
|
|
|
uint64_t base_addr = (uint64_t)mqnic_reg_read32(base, MQNIC_CPL_QUEUE_BASE_ADDR_REG) + ((uint64_t)mqnic_reg_read32(base, MQNIC_CPL_QUEUE_BASE_ADDR_REG+4) << 32);
|
|
uint8_t active = (mqnic_reg_read32(base, MQNIC_CPL_QUEUE_ACTIVE_LOG_SIZE_REG) & MQNIC_CPL_QUEUE_ACTIVE_MASK) != 0;
|
|
uint8_t log_queue_size = mqnic_reg_read32(base, MQNIC_CPL_QUEUE_ACTIVE_LOG_SIZE_REG) & 0xff;
|
|
uint8_t armed = (mqnic_reg_read32(base, MQNIC_CPL_QUEUE_INTERRUPT_INDEX_REG) & MQNIC_CPL_QUEUE_ARM_MASK) != 0;
|
|
uint8_t continuous = (mqnic_reg_read32(base, MQNIC_CPL_QUEUE_INTERRUPT_INDEX_REG) & MQNIC_CPL_QUEUE_CONT_MASK) != 0;
|
|
uint32_t interrupt_index = mqnic_reg_read32(base, MQNIC_CPL_QUEUE_INTERRUPT_INDEX_REG) & 0xffff;
|
|
uint32_t head_ptr = mqnic_reg_read32(base, MQNIC_CPL_QUEUE_HEAD_PTR_REG);
|
|
uint32_t tail_ptr = mqnic_reg_read32(base, MQNIC_CPL_QUEUE_TAIL_PTR_REG);
|
|
uint32_t occupancy = (head_ptr - tail_ptr) & 0xffff;
|
|
|
|
printf("EQ %4d 0x%016lx %d %2d %d %d %4d %6d %6d %6d\n", k, base_addr, active, log_queue_size, armed, continuous, interrupt_index, head_ptr, tail_ptr, occupancy);
|
|
}
|
|
|
|
for (int k = 0; k < dev_sched_block->sched_count; k++)
|
|
{
|
|
printf("Scheduler block %d scheduler %d\n", sched_block, k);
|
|
for (int l = 0; l < dev_interface->tx_queue_count; l++)
|
|
{
|
|
printf("Sched %2d queue %4d state: 0x%08x\n", k, l, mqnic_reg_read32(dev_sched_block->sched[k]->regs, l*4));
|
|
}
|
|
}
|
|
|
|
if (dev->stats_rb)
|
|
{
|
|
printf("Statistics counters\n");
|
|
for (int k = 0; k < dev->stats_count; k++)
|
|
{
|
|
printf("Index %d: %lu\n", k, mqnic_stats_read(dev, k));
|
|
}
|
|
}
|
|
|
|
err:
|
|
|
|
mqnic_close(dev);
|
|
|
|
return ret;
|
|
}
|