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50 lines
1.6 KiB
Makefile
50 lines
1.6 KiB
Makefile
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# FPGA settings
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FPGA_PART = xcu280-fsvh2892-2L-e
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FPGA_TOP = fpga
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FPGA_ARCH = virtexuplus
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# Files for synthesis
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SYN_FILES = rtl/fpga.v
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SYN_FILES += rtl/fpga_core.v
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SYN_FILES += rtl/sync_reset.v
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SYN_FILES += rtl/sync_signal.v
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SYN_FILES += rtl/axi_ram.v
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SYN_FILES += rtl/axis_register.v
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SYN_FILES += lib/pcie/rtl/axis_arb_mux.v
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SYN_FILES += lib/pcie/rtl/pcie_us_axil_master.v
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SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma.v
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SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma_rd.v
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SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma_wr.v
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SYN_FILES += lib/pcie/rtl/pcie_tag_manager.v
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SYN_FILES += lib/pcie/rtl/pcie_us_axi_master.v
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SYN_FILES += lib/pcie/rtl/pcie_us_axi_master_rd.v
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SYN_FILES += lib/pcie/rtl/pcie_us_axi_master_wr.v
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SYN_FILES += lib/pcie/rtl/pcie_us_axis_cq_demux.v
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SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
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SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
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SYN_FILES += lib/pcie/rtl/arbiter.v
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SYN_FILES += lib/pcie/rtl/priority_encoder.v
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SYN_FILES += lib/pcie/rtl/pulse_merge.v
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# XDC files
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XDC_FILES = fpga.xdc
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# IP
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#XCI_FILES =
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IP_TCL_FILES = ip/pcie4c_uscale_plus_0.tcl
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include ../common/vivado.mk
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program: $(FPGA_TOP).bit
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echo "open_hw" > program.tcl
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echo "connect_hw_server" >> program.tcl
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echo "open_hw_target" >> program.tcl
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echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
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echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
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echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
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echo "program_hw_devices [current_hw_device]" >> program.tcl
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echo "exit" >> program.tcl
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vivado -nojournal -nolog -mode batch -source program.tcl
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