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533 lines
18 KiB
Python
Executable File
533 lines
18 KiB
Python
Executable File
#!/usr/bin/env python2
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"""
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Copyright (c) 2014 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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"""
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from myhdl import *
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import os
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from Queue import Queue
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import axis_ep
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module = 'axis_rate_limit'
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srcs = []
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srcs.append("../rtl/%s.v" % module)
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srcs.append("test_%s.v" % module)
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src = ' '.join(srcs)
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build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
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def dut_axis_rate_limit(clk,
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rst,
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current_test,
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input_axis_tdata,
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input_axis_tvalid,
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input_axis_tready,
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input_axis_tlast,
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input_axis_tuser,
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output_axis_tdata,
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output_axis_tvalid,
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output_axis_tready,
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output_axis_tlast,
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output_axis_tuser,
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rate_num,
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rate_denom,
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rate_by_frame):
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if os.system(build_cmd):
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raise Exception("Error running build command")
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return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
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clk=clk,
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rst=rst,
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current_test=current_test,
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input_axis_tdata=input_axis_tdata,
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input_axis_tvalid=input_axis_tvalid,
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input_axis_tready=input_axis_tready,
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input_axis_tlast=input_axis_tlast,
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input_axis_tuser=input_axis_tuser,
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output_axis_tdata=output_axis_tdata,
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output_axis_tvalid=output_axis_tvalid,
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output_axis_tready=output_axis_tready,
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output_axis_tlast=output_axis_tlast,
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output_axis_tuser=output_axis_tuser,
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rate_num=rate_num,
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rate_denom=rate_denom,
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rate_by_frame=rate_by_frame)
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def bench():
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# Inputs
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clk = Signal(bool(0))
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rst = Signal(bool(0))
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current_test = Signal(intbv(0)[8:])
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input_axis_tdata = Signal(intbv(0)[8:])
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input_axis_tvalid = Signal(bool(0))
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input_axis_tlast = Signal(bool(0))
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input_axis_tuser = Signal(bool(0))
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output_axis_tready = Signal(bool(0))
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rate_num = Signal(intbv(0)[8:])
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rate_denom = Signal(intbv(0)[8:])
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rate_by_frame = Signal(bool(0))
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# Outputs
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input_axis_tready = Signal(bool(0))
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output_axis_tdata = Signal(intbv(0)[8:])
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output_axis_tvalid = Signal(bool(0))
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output_axis_tlast = Signal(bool(0))
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output_axis_tuser = Signal(bool(0))
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# sources and sinks
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source_queue = Queue()
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source_pause = Signal(bool(0))
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sink_queue = Queue()
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sink_pause = Signal(bool(0))
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source = axis_ep.AXIStreamSource(clk,
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rst,
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tdata=input_axis_tdata,
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tvalid=input_axis_tvalid,
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tready=input_axis_tready,
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tlast=input_axis_tlast,
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tuser=input_axis_tuser,
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fifo=source_queue,
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pause=source_pause,
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name='source')
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sink = axis_ep.AXIStreamSink(clk,
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rst,
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tdata=output_axis_tdata,
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tvalid=output_axis_tvalid,
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tready=output_axis_tready,
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tlast=output_axis_tlast,
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tuser=output_axis_tuser,
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fifo=sink_queue,
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pause=sink_pause,
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name='sink')
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# DUT
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dut = dut_axis_rate_limit(clk,
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rst,
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current_test,
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input_axis_tdata,
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input_axis_tvalid,
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input_axis_tready,
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input_axis_tlast,
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input_axis_tuser,
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output_axis_tdata,
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output_axis_tvalid,
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output_axis_tready,
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output_axis_tlast,
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output_axis_tuser,
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rate_num,
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rate_denom,
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rate_by_frame)
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@always(delay(4))
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def clkgen():
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clk.next = not clk
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reset_stats = Signal(bool(False))
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cur_frame = Signal(bool(False))
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tick_count = Signal(intbv(0))
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byte_count = Signal(intbv(0))
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frame_count = Signal(intbv(0))
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@always(clk.posedge)
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def monitor():
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ctc = int(tick_count)
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cbc = int(byte_count)
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cfc = int(frame_count)
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if reset_stats:
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ctc = 0
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cbc = 0
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cfc = 0
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reset_stats.next = 0
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ctc += 1
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if output_axis_tready and output_axis_tvalid:
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cbc += 1
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if output_axis_tlast:
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cur_frame.next = False
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elif not cur_frame:
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cfc += 1
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cur_frame.next = True
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tick_count.next = ctc
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byte_count.next = cbc
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frame_count.next = cfc
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@instance
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def check():
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yield delay(100)
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yield clk.posedge
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rst.next = 1
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yield clk.posedge
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rst.next = 0
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yield clk.posedge
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yield delay(100)
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yield clk.posedge
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yield clk.posedge
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rate_num.next = 1
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rate_denom.next = 4
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rate_by_frame.next = 1
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for frame_mode in (True, False):
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print("test frame mode %s" % frame_mode)
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rate_by_frame.next = frame_mode
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rate_num.next = 1
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rate_denom.next = 4
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yield clk.posedge
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print("test 1: test packet")
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current_test.next = 1
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test_frame = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
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'\x5A\x51\x52\x53\x54\x55' +
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'\x80\x00' +
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'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
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source_queue.put(test_frame)
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yield clk.posedge
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while input_axis_tvalid or output_axis_tvalid:
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yield clk.posedge
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while not input_axis_tready:
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yield clk.posedge
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yield clk.posedge
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rx_frame = None
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if not sink_queue.empty():
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rx_frame = sink_queue.get()
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assert rx_frame == test_frame
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yield delay(100)
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yield clk.posedge
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print("test 2: longer packet")
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current_test.next = 2
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test_frame = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
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'\x5A\x51\x52\x53\x54\x55' +
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'\x80\x00' +
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bytearray(range(256)))
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source_queue.put(test_frame)
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yield clk.posedge
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while input_axis_tvalid or output_axis_tvalid:
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yield clk.posedge
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while not input_axis_tready:
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yield clk.posedge
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yield clk.posedge
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rx_frame = None
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if not sink_queue.empty():
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rx_frame = sink_queue.get()
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assert rx_frame == test_frame
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yield clk.posedge
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print("test 3: test packet with pauses")
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current_test.next = 3
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test_frame = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
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'\x5A\x51\x52\x53\x54\x55' +
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'\x80\x00' +
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bytearray(range(256)))
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source_queue.put(test_frame)
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yield clk.posedge
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yield delay(64)
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yield clk.posedge
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source_pause.next = True
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yield delay(32)
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yield clk.posedge
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source_pause.next = False
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yield delay(64)
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yield clk.posedge
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sink_pause.next = True
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yield delay(32)
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yield clk.posedge
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sink_pause.next = False
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while input_axis_tvalid or output_axis_tvalid:
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yield clk.posedge
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while not input_axis_tready:
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yield clk.posedge
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yield clk.posedge
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rx_frame = None
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if not sink_queue.empty():
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rx_frame = sink_queue.get()
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assert rx_frame == test_frame
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yield delay(100)
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yield clk.posedge
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print("test 4: back-to-back packets")
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current_test.next = 4
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test_frame1 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
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'\x5A\x51\x52\x53\x54\x55' +
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'\x80\x00' +
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'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
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test_frame2 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
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'\x5A\x51\x52\x53\x54\x55' +
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'\x80\x00' +
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'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
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source_queue.put(test_frame1)
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source_queue.put(test_frame2)
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yield clk.posedge
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while input_axis_tvalid or output_axis_tvalid:
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yield clk.posedge
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while not input_axis_tready:
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yield clk.posedge
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yield clk.posedge
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rx_frame = None
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if not sink_queue.empty():
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rx_frame = sink_queue.get()
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assert rx_frame == test_frame1
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rx_frame = None
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if not sink_queue.empty():
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rx_frame = sink_queue.get()
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assert rx_frame == test_frame2
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yield delay(100)
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yield clk.posedge
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print("test 5: alternate pause source")
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current_test.next = 5
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test_frame1 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
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'\x5A\x51\x52\x53\x54\x55' +
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'\x80\x00' +
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'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
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test_frame2 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
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'\x5A\x51\x52\x53\x54\x55' +
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'\x80\x00' +
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'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
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source_queue.put(test_frame1)
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source_queue.put(test_frame2)
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yield clk.posedge
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while input_axis_tvalid or output_axis_tvalid:
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source_pause.next = True
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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source_pause.next = False
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yield clk.posedge
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while input_axis_tvalid or output_axis_tvalid:
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yield clk.posedge
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while not input_axis_tready:
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yield clk.posedge
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yield clk.posedge
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rx_frame = None
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if not sink_queue.empty():
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rx_frame = sink_queue.get()
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assert rx_frame == test_frame1
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rx_frame = None
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if not sink_queue.empty():
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rx_frame = sink_queue.get()
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assert rx_frame == test_frame2
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yield delay(100)
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yield clk.posedge
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print("test 6: alternate pause sink")
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current_test.next = 6
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test_frame1 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
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'\x5A\x51\x52\x53\x54\x55' +
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'\x80\x00' +
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'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
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test_frame2 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
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'\x5A\x51\x52\x53\x54\x55' +
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'\x80\x00' +
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'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
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source_queue.put(test_frame1)
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source_queue.put(test_frame2)
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yield clk.posedge
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while input_axis_tvalid or output_axis_tvalid:
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sink_pause.next = True
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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sink_pause.next = False
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yield clk.posedge
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while input_axis_tvalid or output_axis_tvalid:
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yield clk.posedge
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while not input_axis_tready:
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yield clk.posedge
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yield clk.posedge
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rx_frame = None
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if not sink_queue.empty():
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rx_frame = sink_queue.get()
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assert rx_frame == test_frame1
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rx_frame = None
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if not sink_queue.empty():
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rx_frame = sink_queue.get()
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assert rx_frame == test_frame2
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yield delay(100)
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yield clk.posedge
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print("test 7: tuser assert")
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current_test.next = 7
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test_frame = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
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'\x5A\x51\x52\x53\x54\x55' +
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'\x80\x00' +
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'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
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test_frame.user = 1
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source_queue.put(test_frame)
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yield clk.posedge
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while input_axis_tvalid or output_axis_tvalid:
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yield clk.posedge
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while not input_axis_tready:
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yield clk.posedge
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yield clk.posedge
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rx_frame = None
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if not sink_queue.empty():
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rx_frame = sink_queue.get()
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assert rx_frame == test_frame
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assert rx_frame.user[-1]
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yield delay(100)
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yield clk.posedge
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print("test 8: various lengths and delays")
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current_test.next = 8
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for rate in ((1,1), (1,2), (1,10), (2,3)):
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print("test 8 rate %d / %d" % rate)
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rate_num.next = rate[0]
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rate_denom.next = rate[1]
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reset_stats.next = 1
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yield clk.posedge
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start_time = now()
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lens = [32, 48, 64, 96, 128, 256]
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test_frame = []
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for i in range(len(lens)):
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test_frame.append(axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
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'\x5A\x51\x52\x53\x54\x55' +
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'\x80\x00' +
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bytearray(range(lens[i]))))
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for f in test_frame:
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source_queue.put(f)
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yield clk.posedge
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yield clk.posedge
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while input_axis_tvalid or output_axis_tvalid:
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yield clk.posedge
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while not input_axis_tready:
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yield clk.posedge
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stop_time = now()
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rx_frame = []
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for i in range(len(lens)):
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if not sink_queue.empty():
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rx_frame.append(sink_queue.get())
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assert len(rx_frame) == len(test_frame)
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for i in range(len(lens)):
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assert rx_frame[i] == test_frame[i]
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cycle = (stop_time - start_time) / 8
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print("cycles %d" % cycle)
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print("tick count %d" % tick_count)
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print("byte count %d" % byte_count)
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print("frame count %d" % frame_count)
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assert tick_count == cycle
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assert byte_count == sum(len(f.data) for f in test_frame)
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assert frame_count == len(test_frame)
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test_rate = 1.0 * rate_num / rate_denom
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meas_rate = 1.0 * byte_count / tick_count
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error = (test_rate - meas_rate) / test_rate
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print("test rate %f" % test_rate)
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print("meas rate %f" % meas_rate)
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|
print("error %f%%" % (error*100))
|
|
|
|
assert abs(error) < 0.1
|
|
|
|
yield delay(100)
|
|
|
|
raise StopSimulation
|
|
|
|
return dut, source, sink, clkgen, monitor, check
|
|
|
|
def test_bench():
|
|
os.chdir(os.path.dirname(os.path.abspath(__file__)))
|
|
sim = Simulation(bench())
|
|
sim.run()
|
|
|
|
if __name__ == '__main__':
|
|
print("Running test...")
|
|
test_bench()
|
|
|