mirror of
https://github.com/corundum/corundum.git
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537 lines
18 KiB
Verilog
537 lines
18 KiB
Verilog
/*
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Copyright (c) 2021 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* FPGA top-level module
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*/
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module fpga (
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/*
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* Clock: 300 MHz
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*/
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input wire usr_refclk0,
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/*
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* GPIO
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*/
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output wire [1:0] led_user_grn,
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output wire [1:0] led_user_red,
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output wire [3:0] led_qsfp,
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/*
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* PCIe: gen 3 x16
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*/
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output wire [15:0] pcie_tx,
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input wire [15:0] pcie_rx,
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input wire pcie_refclk,
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input wire pcie_perstn
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);
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parameter SEG_COUNT = 2;
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parameter SEG_DATA_WIDTH = 256;
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parameter SEG_EMPTY_WIDTH = $clog2(SEG_DATA_WIDTH/32);
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parameter TX_SEQ_NUM_WIDTH = 6;
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parameter PCIE_TAG_COUNT = 256;
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parameter BAR0_APERTURE = 24;
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parameter BAR2_APERTURE = 24;
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parameter BAR4_APERTURE = 16;
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// Clock and reset
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wire ninit_done;
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reset_release reset_release_inst (
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.ninit_done (ninit_done)
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);
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wire clk_100mhz = usr_refclk0;
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wire rst_100mhz;
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sync_reset #(
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.N(20)
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)
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sync_reset_100mhz_inst (
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.clk(clk_100mhz),
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.rst(ninit_done),
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.out(rst_100mhz)
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);
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wire coreclkout_hip;
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wire reset_status;
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wire clk = coreclkout_hip;
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wire rst = reset_status;
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wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] rx_st_data;
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wire [SEG_COUNT*SEG_EMPTY_WIDTH-1:0] rx_st_empty;
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wire [SEG_COUNT-1:0] rx_st_sop;
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wire [SEG_COUNT-1:0] rx_st_eop;
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wire [SEG_COUNT-1:0] rx_st_valid;
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wire rx_st_ready;
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wire [SEG_COUNT-1:0] rx_st_vf_active = 0;
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wire [SEG_COUNT*3-1:0] rx_st_func_num = 0;
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wire [SEG_COUNT*11-1:0] rx_st_vf_num = 0;
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wire [SEG_COUNT*3-1:0] rx_st_bar_range;
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wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] tx_st_data;
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wire [SEG_COUNT-1:0] tx_st_sop;
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wire [SEG_COUNT-1:0] tx_st_eop;
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wire [SEG_COUNT-1:0] tx_st_valid;
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wire tx_st_ready;
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wire [SEG_COUNT-1:0] tx_st_err;
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wire [7:0] tx_ph_cdts;
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wire [11:0] tx_pd_cdts;
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wire [7:0] tx_nph_cdts;
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wire [11:0] tx_npd_cdts;
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wire [7:0] tx_cplh_cdts;
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wire [11:0] tx_cpld_cdts;
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wire [SEG_COUNT-1:0] tx_hdr_cdts_consumed;
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wire [SEG_COUNT-1:0] tx_data_cdts_consumed;
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wire [SEG_COUNT*2-1:0] tx_cdts_type;
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wire [SEG_COUNT*1-1:0] tx_cdts_data_value;
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wire [31:0] tl_cfg_ctl;
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wire [4:0] tl_cfg_add;
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wire [1:0] tl_cfg_func;
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pcie pcie_hip_inst (
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.refclk (pcie_refclk),
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.coreclkout_hip (coreclkout_hip),
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.npor (!rst_100mhz),
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.pin_perst (pcie_perstn),
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.reset_status (reset_status),
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.serdes_pll_locked (),
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.pld_core_ready (1'b1),
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.pld_clk_inuse (),
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.testin_zero (),
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.clr_st (),
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.ninit_done (ninit_done),
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.rx_st_ready (rx_st_ready),
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.rx_st_sop (rx_st_sop),
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.rx_st_eop (rx_st_eop),
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.rx_st_data (rx_st_data),
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.rx_st_valid (rx_st_valid),
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.rx_st_empty (rx_st_empty),
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.tx_st_sop (tx_st_sop),
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.tx_st_eop (tx_st_eop),
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.tx_st_data (tx_st_data),
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.tx_st_valid (tx_st_valid),
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.tx_st_err (tx_st_err),
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.tx_st_ready (tx_st_ready),
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.rx_st_bar_range (rx_st_bar_range),
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.tx_cdts_type (tx_cdts_type),
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.tx_data_cdts_consumed (tx_data_cdts_consumed),
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.tx_hdr_cdts_consumed (tx_hdr_cdts_consumed),
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.tx_cdts_data_value (tx_cdts_data_value),
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.tx_cpld_cdts (tx_cpld_cdts),
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.tx_pd_cdts (tx_pd_cdts),
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.tx_npd_cdts (tx_npd_cdts),
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.tx_cplh_cdts (tx_cplh_cdts),
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.tx_ph_cdts (tx_ph_cdts),
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.tx_nph_cdts (tx_nph_cdts),
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.app_msi_req (1'b0),
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.app_msi_ack (),
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.app_msi_tc (3'd0),
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.app_msi_num (5'd0),
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.app_int_sts (4'd0),
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.app_msi_func_num (2'd0),
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.int_status (),
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.int_status_common (),
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.derr_cor_ext_rpl (),
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.derr_rpl (),
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.derr_cor_ext_rcv (),
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.derr_uncor_ext_rcv (),
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.rx_par_err (),
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.tx_par_err (),
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.ltssmstate (),
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.link_up (),
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.lane_act (),
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.tl_cfg_func (tl_cfg_func),
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.tl_cfg_add (tl_cfg_add),
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.tl_cfg_ctl (tl_cfg_ctl),
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.app_err_valid (0),
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.app_err_hdr (0),
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.app_err_info (0),
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.app_err_func_num (0),
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.test_in (0),
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.simu_mode_pipe (0),
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.currentspeed (),
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.sim_pipe_pclk_in (1'b0),
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.sim_pipe_rate (),
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.sim_ltssmstate (),
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.txdata0 (),
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.txdata1 (),
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.txdata2 (),
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.txdata3 (),
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.txdata4 (),
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.txdata5 (),
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.txdata6 (),
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.txdata7 (),
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.txdatak0 (),
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.txdatak1 (),
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.txdatak2 (),
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.txdatak3 (),
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.txdatak4 (),
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.txdatak5 (),
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.txdatak6 (),
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.txdatak7 (),
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.txcompl0 (),
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.txcompl1 (),
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.txcompl2 (),
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.txcompl3 (),
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.txcompl4 (),
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.txcompl5 (),
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.txcompl6 (),
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.txcompl7 (),
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.txelecidle0 (),
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.txelecidle1 (),
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.txelecidle2 (),
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.txelecidle3 (),
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.txelecidle4 (),
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.txelecidle5 (),
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.txelecidle6 (),
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.txelecidle7 (),
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.txdetectrx0 (),
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.txdetectrx1 (),
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.txdetectrx2 (),
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.txdetectrx3 (),
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.txdetectrx4 (),
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.txdetectrx5 (),
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.txdetectrx6 (),
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.txdetectrx7 (),
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.powerdown0 (),
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.powerdown1 (),
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.powerdown2 (),
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.powerdown3 (),
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.powerdown4 (),
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.powerdown5 (),
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.powerdown6 (),
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.powerdown7 (),
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.txmargin0 (),
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.txmargin1 (),
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.txmargin2 (),
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.txmargin3 (),
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.txmargin4 (),
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.txmargin5 (),
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.txmargin6 (),
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.txmargin7 (),
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.txdeemph0 (),
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.txdeemph1 (),
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.txdeemph2 (),
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.txdeemph3 (),
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.txdeemph4 (),
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.txdeemph5 (),
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.txdeemph6 (),
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.txdeemph7 (),
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.txswing0 (),
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.txswing1 (),
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.txswing2 (),
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.txswing3 (),
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.txswing4 (),
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.txswing5 (),
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.txswing6 (),
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.txswing7 (),
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.txsynchd0 (),
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.txsynchd1 (),
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.txsynchd2 (),
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.txsynchd3 (),
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.txsynchd4 (),
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.txsynchd5 (),
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.txsynchd6 (),
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.txsynchd7 (),
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.txblkst0 (),
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.txblkst1 (),
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.txblkst2 (),
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.txblkst3 (),
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.txblkst4 (),
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.txblkst5 (),
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.txblkst6 (),
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.txblkst7 (),
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.txdataskip0 (),
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.txdataskip1 (),
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.txdataskip2 (),
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.txdataskip3 (),
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.txdataskip4 (),
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.txdataskip5 (),
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.txdataskip6 (),
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.txdataskip7 (),
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.rate0 (),
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.rate1 (),
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.rate2 (),
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.rate3 (),
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.rate4 (),
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.rate5 (),
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.rate6 (),
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.rate7 (),
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.rxpolarity0 (),
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.rxpolarity1 (),
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.rxpolarity2 (),
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.rxpolarity3 (),
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.rxpolarity4 (),
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.rxpolarity5 (),
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.rxpolarity6 (),
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.rxpolarity7 (),
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.currentrxpreset0 (),
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.currentrxpreset1 (),
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.currentrxpreset2 (),
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.currentrxpreset3 (),
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.currentrxpreset4 (),
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.currentrxpreset5 (),
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.currentrxpreset6 (),
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.currentrxpreset7 (),
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.currentcoeff0 (),
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.currentcoeff1 (),
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.currentcoeff2 (),
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.currentcoeff3 (),
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.currentcoeff4 (),
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.currentcoeff5 (),
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.currentcoeff6 (),
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.currentcoeff7 (),
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.rxeqeval0 (),
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.rxeqeval1 (),
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.rxeqeval2 (),
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.rxeqeval3 (),
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.rxeqeval4 (),
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.rxeqeval5 (),
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.rxeqeval6 (),
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.rxeqeval7 (),
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.rxeqinprogress0 (),
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.rxeqinprogress1 (),
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.rxeqinprogress2 (),
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.rxeqinprogress3 (),
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.rxeqinprogress4 (),
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.rxeqinprogress5 (),
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.rxeqinprogress6 (),
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.rxeqinprogress7 (),
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.invalidreq0 (),
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.invalidreq1 (),
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.invalidreq2 (),
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.invalidreq3 (),
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.invalidreq4 (),
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.invalidreq5 (),
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.invalidreq6 (),
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.invalidreq7 (),
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.rxdata0 (32'd0),
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.rxdata1 (32'd0),
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.rxdata2 (32'd0),
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.rxdata3 (32'd0),
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.rxdata4 (32'd0),
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.rxdata5 (32'd0),
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.rxdata6 (32'd0),
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.rxdata7 (32'd0),
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.rxdatak0 (4'd0),
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.rxdatak1 (4'd0),
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.rxdatak2 (4'd0),
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.rxdatak3 (4'd0),
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.rxdatak4 (4'd0),
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.rxdatak5 (4'd0),
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.rxdatak6 (4'd0),
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.rxdatak7 (4'd0),
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.phystatus0 (1'b0),
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.phystatus1 (1'b0),
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.phystatus2 (1'b0),
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.phystatus3 (1'b0),
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.phystatus4 (1'b0),
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.phystatus5 (1'b0),
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.phystatus6 (1'b0),
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.phystatus7 (1'b0),
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.rxvalid0 (1'b0),
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.rxvalid1 (1'b0),
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.rxvalid2 (1'b0),
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.rxvalid3 (1'b0),
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.rxvalid4 (1'b0),
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.rxvalid5 (1'b0),
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.rxvalid6 (1'b0),
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.rxvalid7 (1'b0),
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.rxstatus0 (3'd0),
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.rxstatus1 (3'd0),
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.rxstatus2 (3'd0),
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.rxstatus3 (3'd0),
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.rxstatus4 (3'd0),
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.rxstatus5 (3'd0),
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.rxstatus6 (3'd0),
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.rxstatus7 (3'd0),
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.rxelecidle0 (1'b0),
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.rxelecidle1 (1'b0),
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.rxelecidle2 (1'b0),
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.rxelecidle3 (1'b0),
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.rxelecidle4 (1'b0),
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.rxelecidle5 (1'b0),
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.rxelecidle6 (1'b0),
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.rxelecidle7 (1'b0),
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.rxsynchd0 (2'd0),
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.rxsynchd1 (2'd0),
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.rxsynchd2 (2'd0),
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.rxsynchd3 (2'd0),
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.rxsynchd4 (2'd0),
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.rxsynchd5 (2'd0),
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.rxsynchd6 (2'd0),
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.rxsynchd7 (2'd0),
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.rxblkst0 (1'b0),
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.rxblkst1 (1'b0),
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.rxblkst2 (1'b0),
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.rxblkst3 (1'b0),
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.rxblkst4 (1'b0),
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.rxblkst5 (1'b0),
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.rxblkst6 (1'b0),
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.rxblkst7 (1'b0),
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.rxdataskip0 (1'b0),
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.rxdataskip1 (1'b0),
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.rxdataskip2 (1'b0),
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.rxdataskip3 (1'b0),
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.rxdataskip4 (1'b0),
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.rxdataskip5 (1'b0),
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.rxdataskip6 (1'b0),
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.rxdataskip7 (1'b0),
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.dirfeedback0 (6'd0),
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.dirfeedback1 (6'd0),
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.dirfeedback2 (6'd0),
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.dirfeedback3 (6'd0),
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.dirfeedback4 (6'd0),
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.dirfeedback5 (6'd0),
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.dirfeedback6 (6'd0),
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.dirfeedback7 (6'd0),
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.sim_pipe_mask_tx_pll_lock (1'b0),
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.rx_in0 (pcie_rx[0]),
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.rx_in1 (pcie_rx[1]),
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.rx_in2 (pcie_rx[2]),
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.rx_in3 (pcie_rx[3]),
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.rx_in4 (pcie_rx[4]),
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.rx_in5 (pcie_rx[5]),
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.rx_in6 (pcie_rx[6]),
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.rx_in7 (pcie_rx[7]),
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.rx_in8 (pcie_rx[8]),
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.rx_in9 (pcie_rx[9]),
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.rx_in10 (pcie_rx[10]),
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.rx_in11 (pcie_rx[11]),
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.rx_in12 (pcie_rx[12]),
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.rx_in13 (pcie_rx[13]),
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.rx_in14 (pcie_rx[14]),
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.rx_in15 (pcie_rx[15]),
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.tx_out0 (pcie_tx[0]),
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.tx_out1 (pcie_tx[1]),
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.tx_out2 (pcie_tx[2]),
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.tx_out3 (pcie_tx[3]),
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.tx_out4 (pcie_tx[4]),
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.tx_out5 (pcie_tx[5]),
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.tx_out6 (pcie_tx[6]),
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.tx_out7 (pcie_tx[7]),
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.tx_out8 (pcie_tx[8]),
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.tx_out9 (pcie_tx[9]),
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.tx_out10 (pcie_tx[10]),
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.tx_out11 (pcie_tx[11]),
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.tx_out12 (pcie_tx[12]),
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.tx_out13 (pcie_tx[13]),
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.tx_out14 (pcie_tx[14]),
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.tx_out15 (pcie_tx[15]),
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.pm_linkst_in_l1 (),
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.pm_linkst_in_l0s (),
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.pm_state (),
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.pm_dstate (),
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.apps_pm_xmt_pme (0),
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.apps_ready_entr_l23 (0),
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.apps_pm_xmt_turnoff (0),
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.app_init_rst (0),
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.app_xfer_pending (0)
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);
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fpga_core #(
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.SEG_COUNT(SEG_COUNT),
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.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
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.SEG_EMPTY_WIDTH(SEG_EMPTY_WIDTH),
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.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
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.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
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.BAR0_APERTURE(BAR0_APERTURE),
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.BAR2_APERTURE(BAR2_APERTURE),
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.BAR4_APERTURE(BAR4_APERTURE)
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)
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fpga_core_inst (
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.clk(clk),
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.rst(rst),
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/*
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* GPIO
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*/
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.led_user_grn(led_user_grn),
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.led_user_red(led_user_red),
|
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.led_qsfp(led_qsfp),
|
|
|
|
/*
|
|
* H-tile RX AVST interface
|
|
*/
|
|
.rx_st_data(rx_st_data),
|
|
.rx_st_empty(rx_st_empty),
|
|
.rx_st_sop(rx_st_sop),
|
|
.rx_st_eop(rx_st_eop),
|
|
.rx_st_valid(rx_st_valid),
|
|
.rx_st_ready(rx_st_ready),
|
|
.rx_st_vf_active(rx_st_vf_active),
|
|
.rx_st_func_num(rx_st_func_num),
|
|
.rx_st_vf_num(rx_st_vf_num),
|
|
.rx_st_bar_range(rx_st_bar_range),
|
|
|
|
/*
|
|
* H-tile TX AVST interface
|
|
*/
|
|
.tx_st_data(tx_st_data),
|
|
.tx_st_sop(tx_st_sop),
|
|
.tx_st_eop(tx_st_eop),
|
|
.tx_st_valid(tx_st_valid),
|
|
.tx_st_ready(tx_st_ready),
|
|
.tx_st_err(tx_st_err),
|
|
|
|
/*
|
|
* H-tile TX flow control
|
|
*/
|
|
.tx_ph_cdts(tx_ph_cdts),
|
|
.tx_pd_cdts(tx_pd_cdts),
|
|
.tx_nph_cdts(tx_nph_cdts),
|
|
.tx_npd_cdts(tx_npd_cdts),
|
|
.tx_cplh_cdts(tx_cplh_cdts),
|
|
.tx_cpld_cdts(tx_cpld_cdts),
|
|
.tx_hdr_cdts_consumed(tx_hdr_cdts_consumed),
|
|
.tx_data_cdts_consumed(tx_data_cdts_consumed),
|
|
.tx_cdts_type(tx_cdts_type),
|
|
.tx_cdts_data_value(tx_cdts_data_value),
|
|
|
|
/*
|
|
* H-tile configuration interface
|
|
*/
|
|
.tl_cfg_ctl(tl_cfg_ctl),
|
|
.tl_cfg_add(tl_cfg_add),
|
|
.tl_cfg_func(tl_cfg_func)
|
|
);
|
|
|
|
endmodule
|
|
|
|
`resetall
|