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134 lines
3.6 KiB
Verilog
134 lines
3.6 KiB
Verilog
/*
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Copyright (c) 2015-2017 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* Testbench for axis_xgmii_tx_32
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*/
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module test_axis_xgmii_tx_32;
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// Parameters
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parameter DATA_WIDTH = 32;
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parameter KEEP_WIDTH = (DATA_WIDTH/8);
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parameter CTRL_WIDTH = (DATA_WIDTH/8);
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parameter ENABLE_PADDING = 1;
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parameter ENABLE_DIC = 1;
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parameter MIN_FRAME_LENGTH = 64;
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parameter PTP_TS_ENABLE = 0;
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parameter PTP_TS_WIDTH = 96;
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parameter PTP_TAG_ENABLE = PTP_TS_ENABLE;
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parameter PTP_TAG_WIDTH = 16;
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parameter USER_WIDTH = (PTP_TAG_ENABLE ? PTP_TAG_WIDTH : 0) + 1;
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// Inputs
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reg clk = 0;
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reg rst = 0;
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reg [7:0] current_test = 0;
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reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
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reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
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reg s_axis_tvalid = 0;
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reg s_axis_tlast = 0;
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reg [USER_WIDTH-1:0] s_axis_tuser = 0;
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reg [PTP_TS_WIDTH-1:0] ptp_ts = 0;
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reg [7:0] ifg_delay = 0;
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// Outputs
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wire s_axis_tready;
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wire [DATA_WIDTH-1:0] xgmii_txd;
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wire [CTRL_WIDTH-1:0] xgmii_txc;
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wire [PTP_TS_WIDTH-1:0] m_axis_ptp_ts;
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wire [PTP_TAG_WIDTH-1:0] m_axis_ptp_ts_tag;
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wire m_axis_ptp_ts_valid;
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wire start_packet;
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wire error_underflow;
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initial begin
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// myhdl integration
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$from_myhdl(
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clk,
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rst,
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current_test,
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s_axis_tdata,
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s_axis_tkeep,
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s_axis_tvalid,
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s_axis_tlast,
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s_axis_tuser,
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ptp_ts,
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ifg_delay
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);
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$to_myhdl(
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s_axis_tready,
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xgmii_txd,
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xgmii_txc,
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m_axis_ptp_ts,
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m_axis_ptp_ts_tag,
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m_axis_ptp_ts_valid,
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start_packet,
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error_underflow
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);
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// dump file
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$dumpfile("test_axis_xgmii_tx_32.lxt");
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$dumpvars(0, test_axis_xgmii_tx_32);
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end
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axis_xgmii_tx_32 #(
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.DATA_WIDTH(DATA_WIDTH),
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.KEEP_WIDTH(KEEP_WIDTH),
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.CTRL_WIDTH(CTRL_WIDTH),
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.ENABLE_PADDING(ENABLE_PADDING),
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.ENABLE_DIC(ENABLE_DIC),
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.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
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.PTP_TS_ENABLE(PTP_TS_ENABLE),
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.PTP_TS_WIDTH(PTP_TS_WIDTH),
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.PTP_TAG_ENABLE(PTP_TAG_ENABLE),
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.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
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.USER_WIDTH(USER_WIDTH)
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)
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UUT (
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.clk(clk),
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.rst(rst),
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.s_axis_tdata(s_axis_tdata),
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.s_axis_tkeep(s_axis_tkeep),
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.s_axis_tvalid(s_axis_tvalid),
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.s_axis_tready(s_axis_tready),
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.s_axis_tlast(s_axis_tlast),
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.s_axis_tuser(s_axis_tuser),
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.xgmii_txd(xgmii_txd),
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.xgmii_txc(xgmii_txc),
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.ptp_ts(ptp_ts),
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.m_axis_ptp_ts(m_axis_ptp_ts),
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.m_axis_ptp_ts_tag(m_axis_ptp_ts_tag),
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.m_axis_ptp_ts_valid(m_axis_ptp_ts_valid),
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.ifg_delay(ifg_delay),
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.start_packet(start_packet),
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.error_underflow(error_underflow)
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);
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endmodule
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